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* Resolve conflicts involving dead vector lanes for -new-coalescer.Jakob Stoklund Olesen2012-09-191-9/+155
| | | | | | | | | | | | | | | | | | | | | A common coalescing conflict in vector code is lane insertion: %dst = FOO %src = BAR %dst:ssub0 = COPY %src The live range of %src interferes with the ssub0 lane of %dst, but that lane is never read after %src would have clobbered it. That makes it safe to merge the live ranges and eliminate the COPY: %dst = FOO %dst:ssub0 = BAR This patch teaches the new coalescer to resolve conflicts where dead vector lanes would be clobbered, at least as long as the clobbered vector lanes don't escape the basic block. llvm-svn: 164250
* This patch adds memory support functions which will later be used to ↵Andrew Kaylor2012-09-193-90/+325
| | | | | | implement section-specific protection handling in MCJIT. llvm-svn: 164249
* Add support for macro parameters/arguments delimited by spaces,Preston Gurd2012-09-193-25/+133
| | | | | | | | | | to improve compatibility with GNU as. Based on a patch by PaX Team. Fixed assertion failures on non-Darwin and added additional test cases. llvm-svn: 164248
* Add support for accessing an MDNode's operands via the C binding. Patch byDuncan Sands2012-09-191-0/+13
| | | | | | Anthony Bryant. llvm-svn: 164247
* Support default parameters/arguments for assembler macros.Preston Gurd2012-09-191-7/+31
| | | | | | | | This patch is based on the one by PaX Team. Patch by Andy Zhang! llvm-svn: 164246
* Enhance unmatched '.endr' directive error message in assembler.Preston Gurd2012-09-191-1/+1
| | | | | | | | The directive can be matched with directives other than '.rept' Patch by Andy Zhang! llvm-svn: 164245
* Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao2012-09-191-176/+140
| | | | | | | | | | | - Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. llvm-svn: 164243
* Renaming functions to match coding style guidelinesMichael Ilseman2012-09-191-4/+4
| | | | llvm-svn: 164238
* Doxygen-ify commentsMichael Ilseman2012-09-191-8/+16
| | | | llvm-svn: 164235
* Put the * and & next to the variable, rather than the type.Michael Ilseman2012-09-191-73/+73
| | | | llvm-svn: 164232
* GCC doesn't understand that OrigAliasResult having a value is correlated withDuncan Sands2012-09-191-1/+1
| | | | | | | ArePhisAssumedNoAlias, and warns that OrigAliasResult may be used uninitialized. Pacify GCC. llvm-svn: 164229
* Small structs for PPC64 SVR4 must be passed right-justified in registers.Bill Schmidt2012-09-192-61/+143
| | | | | | | | | | | | | | | lib/Target/PowerPC/PPCISelLowering.{h,cpp} Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4. Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4. Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4. Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4. Rename LowerCall_SVR4 to LowerCall_32SVR4. Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4. test/CodeGen/PowerPC/structsinregs.ll New test. llvm-svn: 164228
* SimplifyCFG: Don't generate invalid code for switch used to initializeHans Wennborg2012-09-191-9/+8
| | | | | | | | | | | | | two variables where the first variable is returned and the second ignored. I don't think this occurs in practice (other passes should have cleaned up the unused phi node), but it should still be handled correctly. Also make the logic for determining if we should return early less sketchy. llvm-svn: 164225
* IntegerDivision: Style cleanups, avoid warning about mixing || and && ↵Benjamin Kramer2012-09-191-7/+5
| | | | | | without parens. llvm-svn: 164216
* Prevent inlining of callees which allocate lots of memory into a recursive ↵Nadav Rotem2012-09-191-14/+58
| | | | | | | | | | | | | | | | | | caller. Example: void foo() { ... foo(); // I'm recursive! bar(); } bar() { int a[1000]; // large stack size } rdar://10853263 llvm-svn: 164207
* CodeGenPrep: turn lookup tables into switches for some targets.Hans Wennborg2012-09-191-4/+114
| | | | | | | | | | | | | | | | | | | This is a follow-up from r163302, which added a transformation to SimplifyCFG that turns some switches into loads from lookup tables. It was pointed out that some targets, such as GPUs and deeply embedded targets, might not find this appropriate, but SimplifyCFG doesn't have enough information about the target to decide this. This patch adds the reverse transformation to CodeGenPrep: it turns loads from lookup tables back into switches for targets where we do not build jump tables (assuming these are also the targets where lookup tables are inappropriate). Hopefully we will eventually get to have target information in SimplifyCFG, and then this CodeGenPrep transformation can be removed. llvm-svn: 164206
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-193-22/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* whitespace.Nadav Rotem2012-09-191-9/+0
| | | | llvm-svn: 164203
* Add explicit VEX_L tags to all 256-bit instructions. This will allow us to ↵Craig Topper2012-09-193-240/+254
| | | | | | remove code from the code emitters that examined operands to set the L-bit. llvm-svn: 164202
* De-nest if's and fix mix-upSean Silva2012-09-191-41/+37
| | | | | | | | | | | | | | | | | | Two deeply nested if's obscured that the sense of the conditions was mixed up. Amazingly, TableGen's output is exactly the same even with the sense of the tests fixed; it seems that all of TableGen's conversions are symmetric so that the inverted sense was nonetheless correct "by accident". As such, I couldn't come up with a test case. If there does in fact exist a non-symmetric conversion in TableGen's type system, then a test case should be prepared. Despite the symmetry, both if's are left in place for robustness in the face of future changes. Review by Jakob. llvm-svn: 164195
* Tidy up. Minor formatting.Jim Grosbach2012-09-181-3/+2
| | | | llvm-svn: 164182
* Tidy up. 80 columns.Jim Grosbach2012-09-181-2/+6
| | | | llvm-svn: 164181
* comment typoAndrew Trick2012-09-181-1/+1
| | | | llvm-svn: 164180
* Fix the last crasher I've gotten a reproduction for in SROA. This oneChandler Carruth2012-09-181-0/+2
| | | | | | | | | | | from the dragonegg build bots when we turned on the full version of the pass. Included a much reduced test case for this pesky bug, despite bugpoint's uncooperative behavior. Also, I audited all the similar code I could find and didn't spot any other cases where this mistake cropped up. llvm-svn: 164178
* New utility for expanding integer division for targets that don't support it.Michael Ilseman2012-09-182-0/+307
| | | | | | Implementation derived from compiler-rt's implementation of signed and unsigned integer division. llvm-svn: 164173
* MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648Evan Cheng2012-09-181-2/+4
| | | | llvm-svn: 164169
* Fix the isLocalCall() by checking for linker weakness as well.Roman Divacky2012-09-181-1/+2
| | | | llvm-svn: 164155
* TargetSchedule: cleanup computeOperandLatency logic & diagnostics.Andrew Trick2012-09-181-6/+16
| | | | llvm-svn: 164154
* misched: Make ScheduleDAGInstrs use the TargetSchedule interface.Andrew Trick2012-09-181-16/+14
| | | | llvm-svn: 164153
* Revert r164051.Akira Hatanaka2012-09-181-4/+0
| | | | llvm-svn: 164150
* LSR critical edge splitting fix for PR13756.Andrew Trick2012-09-181-11/+15
| | | | llvm-svn: 164147
* Fix getCommonType in a different way from the way I fixed it whenChandler Carruth2012-09-181-1/+1
| | | | | | | | | | | | working on FCA splitting. Instead of refusing to form a common type when there are uses of a subsection of the alloca as well as a use of the entire alloca, just skip the subsection uses and continue looking for a whole-alloca use with a type that we can use. This produces slightly prettier IR I think, and also fixes the other failure in the test. llvm-svn: 164146
* Fix build for compilers that don't understand injected class names properly.Benjamin Kramer2012-09-181-2/+2
| | | | llvm-svn: 164142
* Avoid symbol name clash when filling TOC.Roman Divacky2012-09-182-3/+14
| | | | | | Patch by Adhemerval Zanella. llvm-svn: 164141
* SROA: Use CRTP for OpSplitter to get rid of virtual dispatch and the ↵Benjamin Kramer2012-09-181-8/+7
| | | | | | virtual-dtor warnings that come with it. llvm-svn: 164140
* On PPC64 emit the environment pointer. Patch by Adhemerval Zanella.Roman Divacky2012-09-181-0/+2
| | | | llvm-svn: 164139
* Optimize local func calls to not emit nop for TOC restoration.Roman Divacky2012-09-181-2/+10
| | | | | | Patch by Adhemerval Zanella. llvm-svn: 164138
* SROA: Replace the member function template contraption for recursively ↵Benjamin Kramer2012-09-181-97/+105
| | | | | | | | splitting aggregates into a real class. No intended functionality change. llvm-svn: 164135
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-1811-43/+61
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* SROA.cpp: Appease msvc.NAKAMURA Takumi2012-09-181-1/+1
| | | | | | ...I don't know why this could appease msvc...baad. llvm-svn: 164130
* LNT builders have picked up new SROA, disable it to get the remaining ↵Benjamin Kramer2012-09-181-1/+1
| | | | | | builders green again. llvm-svn: 164124
* Fix a warning in release builds and a test case I forgot to update withChandler Carruth2012-09-181-0/+1
| | | | | | a fix to getCommonType in the previous patch. llvm-svn: 164120
* Add a major missing piece to the new SROA pass: aggressive splitting ofChandler Carruth2012-09-182-8/+221
| | | | | | | | | | | | | | | | | | | | | | | FCAs. This is essential in order to promote allocas that are used in struct returns by frontends like Clang. The FCA load would block the rest of the pass from firing, resulting is significant regressions with the bullet benchmark in the nightly test suite. Thanks to Duncan for repeated discussions about how best to do this, and to both him and Benjamin for review. This appears to have blocked many places where the pass tries to fire, and so I'm expect somewhat different results with this fix added. As with the last big patch, I'm including a change to enable the SROA by default *temporarily*. Ben is going to remove this as soon as the LNT bots pick up the patch. I'm just trying to get a round of LNT numbers from the stable machines in the lab. NOTE: Four clang tests are expected to fail in the brief window where this is enabled. Sorry for the noise! llvm-svn: 164119
* Fix instcombine to obey requested alignment when merging allocas.Richard Osborne2012-09-181-3/+7
| | | | llvm-svn: 164117
* More domain conversion; convert VFP VMOVS to NEON instructions in more cases ↵James Molloy2012-09-181-13/+56
| | | | | | - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not. llvm-svn: 164114
* Replaced ReInitMCSubtargetInfo with InitMCProcessor.Andrew Trick2012-09-181-14/+15
| | | | | | | | Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. llvm-svn: 164105
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-183-8/+148
| | | | llvm-svn: 164098
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-182-2/+11
| | | | | | model. llvm-svn: 164092
* Mark unimplemented copy constructors and copy assignment operators as ↵Craig Topper2012-09-185-11/+10
| | | | | | LLVM_DELETED_FUNCTION. llvm-svn: 164090
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-182-5/+42
| | | | | | | | | aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 llvm-svn: 164089
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