summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* More accurate header inclusions. NFC.Peter Collingbourne2017-03-282-0/+2
| | | | llvm-svn: 298960
* [AVX-512] Punt on fast-isel of truncates to i1 when AVX512 is enabled.Craig Topper2017-03-281-1/+2
| | | | | | | | | | We should be masking the value and emitting a register copy like we do in non-fast isel. Instead we were just updating the value map and emitting nothing. After r298928 we started seeing cases where we would create a copy from GR8 to GR32 because the source register in a VK1 to GR32 copy was replaced by the GR8 going into a truncate. This fixes PR32451. llvm-svn: 298957
* [PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64Guozhi Wei2017-03-283-19/+37
| | | | | | | | | | In PPCBoolRetToInt bool value is changed to i32 type. On ppc64 it may introduce an extra zero extension for the return value. This patch changes the integer type to i64 to avoid the zero extension on ppc64. This patch fixed PR32442. Differential Revision: https://reviews.llvm.org/D31407 llvm-svn: 298955
* [DAGCombiner] reduce code duplication with local variables; NFCISanjay Patel2017-03-281-21/+21
| | | | llvm-svn: 298954
* LTO: Replace InputFile::Symbol::getFlags() with predicate accessors. NFC.Peter Collingbourne2017-03-281-2/+2
| | | | | | | This makes the predicates independent of the flag representation and makes the code a little easier to read. llvm-svn: 298951
* [DAG] fix formatting; NFCSanjay Patel2017-03-281-8/+8
| | | | llvm-svn: 298950
* [DAGCombiner] remove redundant conditions and duplicated code; NFCISanjay Patel2017-03-281-10/+8
| | | | llvm-svn: 298949
* [AMDGPU] Boost unroll threshold for loops reading local memoryStanislav Mekhanoshin2017-03-281-30/+72
| | | | | | | | | | | | | This is less important than increase threshold for private memory, but still brings performance improvements in a wide range of tests. Unrolling more for local memory serves three purposes: it allows to combine ds operations if offset becomes static, saves registers used for offsets in case of static offsets, and allows better lds latency hiding. Differential Revision: https://reviews.llvm.org/D31412 llvm-svn: 298948
* [AMDGPU] Fix recorded region boundaries in max-occupancy schedulerStanislav Mekhanoshin2017-03-282-17/+7
| | | | | | | | | | This is incorrect to record region boundaries before scheduling, it may change after scheduling. As a result second pass may see less instructions to schedule than it should. Differential Revision: https://reviews.llvm.org/D31434 llvm-svn: 298945
* [DAGCombiner] rename variables in foldAndOfSetCCs for easier reading; NFCISanjay Patel2017-03-281-32/+30
| | | | llvm-svn: 298944
* [X86][MMX] Match MMX fp_to_sint conversions from XMM registersSimon Pilgrim2017-03-282-4/+25
| | | | | | | | | | We currently perform the various fp_to_sint XMM conversion and then transfer to the MMX register (on 32-bit via the stack). This patch improves support for MOVDQ2Q XMM to MMX transfers and adds the XMM->MMX fp_to_sint direct conversion patterns. The SSE2 specifications are the same as for XMM->XMM and XMM->MMX rounding/exceptions/etc. Differential Revision: https://reviews.llvm.org/D30868 llvm-svn: 298943
* Fix crashing on TargetCustom PseudoSourceValuesMatt Arsenault2017-03-281-1/+4
| | | | | | Default to something more reasonable if printCustom isn't implemented. llvm-svn: 298941
* [DAGCombiner] clean up foldAndOfSetCCs; NFCISanjay Patel2017-03-281-77/+75
| | | | | | | | 1. Fix bogus comment. 2. Early exit to reduce indent. 3. Change node pointer param to what it really is: an SDLoc. llvm-svn: 298940
* [IR] Add AllowContract to FastMathFlagsAdam Nemet2017-03-287-0/+17
| | | | | | | | | | | | -ffp-contract=fast does not currently work with LTO because it's passed as a TargetOption to the backend rather than in the IR. This adds it to FastMathFlags. This is toward fixing PR25721 Differential Revision: https://reviews.llvm.org/D31164 llvm-svn: 298939
* [DAGCombiner] add helper function for and-of-setcc folds; NFCSanjay Patel2017-03-281-25/+37
| | | | | | This is just a cut and paste followed by clang-format. Clean up to follow. llvm-svn: 298938
* Add support for -fno-builtin to LTO and ThinLTO to libLTOMehdi Amini2017-03-282-7/+12
| | | | | | | | | | Reviewers: tejohnson, pcc Subscribers: Prazek, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D30791 llvm-svn: 298936
* [AMDGPU] Split -amdgpu-early-inline-all optionStanislav Mekhanoshin2017-03-281-3/+13
| | | | | | | | | | Previously it was covered by the internalization. It turns out we cannot run internalizer in FE, it break separate compilation tests. Thus early inliner gets its own option. Differential Revision: https://reviews.llvm.org/D31429 llvm-svn: 298935
* [x86] use VPMOVMSK to replace memcmp libcalls for 32-byte equalitySanjay Patel2017-03-282-9/+13
| | | | | | | Follow-up to: https://reviews.llvm.org/rL298775 llvm-svn: 298933
* Revert "Dont emit Mapping symbols for sections that contain only data."Weiming Zhao2017-03-283-92/+18
| | | | | | | | It breaks some lld tests. This reverts commit 3a50eea6d9732ab40e9a7aebe6be777b53a8b35c. llvm-svn: 298932
* [SDAG] Deal with deleted node in PromoteIntShiftOpNirav Dave2017-03-281-5/+11
| | | | | | | | | | | | | | | Deal with case that initial node is deleted during dag-combine leading to an assertional failure in promoteIntShiftOp. Fixes PR32420. Reviewers: spatel, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31403 llvm-svn: 298931
* [X86][AVX2] Add support for combining v16i16 shuffles to VPBLENDWSimon Pilgrim2017-03-281-28/+47
| | | | llvm-svn: 298929
* [AVX-512] Fix accidental uses of AH/BH/CH/DH after copies to/from mask registersCraig Topper2017-03-283-53/+106
| | | | | | | | | | | | | | | | We've had several bugs(PR32256, PR32241) recently that resulted from usages of AH/BH/CH/DH either before or after a copy to/from a mask register. This ultimately occurs because we create COPY_TO_REGCLASS with VK1 and GR8. Then in CopyToFromAsymmetricReg in X86InstrInfo we find a 32-bit super register for the GR8 to emit the KMOV with. But as these tests are demonstrating, its possible for the GR8 register to be a high register and we end up doing an accidental extra or insert from bits 15:8. I think the best way forward is to stop making copies directly between mask registers and GR8/GR16. Instead I think we should restrict to only copies between mask registers and GR32/GR64 and use EXTRACT_SUBREG/INSERT_SUBREG to handle the conversion from GR32 to GR16/8 or vice versa. Unfortunately, this complicates fastisel a bit more now to create the subreg extracts where we used to create GR8 copies. We can probably make a helper function to bring down the repitition. This does result in KMOVD being used for copies when BWI is available because we don't know the original mask register size. This caused a lot of deltas on tests because we have to split the checks for KMOVD vs KMOVW based on BWI. Differential Revision: https://reviews.llvm.org/D30968 llvm-svn: 298928
* [X86][SSE] Refactored shuffle BLEND combining to make future 16i16 support ↵Simon Pilgrim2017-03-281-34/+33
| | | | | | | | easier. NFCI. Call the matchVectorShuffleAsBlend test as early as possible. llvm-svn: 298925
* [SDAG] Avoid deleted SDNodes PromoteIntBinOpNirav Dave2017-03-281-20/+19
| | | | | | | | | | | | | | | Reorder work in PromoteIntBinOp to prevent stale (deleted) nodes from being used. Fixes PR32340 and PR32345. Reviewers: hfinkel, dbabokin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31148 llvm-svn: 298923
* [SDAG] Fix Stale SDNode usage in visitANDNirav Dave2017-03-281-4/+4
| | | | | | | | | | | | | | | Reorder CombineTo Calls to prevent potential use of deleted node. Fixes PR32372. Reviewers: jnspaulsson, RKSimon, uweigand, jonpa Reviewed By: jonpa Subscribers: jonpa, llvm-commits Differential Revision: https://reviews.llvm.org/D31346 llvm-svn: 298920
* Fix signed/unsigned comparison warningSimon Pilgrim2017-03-281-2/+2
| | | | llvm-svn: 298917
* [SDAG] Minor cleanup of variable usage. NFC.Nirav Dave2017-03-281-2/+2
| | | | llvm-svn: 298916
* [X86][SSE] Begin merging vector shuffle to BLEND for lowering and combining.Simon Pilgrim2017-03-281-70/+82
| | | | | | Split off matchVectorShuffleAsBlend from lowerVectorShuffleAsBlend for reuse in combining. llvm-svn: 298914
* Wdocumentation fixSimon Pilgrim2017-03-281-1/+0
| | | | llvm-svn: 298911
* [X86][SSE] Set second operand to undef instead of first operand in unary ↵Simon Pilgrim2017-03-281-1/+2
| | | | | | | | shuffle combines. Copy isn't necessary after the matchVectorShuffleWithUNPCK refactor and undef value will make some future undef/zero handling easier. llvm-svn: 298910
* Strip trailing whitespaceSimon Pilgrim2017-03-281-1/+1
| | | | llvm-svn: 298909
* [AArch64] [Assembler] option to disable negative immediate conversionsSanne Wouda2017-03-284-10/+30
| | | | | | | | | | | | | | | | | Summary: Similar to the ARM target in https://reviews.llvm.org/rL298380, this patch adds identical infrastructure for disabling negative immediate conversions, and converts the existing aliases to the new infrastucture. Reviewers: rengolin, javed.absar, olista01, SjoerdMeijer, samparker Reviewed By: samparker Subscribers: samparker, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D31243 llvm-svn: 298908
* [GlobalISel][X86] support G_FRAME_INDEX instruction selection.Igor Breger2017-03-282-22/+102
| | | | | | | | | | | | | | | | Summary: G_LOAD/G_STORE, add alternative RegisterBank mapping. For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank. Reviewers: zvi, rovka, qcolombet, ab Reviewed By: zvi Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30979 llvm-svn: 298907
* [InstCombine] For select rule, use positive check of constant int for select ↵Anna Thomas2017-03-281-1/+1
| | | | | | operand. NFCI llvm-svn: 298906
* [AMDGPU] Update SI scheduler colorHighLatenciesGroupsValery Pykhtin2017-03-282-22/+100
| | | | | | | | | | Depends on rL298896: MachineScheduler/ScheduleDAG: Add support for GetSubGraph Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30152 llvm-svn: 298902
* Dont emit Mapping symbols for sections that contain only data.Weiming Zhao2017-03-283-18/+92
| | | | | | | | | | | | | | | | | Summary: Dont emit mapping symbols for sections that contain only data. Patched by Shankar Easwaran <shankare@codeaurora.org> Reviewers: rengolin, peter.smith, weimingz, kparzysz, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 298901
* [APInt] Reformat tc functions to put opening curly braces on the end of the ↵Craig Topper2017-03-281-104/+45
| | | | | | previous line. NFC llvm-svn: 298900
* [APInt] Remove an anonymous namespace around static functions. NFCCraig Topper2017-03-281-35/+33
| | | | llvm-svn: 298899
* [APInt] Combine variable declaration and initialization where possible in ↵Craig Topper2017-03-281-76/+36
| | | | | | the tc functions. NFCI llvm-svn: 298898
* [APInt] Use 'unsigned' instead of 'unsigned int' in the interface to the ↵Craig Topper2017-03-281-36/+36
| | | | | | APInt tc functions. This is more consistent with the rest of the codebase. NFC llvm-svn: 298897
* MachineScheduler/ScheduleDAG: Add support for GetSubGraphValery Pykhtin2017-03-281-0/+81
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30626 llvm-svn: 298896
* CodeGen : Check LLVM_ENABLE_DUMP definition for ↵Junmo Park2017-03-281-1/+2
| | | | | | | | | | | | | dumpMachineInstrRangeWithSlotIndex. Summary: Add missing check routine for dumpMachineInstrRangeWithSlotIndex including LLVM_DUMP_METHOD. Reviewers: bkramer Differential revision: https://reviews.llvm.org/D30367 llvm-svn: 298895
* [APInt] Move the single word cases of the bitwise operators inline.Craig Topper2017-03-281-18/+3
| | | | llvm-svn: 298894
* Revert "[asan] Delay creation of asan ctor."Alex Shlyapnikov2017-03-272-26/+21
| | | | | | | | Speculative revert. Some libfuzzer tests are affected. This reverts commit r298731. llvm-svn: 298890
* Revert "[asan] Put ctor/dtor in comdat."Alex Shlyapnikov2017-03-271-41/+9
| | | | | | | | Speculative revert, some libfuzzer tests are affected. This reverts commit r298756. llvm-svn: 298889
* Remove an oddly unnecessary temporary.Eric Christopher2017-03-271-2/+1
| | | | llvm-svn: 298888
* [libfuzzer] Remove XFAIL for OutOfMemory test.Juergen Ributzka2017-03-271-1/+0
| | | | | | | | This test is now passing on Darwin. See rdar://problem/31282257. llvm-svn: 298886
* Improve machine schedulers for in-order processorsJaved Absar2017-03-273-1/+55
| | | | | | | | | | | This patch enables schedulers to specify instructions that cannot be issued with any other instructions. It also fixes BeginGroup/EndGroup. Reviewed by: Andrew Trick Differential Revision: https://reviews.llvm.org/D30744 llvm-svn: 298885
* Add the error handling for Mach-O dyld compact lazy bind, weak bind andKevin Enderby2017-03-271-46/+274
| | | | | | | | | | | | | | | | | | | | | rebase entry errors and test cases for each of the error checks. Also verified with Nick Kledzik that a BIND_OPCODE_SET_ADDEND_SLEB opcode is legal in a lazy bind table, so code that had that as an error check was removed. With MachORebaseEntry and MachOBindEntry classes now returning an llvm::Error in all cases for malformed input the variables Malformed and logic to set use them is no longer needed and has been removed from those classes. Also in a few places, removed the redundant Done assignment to true when also calling moveToEnd() as it does that assignment. This only leaves the dyld compact export entries left to have error handling yet to be added for the dyld compact info. llvm-svn: 298883
* [LV] Transform truncations of non-primary induction variablesMatthew Simpson2017-03-271-11/+10
| | | | | | | | | | | | The vectorizer tries to replace truncations of induction variables with new induction variables having the smaller type. After r295063, this optimization was applied to all integer induction variables, including non-primary ones. When optimizing the truncation of a non-primary induction variable, we still need to transform the new induction so that it has the correct start value. This should fix PR32419. Reference: https://bugs.llvm.org/show_bug.cgi?id=32419 llvm-svn: 298882
OpenPOWER on IntegriCloud