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* [libFuzzer] fix merging with trace-pc-guardKostya Serebryany2016-09-238-27/+25
| | | | llvm-svn: 282224
* AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_sizeTom Stellard2016-09-233-1/+25
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D24835 llvm-svn: 282223
* [libFuzzer] simplify the TracePC logicKostya Serebryany2016-09-233-29/+20
| | | | llvm-svn: 282222
* [RegisterBankInfo] Mark the dump methods with LLVM_DUMP_METHOD.Quentin Colombet2016-09-231-4/+4
| | | | | | NFC llvm-svn: 282221
* [AArch64][RegisterBankInfo] Sanity check TableGen'ed like inputs.Quentin Colombet2016-09-231-0/+47
| | | | | | | Make sure the entries written to mimic the behavior of TableGen are sane. llvm-svn: 282220
* [libFuzzer] move value profiling logic into TracePCKostya Serebryany2016-09-236-32/+21
| | | | llvm-svn: 282219
* Triple: Add opencl environment typeTom Stellard2016-09-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For AMDGPU, we have been using the operating system component of the triple for specifying the low-level runtime that is being used. The rationale for this is that the host operating system (e.g. Linux) is irrelevant for GPU code, since its execution enviroment will be mostly controled by the low-level runtime being used to execute the code. In most cases, higher level languages have their own runtime which is implemented on top of the low-level runtime. The kernel ABIs of each language mostly depend on the low-level runtime, but there may be some slight differences between languages. OpenCL for example, may append additional arguments to the kernel in order to pass values like global offsets or buffers for printf. OpenMP, HCC, or other languages may want to add their own values which differ from OpenCL. The reason for adding a new opencl environment type is to make it possible for the backend to distinguish between the ABIs of the higher-level languages and handle them correctly. It seems cleaner to use the enviroment component for this rather than creating a new OS type for every combination of low-level runtime / high-level language. Reviewers: Anastasia, chandlerc Subscribers: whchung, pekka.jaaskelainen, wdng, yaxunl, llvm-commits Differential Revision: https://reviews.llvm.org/D24735 llvm-svn: 282218
* [MC] Support skip and count for .incbin directivePetr Hosek2016-09-231-7/+45
| | | | | | | | These optional arguments are supported by GNU assembler. Differential Revision: https://reviews.llvm.org/D24714 llvm-svn: 282217
* [libFuzzer] change ValueBitMap to remember the number of bits in itKostya Serebryany2016-09-237-30/+29
| | | | llvm-svn: 282216
* [AArch64][RegisterBankInfo] Switch to TableGen'ed like PartialMapping.Quentin Colombet2016-09-232-20/+70
| | | | | | | | | Statically instanciate the most common PartialMappings. This should be closer to what the code would look like when TableGen support is added for GlobalISel. As a side effect, this should improve compile time. llvm-svn: 282215
* [RegisterBankInfo] Check that the mapping covers the interesting bits.Quentin Colombet2016-09-231-2/+3
| | | | | | | | | | | | | | | In the verify method of the ValueMapping class we used to check that the mapping exactly matches the bits of the input value. This is problematic for statically allocated mappings because we would need a different mapping for each different size of the value that maps on one instruction. For instance, with such scheme, we would need a different mapping for a value of size 1, 5, 23 whereas they all end up on a 32-bit wide instruction. Therefore, change the verifier to check that the meaningful bits are covered by the mapping instead of matching them. llvm-svn: 282214
* [RegisterBankInfo] Use array instead of SmallVector for BreakDown.Quentin Colombet2016-09-233-47/+54
| | | | | | | | | | | | | This is another step toward TableGen'ed like structures. The BreakDown of the mapping of the value will be statically computed by TableGen, thus we only have to point to the right entry in the table instead of dynamically allocate the mapping for each instruction. We still support the dynamic allocation through a factory of PartialMapping to ease the bring-up of the targets while the TableGen backend is not available. llvm-svn: 282213
* [libFuzzer] simplify the crash minimizer; split MaxLen into two: MaxInputLen ↵Kostya Serebryany2016-09-223-29/+36
| | | | | | and MaxMutationLen, allow MaxMutationLen to be less than MaxInputLen llvm-svn: 282211
* [InstCombine] fold X urem C -> X < C ? X : X - C when C is big (PR28672)Sanjay Patel2016-09-221-0/+8
| | | | | | | | | | | | We already have the udiv variant of this transform, so I think this is ok for InstCombine too even though there is an increase in IR instructions. As the tests and TODO comments show, the transform can lead to follow-on combines. This should fix: https://llvm.org/bugs/show_bug.cgi?id=28672 Differential Revision: https://reviews.llvm.org/D24527 llvm-svn: 282209
* [AsmParser] Remove unused partial template specialization.Davide Italiano2016-09-221-10/+0
| | | | llvm-svn: 282206
* MachineScheduler: Slightly simplify release nodeMatthias Braun2016-09-221-14/+0
| | | | llvm-svn: 282201
* MachineScheduler: Remove ineffective heuristic; NFCMatthias Braun2016-09-221-11/+0
| | | | | | | | | Currently all nodes get added to the NextSU list when they are released, so any candidate must be in that list, making the heuristic ineffective. Remove it for now, we can add it back later in a working fashion if necessary. llvm-svn: 282200
* Revert r282168 "GVN-hoist: fix store past load dependence analysis (PR30216)"Hans Wennborg2016-09-221-35/+28
| | | | | | | | and also the dependent r282175 "GVN-hoist: do not dereference null pointers" It's causing compiler crashes building Harfbuzz (PR30499). llvm-svn: 282199
* [RDF] Add initial support for lane masks in the DFGKrzysztof Parzyszek2016-09-225-62/+163
| | | | | | | Use lane masks for calculating covering and aliasing of register references. llvm-svn: 282194
* [Hexagon] Remove USR_OVF from CtrRegs register classKrzysztof Parzyszek2016-09-221-1/+4
| | | | | | | | | USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both a register and its proper subregister in the same register class has bad consequences for lane mask calculation: based solely on the lane mask info, USR_OVF would not appear to be a subregister of USR. llvm-svn: 282192
* [RDF] Print the function name for calls in dumpsKrzysztof Parzyszek2016-09-221-3/+18
| | | | llvm-svn: 282191
* [RDF] Use uint32_t for register numbers instead of unsignedKrzysztof Parzyszek2016-09-222-8/+8
| | | | llvm-svn: 282190
* i386 does not support optimized swifterror handlingArnold Schwaighofer2016-09-222-3/+5
| | | | | | rdar://28432565 llvm-svn: 282186
* Win64: Don't emit unwind info for "leaf" functions (PR30337)Hans Wennborg2016-09-223-4/+22
| | | | | | | | | | | | According to MSDN (see the PR), functions which don't touch any callee-saved registers (including %rsp) don't need any unwind info. This patch makes LLVM not emit unwind info for such functions, to save binary size. Differential Revision: https://reviews.llvm.org/D24748 llvm-svn: 282185
* [PowerPC] Sign extend sub-word values for atomic comparisonsNemanja Ivanovic2016-09-221-2/+11
| | | | | | | | Atomic comparison instructions use the sub-word load instruction on Power8 and up but the value is not sign extended prior to the signed word compare instruction. This patch adds that sign extension. llvm-svn: 282182
* [DAG] Fix incorrect alignment of ext load.Nirav Dave2016-09-221-1/+1
| | | | | | | | | | | | Correctly use alignment size from loaded size not output value size. Reviewers: jyknight, tstellarAMD, arsenm Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23356 llvm-svn: 282177
* GVN-hoist: do not dereference null pointersSebastian Pop2016-09-221-0/+3
| | | | | | | there may be basic blocks without memory accesses, in which case the list of accesses is a null pointer. llvm-svn: 282175
* [PPC] Set SP after loading data from stack frame, if no red zone is presentKrzysztof Parzyszek2016-09-221-50/+195
| | | | | | | | | | | Follow-up to r280705: Make sure that the SP is only restored after all data is loaded from the stack frame, if there is no red zone. This completes the fix for https://llvm.org/bugs/show_bug.cgi?id=26519. Differential Revision: https://reviews.llvm.org/D24466 llvm-svn: 282174
* Speculative fix for build failures due to consumeInteger.Zachary Turner2016-09-221-0/+3
| | | | | | | | | | | | | | | | A recent patch added support for consumeInteger() and made getAsInteger delegate to this function. A few buildbots are failing as a result with an assertion failure. On a hunch, I tested what happens if I call getAsInteger() on an empty string, and sure enough it crashes the same way that the buildbots are crashing. I confirmed that getAsInteger() on an empty string did not crash before my patch, so I suspect this to be the cause. I also added a unit test for the empty string. llvm-svn: 282170
* GVN-hoist: fix store past load dependence analysis (PR30216)Sebastian Pop2016-09-221-29/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To hoist stores past loads, we used to search for potential conflicting loads on the hoisting path by following a MemorySSA def-def link from the store to be hoisted to the previous defining memory access, and from there we followed the def-use chains to all the uses that occur on the hoisting path. The problem is that the def-def link may point to a store that does not alias with the store to be hoisted, and so the loads that are walked may not alias with the store to be hoisted, and even as in the testcase of PR30216, the loads that may alias with the store to be hoisted are not visited. The current patch visits all loads on the path from the store to be hoisted to the hoisting position and uses the alias analysis to ask whether the store may alias the load. I was not able to use the MemorySSA functionality to ask for whether load and store are clobbered: I'm not sure which function to call, so I used a call to AA->isNoAlias(). Store past store is still working as before using a MemorySSA query: I added an extra test to pr30216.ll to make sure store past store does not regress. Differential Revision: https://reviews.llvm.org/D24517 llvm-svn: 282168
* GVN-hoist: fix typoSebastian Pop2016-09-221-1/+1
| | | | llvm-svn: 282165
* [Support] Add StringRef::consumeInteger.Zachary Turner2016-09-221-25/+55
| | | | | | | | | | | | | | | | | | | | | StringRef::getInteger() exists and treats the entire string as an integer of the specified radix, failing if any invalid characters are encountered or the number overflows. Sometimes you might have something like "123456foo" and you want to get the number 123456 and leave the string "foo" remaining. This is similar to what would be possible by using the standard runtime library functions strtoul et al and specifying an end pointer. This patch adds consumeInteger(), which does exactly that. It consumes as much as possible until an invalid character is found, and modifies the StringRef in place so that upon return only the portion of the StringRef after the number remains. Differential Revision: https://reviews.llvm.org/D24778 llvm-svn: 282164
* [compiler-rt] fix typo in option description [NFC]Etienne Bergeron2016-09-221-1/+1
| | | | llvm-svn: 282163
* GVN-hoist: only hoist relevant scalar instructionsSebastian Pop2016-09-221-0/+4
| | | | | | | | | | | | | | | | | | | Without this patch, GVN-hoist would think that a branch instruction is a scalar instruction and would try to value number it. The patch filters out all such kind of irrelevant instructions. A bit frustrating is that there is no easy way to discard all those very infrequent instructions, a bit like isa<TerminatorInst> that stands for a large family of instructions. I'm thinking that checking for those very infrequent other instructions would cost us more in compilation time than just letting those instructions getting numbered, so I'm still thinking that a simpler check: if (isa<TerminatorInst>(I)) return false; is better than listing all the other less frequent instructions. Differential Revision: https://reviews.llvm.org/D23929 llvm-svn: 282160
* Reapplying r281895 (and follow-up r281964) after fixing pr30468.Keith Walker2016-09-222-5/+53
| | | | | | | | | | | | | | | | The additional fix is: When adding debug information to a lowered phi node in mem2reg check that we have a valid insertion point after the phi for adding the debug information. This change addresses the issue in pr30468 where a lowered phi was added before a catchswitch and no debug information should be added after the phi in this case. Differential Revision: https://reviews.llvm.org/D24797 llvm-svn: 282155
* GlobalISel: handle stack-based parameters on AArch64.Tim Northover2016-09-223-73/+208
| | | | llvm-svn: 282153
* [RS4GC] Remat in presence of phi and use live valueAnna Thomas2016-09-221-8/+21
| | | | | | | | | | Summary: Reviewers: Subscribers: llvm-svn: 282150
* [AMDGPU][mc] Add support for absolute expressions in DPP modifiers.Artem Tamazov2016-09-221-35/+22
| | | | | | | | | Also added range checking for DPP attributes. Assembler tests added as well. Differential Revision: https://reviews.llvm.org/D24755 llvm-svn: 282145
* [PowerPC] Remove LE patterns matching generic stores/loads to VSX permuting opsNemanja Ivanovic2016-09-221-5/+10
| | | | | | | | | | | | | This patch corresponds to: https://reviews.llvm.org/D21409 The LXVD2X, LXVW4X, STXVD2X and STXVW4X instructions permute the two doublewords in the vector register when in little-endian mode. Custom code ensures that the necessary swaps are inserted for these. This patch simply removes the possibilty that a load/store node will match one of these instructions in the SDAG as that would not insert the necessary swaps. llvm-svn: 282144
* [Power9] Add exploitation of non-permuting memory opsNemanja Ivanovic2016-09-225-21/+68
| | | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. llvm-svn: 282143
* [EfficiencySanitizer] Using '$' instead of '#' for struct counter nameSagar Thakur2016-09-221-6/+6
| | | | | | | | | For MIPS '#' is the start of comment line. Therefore we get assembler errors if # is used in the structure names. Differential: D24334 Reviewed by: zhaoqin llvm-svn: 282141
* Fix revision 281960Dorit Nuzman2016-09-221-2/+4
| | | | llvm-svn: 282139
* [AVX-512] Add support for commuting VPTERNLOG instructions.Craig Topper2016-09-224-39/+171
| | | | | | | | | | VPTERNLOG is a ternary instruction with an immediate specifying the logical operation to perform. For each bit position in the 3 source vectors the bit from each source is concatenated together and the resulting 3-bit value is used to select a bit in the immediate. This bit value is written to the result vector. We can commute this by swapping operands and modifying the immediate. To modify the immediate we need to swap two pairs of bits. The pairs correspond to the locations in the immediate where the commuted operands bits have opposite values and the uncommuted operand has the same value. Bits 0 and 7 will never be swapped since the relevant bits from all sources are the same value. This refactors and reuses parts of the FMA3 commuting code which is also a three operand instruction. llvm-svn: 282132
* [RegisterBankInfo] Move to statically allocated RegisterBank.Quentin Colombet2016-09-224-4/+59
| | | | | | | | | | | | This commit is basically the first step toward what will RegisterBankInfo look when it gets TableGen'ed. It introduces a XXXGenRegisterBankInfo.def file that is what TableGen will issue at some point. Moreover, the RegBanks field in RegisterBankInfo changed to reflect the static (compile time) aspect of the information. llvm-svn: 282131
* [RegisterBankInfo] Take advantage of the extra argument of SmallVector::resize.Quentin Colombet2016-09-221-3/+1
| | | | | | | | When initializing an instance of OperandsMapper, instead of using SmallVector::resize followed by std::fill, use the function that directly does that in SmallVector. llvm-svn: 282130
* [libFuzzer] add 'features' to the corpus elements, allow mutations with Size ↵Kostya Serebryany2016-09-228-44/+66
| | | | | | > MaxSize, fix sha1 in corpus stats; various refactorings llvm-svn: 282129
* [libFuzzer] one more test Kostya Serebryany2016-09-223-0/+30
| | | | llvm-svn: 282127
* [libFuzzer] add stats to the corpus; more refactoringKostya Serebryany2016-09-2110-49/+53
| | | | llvm-svn: 282121
* [libFuzzer] more refactoring; don't compute sha1sum every time we mutate a ↵Kostya Serebryany2016-09-214-57/+53
| | | | | | unit from the corpus, use the stored one. llvm-svn: 282115
* [libFuzzer] more refactoringKostya Serebryany2016-09-2110-8/+13
| | | | llvm-svn: 282113
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