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* [X86][AVX512] Added support for lowering 512-bit vector shuffles to bit/byte ↵Simon Pilgrim2016-06-091-19/+41
| | | | | | | | shifts 512-bit VPSLLDQ/VPSRLDQ can only be used for avx512bw targets so lowerVectorShuffleAsShift had to be adjusted to include the subtarget llvm-svn: 272300
* [NVPTX] Add intrinsics for shfl instructions.Justin Lebar2016-06-091-1/+42
| | | | | | | | | | | | | | | Summary: Currently clang emits these instructions via inline (volatile) asm in the CUDA headers. Switching to intrinsics will let the optimizer reason across calls to these intrinsics. Reviewers: tra Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D21160 llvm-svn: 272298
* [PM] Port LCSSA to the new PM.Easwaran Raman2016-06-098-23/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D21090 llvm-svn: 272294
* AMDGPU/SI: Fix 32-bit fdiv loweringWei Ding2016-06-091-16/+53
| | | | | | | | | We were using the fast fdiv lowering for all division, implementation of IEEE754 fdiv is added. http://reviews.llvm.org/D20557 llvm-svn: 272292
* [LV] Use vector phis for some secondary induction variablesMichael Kuperstein2016-06-091-4/+6
| | | | | | | | | | | | | | Previously, we materialized secondary vector IVs from the primary scalar IV, by offseting the primary to match the correct start value, and then broadcasting it - inside the loop body. Instead, we can use a real vector IV, like we do for the primary. This enables using vector IVs for secondary integer IVs whose type matches the type of the primary. Differential Revision: http://reviews.llvm.org/D20932 llvm-svn: 272283
* SelectionDAG: Implement expansion of {S,U}MIN/MAX in integer legalizationJan Vesely2016-06-092-0/+55
| | | | | | | | | Fixes {u,}long_{min,max,clamp} opencl piglit regressions on EG. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D17898 llvm-svn: 272272
* Reapply "[MBP] Reduce code size by running tail merging in MBP.""Haicheng Wu2016-06-094-34/+121
| | | | | | | | | | | | | | | | This reapplies commit r271930, r271915, r271923. They hit a bug in Thumb which is fixed in r272258 now. The original message: The code layout that TailMerging (inside BranchFolding) works on is not the final layout optimized based on the branch probability. Generally, after BlockPlacement, many new merging opportunities emerge. This patch calls Tail Merging after MBP and calls MBP again if Tail Merging merges anything. llvm-svn: 272267
* [SystemZ] Enable long displacement constraints for inline ASM operandsUlrich Weigand2016-06-092-9/+21
| | | | | | | | | | | | | | | | | | This enables use of the 'S' constraint for inline ASM operands on SystemZ, which allows for a memory reference with a signed 20-bit immediate displacement. This patch includes corresponding documentation and test case updates. I've changed the 'T' constraint to match the new behavior for 'S', as 'T' also uses a long displacement (though index constraints are still not implemented). I also changed 'm' to match the behavior for 'S' as this will allow for a wider range of displacements for 'm', though correct me if that's not the right decision. Author: colpell Differential Revision: http://reviews.llvm.org/D21097 llvm-svn: 272266
* [CodeGen] Change getSDagStackGuard to get an internal sym.Davide Italiano2016-06-091-1/+1
| | | | | | | Fixes a crash in the backend during an LTO build of rtld(1) in FreeBSD. llvm-svn: 272262
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-099-13/+241
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
* [Thumb] A branch is not part of an IT blockJames Molloy2016-06-091-1/+1
| | | | | | | | ReplaceTailWithBranchTo assumed that if an instruction is predicated, it must be part of an IT block. This is not correct for conditional branches. No testcase as this was triggered by the reverted patch r272017 - test coverage will occur when that patch is re-reverted and there is no known way to trigger this in the meantime. llvm-svn: 272258
* [AVX512] Remove masked_move/blendm intrinsic from back-end. Igor Breger2016-06-092-45/+1
| | | | | | | | This is complement patch to D21060. Differential Revision: http://reviews.llvm.org/D21174 llvm-svn: 272257
* [mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, ↵Zlatko Buljan2016-06-094-80/+137
| | | | | | | | SELNEZ.* and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D20862 llvm-svn: 272256
* [AMDGPU] Disassembler: Support for sdwa instructionsSam Kolton2016-06-091-1/+5
| | | | | | | | | | Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21129 llvm-svn: 272255
* [AVX512] Fix shuffle decode printing for several instructions with write ↵Craig Topper2016-06-091-3/+3
| | | | | | masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. llvm-svn: 272252
* [Thumb] Select a BIC instead of AND if the immediate can be encoded more ↵James Molloy2016-06-091-1/+40
| | | | | | | | | | | | | | | | | | | | | | optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 272251
* [X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR ↵Craig Topper2016-06-094-39/+35
| | | | | | instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. llvm-svn: 272249
* [X86] Fix bad comment in assert. NFCCraig Topper2016-06-091-1/+1
| | | | llvm-svn: 272248
* Revert r272194 No need for it if loop Analysis Manager is usedXinliang David Li2016-06-096-16/+17
| | | | llvm-svn: 272243
* AArch64: support the `.arch` directive in the IASSaleem Abdulrasool2016-06-091-0/+28
| | | | | | | | | | Add support to the AArch64 IAS for the `.arch` directive. This allows the assembly input to use architectural functionality in part of a file. This is used in existing code like BoringSSL. Resolves PR26016! llvm-svn: 272241
* [libFuzzer] add one more OOM test, which we currently don't handle very wellKostya Serebryany2016-06-092-0/+30
| | | | llvm-svn: 272240
* [ThinLTO/gold] Enable summary-based internalizationTeresa Johnson2016-06-091-2/+13
| | | | | | | | | | | | Summary: Enable existing summary-based importing support in the gold-plugin. Reviewers: mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: http://reviews.llvm.org/D21080 llvm-svn: 272239
* Minor clean up in loopHasNoAbnormalExits; NFCSanjoy Das2016-06-091-8/+7
| | | | llvm-svn: 272238
* Be wary of abnormal exits from loop when exploiting UBSanjoy Das2016-06-091-1/+2
| | | | | | | | | | | | | | We can safely rely on a NoWrap add recurrence causing UB down the road only if we know the loop does not have a exit expressed in a way that is opaque to ScalarEvolution (e.g. by a function call that conditionally calls exit(0)). I believe with this change PR28012 is fixed. Note: I had to change some llvm-lit tests in LoopReroll, since it looks like they were depending on this incorrect behavior. llvm-svn: 272237
* Factor out a loopHasNoAbnormalExits; NFCSanjoy Das2016-06-091-9/+8
| | | | llvm-svn: 272236
* Search for llvm-symbolizer binary in the same directory as argv[0], beforeRichard Smith2016-06-093-15/+37
| | | | | | | looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
* [codeview] Skip DIGlobalVariables with no variableReid Kleckner2016-06-091-2/+3
| | | | | | They have probably been discarded during optimization. llvm-svn: 272231
* [pdbdump] Verify part of TPI hash streams.Rui Ueyama2016-06-091-0/+28
| | | | | | | | | | | | | | | | | TPI hash table contains a parallel array for the type records. For each type record R, a hash value is calculated by `H(R) % NumBuckets` where H is a hash function, and the result is stored to a bucket element. H is TPI1::hashPrec function in microsoft-pdb repository. Our hash function does not support all type record types yet. Currently it supports only records for line number. I'll extend it in a follow up patch. The aim of verify the hash table is not only detect corrupted files. It ensures that our understanding of how the hash values are calculated is correct. llvm-svn: 272229
* [cpu-detection] Add missing break statements in outer switchesAlina Sbirlea2016-06-091-6/+9
| | | | | | | | | | | | Summary: Break on all switch cases for outer and inner switches. No functionality changed. Reviewers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D21158 llvm-svn: 272228
* [MIR] Check that generic virtual registers get a size.Quentin Colombet2016-06-083-4/+11
| | | | | | | | Without that check it was possible to write test cases where the size was not specified and we ended up with weird asserts down the road, because the default value (1) would not make sense. llvm-svn: 272226
* Function names should start with lowercase letters.Rui Ueyama2016-06-082-3/+3
| | | | llvm-svn: 272225
* [LoopSimplify] Preserve LCSSA when merging exit blocks.Michael Zolotukhin2016-06-081-2/+21
| | | | | | | | | | | | | | Summary: This fixes PR26682. Also add LCSSA as a preserved pass to LoopSimplify, that looks correct to me and allows to write a test for the issue. Reviewers: chandlerc, bogner, sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21112 llvm-svn: 272224
* [PDB] Move PDB functions to a separate file.Rui Ueyama2016-06-083-59/+79
| | | | | | | | We are going to use the hash functions from TPI streams. Differential Revision: http://reviews.llvm.org/D21142 llvm-svn: 272223
* [LoopUnroll] Check that DT is available before trying to verify it.Michael Zolotukhin2016-06-081-1/+1
| | | | llvm-svn: 272221
* [RegBankSelect] Print out the actual mapping of the operands.Quentin Colombet2016-06-081-0/+1
| | | | | | This improves the debuggability of the pass. llvm-svn: 272210
* [RegBankSelect] Remove a debug print of a potentially dead instruction.Quentin Colombet2016-06-081-2/+2
| | | | | | | | For complex rewrittings, which do not occur currently, the related machine instruction may have been deleted in the process. Therefore, do not try to print it after the mapping is applied. llvm-svn: 272209
* [RegisterBankInfo] Avoid code duplication in OperandsMapper for the ↵Quentin Colombet2016-06-081-6/+17
| | | | | | | | | | | | | computation of the end of range. Refactor the code so that we do not compute in two different places the end iterator for the range of new virtual registers for a given operand. Although this refactoring was intended as NFC, this is not the case because it actually fixes a bug where we were returning a range off by 1 (too long). Right now, this could not result in an actual bug because we were accessing this range via the BreakDown size of the related operand. llvm-svn: 272208
* [RegisterBankInfo] Add dump/print methods for OperandsMapper.Quentin Colombet2016-06-081-2/+55
| | | | | | Improve debuggability of the OperandsMapper helper class. llvm-svn: 272207
* [SLPVectorizer] Handle GEP with differing constant index typesMichael Zolotukhin2016-06-081-1/+1
| | | | | | | | | | | | | | | | | | | Summary: This fixes PR27617. Bug description: The SLPVectorizer asserts on encountering GEPs with different index types, such as i8 and i64. The patch includes a simple relaxation of the assert to allow constants being of different types, along with a regression test that will provoke the unrelaxed assert. Reviewers: nadav, mzolotukhin Subscribers: JesperAntonsson, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D20685 Patch by Jesper Antonsson! llvm-svn: 272206
* [PM] Add missing caching of GlobalsAA to EarlyCSE.Davide Italiano2016-06-081-0/+1
| | | | llvm-svn: 272204
* Revive http://reviews.llvm.org/D12778 to handle forward-hot-prob and ↵Dehao Chen2016-06-081-3/+10
| | | | | | | | | | | | | | | | | | | | | | | backward-hot-prob consistently. Summary: Consider the following diamond CFG: A / \ B C \/ D Suppose A->B and A->C have probabilities 81% and 19%. In block-placement, A->B is called a hot edge and the final placement should be ABDC. However, the current implementation outputs ABCD. This is because when choosing the next block of B, it checks if Freq(C->D) > Freq(B->D) * 20%, which is true (if Freq(A) = 100, then Freq(B->D) = 81, Freq(C->D) = 19, and 19 > 81*20%=16.2). Actually, we should use 25% instead of 20% as the probability here, so that we have 19 < 81*25%=20.25, and the desired ABDC layout will be generated. Reviewers: djasper, davidxl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20989 llvm-svn: 272203
* [InstCombine] move fold of select of add/sub to helper function; NFCISanjay Patel2016-06-081-61/+75
| | | | llvm-svn: 272199
* [DebugInfo] Add calling convention support for DWARF and CodeViewReid Kleckner2016-06-0812-36/+91
| | | | | | | | | | | | | | | | | | | | | Summary: Now DISubroutineType has a 'cc' field which should be a DW_CC_ enum. If it is present and non-zero, the backend will emit it as a DW_AT_calling_convention attribute. On the CodeView side, we translate it to the appropriate enum for the LF_PROCEDURE record. I added a new LLVM vendor specific enum to the list of DWARF calling conventions. DWARF does not appear to attempt to standardize these, so I assume it's OK to do this until we coordinate with GCC on how to emit vectorcall convention functions. Reviewers: dexonsmith, majnemer, aaboud, amccarth Subscribers: mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D21114 llvm-svn: 272197
* [InstCombine] fix outdated comment, simplify logic; NFCISanjay Patel2016-06-081-16/+13
| | | | llvm-svn: 272196
* The patch set unroll disable pragma when unrollEvgeny Stupachenko2016-06-081-11/+11
| | | | | | | | | | | | | | | | | with user specified count has been applied. Summary: Previously SetLoopAlreadyUnrolled() set the disable pragma only if there was some loop metadata. Now it set the pragma in all cases. This helps to prevent multiple unroll when -unroll-count=N is given. Reviewers: mzolotukhin Differential Revision: http://reviews.llvm.org/D20765 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 272195
* [PM] Refector LoopAccessInfo analysis code Xinliang David Li2016-06-086-17/+16
| | | | | | | | This is the preparation patch to port the analysis to new PM Differential Revision: http://reviews.llvm.org/D20560 llvm-svn: 272194
* [InstCombine] reduce indent; NFCSanjay Patel2016-06-081-63/+64
| | | | llvm-svn: 272193
* [MemCpyOpt] Do not exchange llvm.lifetime.start and llvm.memcpyTim Shen2016-06-081-0/+5
| | | | | | | | | | Reviewers: iteratee Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21087 llvm-svn: 272192
* [InstCombine] use copyIRFlags() ; NFCISanjay Patel2016-06-081-12/+2
| | | | llvm-svn: 272191
* Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer2016-06-0827-56/+54
| | | | | | | Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
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