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* Remove the debug machine code emitter. The "FilePrinterEmitter" is moreChris Lattner2006-05-021-52/+0
| | | | | | useful for debugging. llvm-svn: 28051
* Extend printBasicBlockLabel a bit so that it can be used to print allNate Begeman2006-05-029-37/+51
| | | | | | | basic block labels, consolidating the code to do so in one place for each target. llvm-svn: 28050
* Update the PPC compilation callback code to not need weird abi-violatingNate Begeman2006-05-021-49/+46
| | | | | | | prologs and epilogs, keep all the asm in one place, and remove use of compiler builtin functions. llvm-svn: 28049
* Add pass ID's for various passes, so they can be AddRequiredID. Patch byChris Lattner2006-05-024-0/+8
| | | | | | Domagoj Babic! llvm-svn: 28048
* De-virtualize SwitchSection.Jeff Cohen2006-05-023-37/+44
| | | | llvm-svn: 28047
* De-virtualize EmitZeroes.Jeff Cohen2006-05-023-11/+9
| | | | llvm-svn: 28046
* Finish support for Microsoft ML/MASM. May still be a few rough edges.Jeff Cohen2006-05-022-3/+50
| | | | llvm-svn: 28045
* Make Intel syntax mode friendlier to Microsoft ML assembler (still needs ↵Jeff Cohen2006-05-023-27/+113
| | | | | | more work). llvm-svn: 28044
* Fix a latent bug that my spiller patch last week exposed: we were leavingChris Lattner2006-05-012-4/+7
| | | | | | | | | instructions in the virtregfolded map that were deleted. Because they were deleted, newly allocated instructions could end up at the same address, magically finding themselves in the map. The solution is to remove entries from the map when we delete the instructions. llvm-svn: 28041
* When promoting a load to a reg-reg copy, where the load was a previousChris Lattner2006-05-011-0/+1
| | | | | | | instruction folded with spill code, make sure the remove the load from the virt reg folded map. llvm-svn: 28040
* Remove previous patch, which wasn't quite right.Chris Lattner2006-05-013-24/+23
| | | | llvm-svn: 28039
* Put PHI/INLINEASM into the correct namespace.Chris Lattner2006-05-011-0/+2
| | | | llvm-svn: 28037
* Dis-favor stores moreEvan Cheng2006-05-011-2/+2
| | | | llvm-svn: 28035
* Bottom up register-pressure reduction scheduler now pushes store operationsEvan Cheng2006-05-011-17/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | up the schedule. This helps code that looks like this: loads ... computations (first set) ... stores (first set) ... loads computations (seccond set) ... stores (seccond set) ... Without this change, the stores and computations are more likely to interleave: loads ... loads ... computations (first set) ... computations (second set) ... computations (first set) ... stores (first set) ... computations (second set) ... stores (stores set) ... This can increase the number of spills if we are unlucky. llvm-svn: 28033
* Didn't mean ScheduleDAGList.cpp to make the last checkin.Evan Cheng2006-05-011-33/+17
| | | | llvm-svn: 28030
* Remove temp. option -spiller-check-liveout, it didn't cause any failure nor ↵Evan Cheng2006-05-012-22/+34
| | | | | | performance regressions. llvm-svn: 28029
* Remove %'s from register names when in intel mode.Chris Lattner2006-05-012-6/+4
| | | | llvm-svn: 28027
* Format #APP lines a bit nicerChris Lattner2006-05-011-2/+2
| | | | llvm-svn: 28026
* Local spiller kills a store if the folded restore is turned into a copy.Evan Cheng2006-04-303-10/+21
| | | | | | | | But this is incorrect if the spilled value live range extends beyond the current BB. It is currently controlled by a temporary option -spiller-check-liveout. llvm-svn: 28024
* Mingw32 patches supplied by Anton Korobeynikov.Jeff Cohen2006-04-292-3/+3
| | | | llvm-svn: 28023
* Remove a bogus transformation. This fixes ↵Chris Lattner2006-04-281-7/+0
| | | | | | | | SingleSource/UnitTests/2006-01-23-InitializedBitField.c with some changes I have to the new CFE. llvm-svn: 28022
* I can't spell: Register, not Regsiter.Evan Cheng2006-04-284-6/+6
| | | | llvm-svn: 28021
* Implemented x86 inline asm b, h, w, k modifiers.Evan Cheng2006-04-284-1/+249
| | | | llvm-svn: 28020
* Fix InstCombine/2006-04-28-ShiftShiftLongLong.llChris Lattner2006-04-281-1/+1
| | | | llvm-svn: 28019
* Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.llChris Lattner2006-04-281-0/+4
| | | | llvm-svn: 28017
* Initial caller side support (for CCC only, not FastCC) of 128-bit vectorEvan Cheng2006-04-281-7/+73
| | | | | | passing by value. llvm-svn: 28015
* Bare-bone X86 inline asm printer support.Evan Cheng2006-04-284-2/+66
| | | | llvm-svn: 28014
* Remove the temporary option: -no-isel-fold-inflightEvan Cheng2006-04-281-11/+0
| | | | llvm-svn: 28012
* Implement four-wide shuffle with 2 shufps if no more than two elements comeEvan Cheng2006-04-281-2/+47
| | | | | | | | | | | from each vector. e.g. shuffle(G1, G2, 7, 1, 5, 2) ==> movaps _G2, %xmm0 shufps $151, _G1, %xmm0 shufps $216, %xmm0, %xmm0 llvm-svn: 28011
* Fix PR743: emit -help output of a tool to cout, not cerr.Chris Lattner2006-04-281-20/+20
| | | | llvm-svn: 28010
* TargetLowering::LowerArguments should return a VBIT_CONVERT ofEvan Cheng2006-04-282-17/+15
| | | | | | FORMAL_ARGUMENTS SDOperand in the return result vector. llvm-svn: 28009
* Mapping of physregs can make it so that the designated and input physregs areChris Lattner2006-04-281-0/+13
| | | | | | the same. In this case, don't emit a noop copy. llvm-svn: 28008
* Fix Transforms/Reassociate/2006-04-27-ReassociateVector.llChris Lattner2006-04-281-2/+3
| | | | llvm-svn: 28007
* Use movaps instead of movapd for spill / restore.Evan Cheng2006-04-281-2/+2
| | | | llvm-svn: 28005
* Added a temporary option -no-isel-fold-inflight to control whether a "inflight"Evan Cheng2006-04-281-1/+12
| | | | | | node can be folded. llvm-svn: 28003
* When we have a two-address instruction where the input cannot be clobberedChris Lattner2006-04-281-26/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | and is already available, instead of falling back to emitting a load, fall back to emitting a reg-reg copy. This generates significantly better code for some SSE testcases, as SSE has lots of two-address instructions and none of them are read/modify/write. As one example, this change does: pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255 xorps %XMM2, %XMM5 cmpltps %XMM1, %XMM0 - movaps XMMWORD PTR [%ESP + 52], %XMM0 - movapd %XMM6, XMMWORD PTR [%ESP + 52] + movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 68] movapd XMMWORD PTR [%ESP + 52], %XMM6 movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 36] cmpltps %XMM3, %XMM0 - movaps XMMWORD PTR [%ESP + 20], %XMM0 - movapd %XMM7, XMMWORD PTR [%ESP + 20] + movaps %XMM7, %XMM0 cmpltps %XMM7, XMMWORD PTR [%ESP + 4] movapd XMMWORD PTR [%ESP + 20], %XMM7 cmpltps %XMM4, %XMM0 ... which is far better than a store followed by a load! llvm-svn: 28001
* Add a noteChris Lattner2006-04-281-0/+8
| | | | llvm-svn: 27999
* Add a noteChris Lattner2006-04-271-0/+44
| | | | llvm-svn: 27998
* Add support for inserting undef into a vector. This implementsChris Lattner2006-04-271-3/+14
| | | | | | Transforms/InstCombine/vec_insert_to_shuffle.ll llvm-svn: 27997
* Make x86 isel lowering produce tailcall nodes. They are match to normal callsEvan Cheng2006-04-272-1/+17
| | | | | | | | for now. Patch contributed by Alexander Friedman. llvm-svn: 27994
* A couple of new entries.Evan Cheng2006-04-271-0/+37
| | | | llvm-svn: 27993
* Support for passing 128-bit vector arguments via XMM registers.Evan Cheng2006-04-271-27/+97
| | | | llvm-svn: 27992
* Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector usesEvan Cheng2006-04-271-3/+16
| | | | | | (VAND, VADD, etc.). Legalizer will assert otherwise. llvm-svn: 27991
* OopsEvan Cheng2006-04-271-1/+1
| | | | llvm-svn: 27989
* Bug fix: not updating NumIntRegs.Evan Cheng2006-04-271-60/+65
| | | | llvm-svn: 27988
* Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll andChris Lattner2006-04-271-1/+29
| | | | | | PR748. llvm-svn: 27987
* - Clean up formal argument lowering code. Prepare for vector pass by value work.Evan Cheng2006-04-272-215/+237
| | | | | | - Fixed vararg support. llvm-svn: 27985
* Fix some nondeterminstic behavior in the mem2reg pass that (in addition toChris Lattner2006-04-271-20/+38
| | | | | | | | | | nondeterminism being bad) could cause some trivial missed optimizations (dead phi nodes being left around for later passes to clean up). With this, llvm-gcc4 now bootstraps and correctly compares. I don't know why I never tried to do it before... :) llvm-svn: 27984
* Implement Transforms/IndVarsSimplify/complex-scev.ll, a case where we didn'tChris Lattner2006-04-261-0/+25
| | | | | | recognize some simple affine IV's. llvm-svn: 27982
* Fix fastcc failures.Evan Cheng2006-04-261-0/+3
| | | | llvm-svn: 27980
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