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* [AliasSetTracker] Cleanup more comments. [NFCI]Alina Sbirlea2019-01-281-4/+6
| | | | llvm-svn: 352416
* [MC] Do not consider .ifdef/.ifndef as a useScott Linder2019-01-281-2/+2
| | | | | | | | This is allowed by GAS and seems correct. Differential Revision: https://reviews.llvm.org/D55439 llvm-svn: 352414
* [AArch64] Add 'apple-latest' CPU aliasFrancis Visoiu Mistrih2019-01-281-0/+3
| | | | | | | | | | | | | | The 'apple-latest' alias is supposed to provide a CPU that contains the latest Apple processor model supported by LLVM. This is supposed to be used by tools like lldb to provide a target that supports most of the CPU features. For now, this is mapped to Cyclone. Differential Revision: https://reviews.llvm.org/D56384 llvm-svn: 352412
* [GlobalISel] Add ISel support for @llvm.lifetime.start and @llvm.lifetime.endJessica Paquette2019-01-281-6/+27
| | | | | | | | | | | | | | | | | | This adds ISel support for lifetime markers in opt levels above O0. It also updates the arm64-irtranslator test, and updates some AArch64 tests that use them for added coverage. It also adds a testcase taken from the X86 codegen tests which verified a bug caused by lifetime markers + stack colouring in the past. This is intended to make sure that GISel doesn't re-introduce the bug. (This is basically a straight copy from what SelectionDAG does in SelectionDAGBuilder.cpp) https://reviews.llvm.org/D57187 llvm-svn: 352410
* [CodeGen][X86] Expand UADDSAT to NOT+UMIN+ADDNikita Popov2019-01-282-0/+13
| | | | | | | | | Followup to D56636, this time handling the UADDSAT case by expanding uadd.sat(a, b) to umin(a, ~b) + b. Differential Revision: https://reviews.llvm.org/D56869 llvm-svn: 352409
* [CodeExtractor] Add support for the `swifterror` attributeVedant Kumar2019-01-281-2/+15
| | | | | | | When passing a `swifterror` argument or alloca as an input to an extraction region, mark the input parameter `swifterror`. llvm-svn: 352408
* [AliasSetTracker] Cleanup comments. [NFCI]Alina Sbirlea2019-01-281-5/+8
| | | | llvm-svn: 352406
* [GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSINJessica Paquette2019-01-283-2/+33
| | | | | | | | | | | | This contains all of the legalizer changes from D57197 necessary to select G_FCOS and G_FSIN. It also updates several existing IR tests in test/CodeGen/AArch64 that verify that we correctly lower the G_FCOS and G_FSIN instructions. https://reviews.llvm.org/D57197 3/3 llvm-svn: 352402
* [GlobalISel][AArch64] Add IRTranslator support for G_FCOS and G_FSINJessica Paquette2019-01-281-0/+10
| | | | | | | | | This adds IRTranslator support for the G_FCOS and G_FSIN generic instructions. https://reviews.llvm.org/D57197 2/3 llvm-svn: 352401
* [AliasSetTracker] Update signature to aliasesPointer [NFCI].Alina Sbirlea2019-01-281-11/+13
| | | | llvm-svn: 352399
* [NFC] TLI query with default(on) behavior wrt DAG combines for fmin/fmax ↵Michael Berg2019-01-281-3/+7
| | | | | | target control llvm-svn: 352396
* [SimpleLoopUnswitch] Early check exit for trivial unswitch with MemorySSA.Alina Sbirlea2019-01-281-0/+4
| | | | | | | | | | | | | | | Summary: If MemorySSA is avaiable, we can skip checking all instructions if block has any Defs. (volatile loads are also Defs). We still need to check all instructions for "canThrow", even if no Defs are found. Reviewers: chandlerc Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits Differential Revision: https://reviews.llvm.org/D57129 llvm-svn: 352393
* [X86][AVX] Remove lowerShuffleByMerging128BitLanes 2-lane restrictionSimon Pilgrim2019-01-281-7/+10
| | | | | | | | First step towards adding support for 64-bit unary "sublane" handling (a bit like lowerShuffleAsRepeatedMaskAndLanePermute). This allows us to add lowerV64I8Shuffle handling. llvm-svn: 352389
* [x86] allow more shuffle splitting to avoid vpermps (PR40434)Sanjay Patel2019-01-281-1/+3
| | | | | | | | | | | | | | | This is tricky to make optimal: sometimes we're better off using a single wider op, but other times it makes more sense to combine a narrow ops to achieve the same result. This solves the case from: https://bugs.llvm.org/show_bug.cgi?id=40434 There's potentially a similar change for vectors with 64-bit elements, but it needs adjustments similar to rL352333 to avoid creating infinite loops. llvm-svn: 352380
* Remove no longer needed Arm specific LICENSE.TXT file.Arnaud A. de Grandmaison2019-01-281-47/+0
| | | | | | | | | As the codebase is now under the Apache 2.0 license with LLVM Exceptions, and all Arm's contributions, past or future, are under that new license, this Arm specific LICENSE.TXT is no longer needed, thus removing it. llvm-svn: 352376
* [mips] Support for +abs2008 attributeAleksandar Beserminji2019-01-287-5/+91
| | | | | | | | | | | | | | | | Instruction abs.[ds] is not generating correct result when working with NaNs for revisions prior mips32r6 and mips64r6. To generate a sequence which always produce a correct result, but also to allow user more control on how his code is compiled, attribute +abs2008 is added, so user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Differential Revision: https://reviews.llvm.org/D35983 llvm-svn: 352370
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-286-3/+96
| | | | | | | | | | | | | | | | | | | Summary: Added the intrinsics llvm.amdgcn.interp.p1.f16() and llvm.amdgcn.interp.p2.f16() and related LIT test. The p1 intrinsic generates code appropriate for both 16 and 32 bank LDS. Reviewers: #amdgpu, dstuttard, arsenm, tpr Reviewed By: #amdgpu, arsenm Subscribers: jvesely, mgorny, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46754 llvm-svn: 352357
* [MIPS GlobalISel] Select subPetar Avramovic2019-01-283-2/+70
| | | | | | | | | Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
* [DebugInfo][DAG] Avoid re-ordering of DBG_VALUEsJeremy Morse2019-01-281-21/+50
| | | | | | | | | | | | | | | | This patch improves the placement of DBG_VALUEs when by SelectionDAG, which as documented in PR40427 can go very wrong. At the core of this is ProcessSourceNode, which assumes the last instruction in a BB is the start of the last processed IR instruction, which isn't always true. Instead, use a helper function to call InstrEmitter::EmitNode, that records before-and-after iterators and determines the first of any new instruction created during emission. This is passed to ProcessSourceNode, which can then make more elightened decisions about ordering for DBG_VALUE placement. Differential revision: https://reviews.llvm.org/D57163 llvm-svn: 352350
* [ARM GlobalISel] Support integer division for Thumb2Diana Picus2019-01-281-19/+21
| | | | | | | | | Support G_SDIV, G_UDIV, G_SREM and G_UREM. The only significant difference between arm and thumb mode is that we need to check a different subtarget feature. llvm-svn: 352346
* [X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types ↵Craig Topper2019-01-283-74/+26
| | | | | | | | for the mask argument. Remove and autoupgrade the old intrinsics llvm-svn: 352343
* [AArch64][GlobalISel] Teach RBS about G_FNEG default mapping.Amara Emerson2019-01-281-0/+1
| | | | llvm-svn: 352340
* [AArch64][GlobalISel] Add some missing vector support for FP arithmetic ops.Amara Emerson2019-01-281-2/+2
| | | | | | | Moved the fneg lowering legalization test from AArch64 to X86, as we want to specify that it's already legal. llvm-svn: 352338
* [AArch64][GlobalISel] Add some vector support for fp <-> int conversions.Amara Emerson2019-01-282-2/+6
| | | | | | Some unrelated, but benign, test changes as well due to the test update script. llvm-svn: 352337
* GlobalISel: Don't reduce elements for atomic load/storeMatt Arsenault2019-01-271-1/+9
| | | | | | | This is invalid for the same reason as in the narrowScalar handling for load. llvm-svn: 352334
* [x86] add restriction for lowering to vpermpsSanjay Patel2019-01-271-2/+19
| | | | | | | | | This transform was added with rL351346, and we had an escape for shufps, but we also want one for unpckps vs. vpermps because vpermps doesn't take an immediate shuffle index operand. llvm-svn: 352333
* GlobalISel: Factor fewerElementVectors into separate functionsMatt Arsenault2019-01-271-156/+170
| | | | llvm-svn: 352332
* [X86][SSE] Add UNDEF handling to combineSelect ISD::USUBSAT matching (PR40083)Simon Pilgrim2019-01-271-5/+7
| | | | llvm-svn: 352330
* [X86][SSE] Permit UNDEFs in combineAddToSUBUS matching (PR40083)Simon Pilgrim2019-01-271-3/+4
| | | | llvm-svn: 352328
* [COFF] Add new relocation types.Martin Storsjo2019-01-272-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D57291 llvm-svn: 352324
* [x86] refactor logic in lowerShuffleWithUndefHalfSanjay Patel2019-01-271-28/+49
| | | | | | | | Although this is longer code, this is no-functional-change-intended. The goal is to untangle the conditions under which we bail out, so that's easier to adjust. llvm-svn: 352320
* GlobalISel: Verify load/store has a pointer inputMatt Arsenault2019-01-271-1/+6
| | | | | | | I expected this to be automatically verified, but it seems nothing uses that the type index was declared as a "ptype" llvm-svn: 352319
* Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""Amara Emerson2019-01-271-1/+14
| | | | | | | I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
* [AArch64][GlobalISel] Fix the G_EXTLOAD combiner creating non-extending ↵Amara Emerson2019-01-271-0/+8
| | | | | | | | | | | | | illegal instructions. This fixes loads like 's1 = load %p (load 1 from %p)' being combined with an extend into an illegal 's8 = g_extload %p (load 1 from %p)' which doesn't do any extension, by avoiding touching those < s8 size loads. This bug was uncovered by a verifier update r351584, which I reverted it to keep the bots green. llvm-svn: 352311
* Revert "Add support for prefix-only CLI options"Thomas Preud'homme2019-01-271-14/+5
| | | | | | This reverts commit r351038. llvm-svn: 352310
* [X86] Add some missing blsr patternsGabor Buella2019-01-271-2/+10
| | | | | | | | | | | | | | | | | | The add+and sequence followed by a branch can happen e.g. when looping over the set bits of an integer: ``` while (x != 0) { func(x & ~x); x &= x - 1; } ``` Reviewed By: ctopper Differential Revision: https://reviews.llvm.org/D57296 llvm-svn: 352306
* [X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to ↵Craig Topper2019-01-271-0/+2
| | | | | | | | | | produce SUBREG_TO_REG def32 here means the producing instruction zeroed bits 63:32. We already do this for zext, but it looks like we can get an and+anyext sometimes. Spotted in the diffs from D33587. llvm-svn: 352303
* GlobalISel: Fix typo in assert messagesMatt Arsenault2019-01-271-2/+2
| | | | llvm-svn: 352301
* GlobalISel: Implement narrowScalar for mulMatt Arsenault2019-01-272-0/+48
| | | | llvm-svn: 352300
* GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_roundMatt Arsenault2019-01-272-2/+5
| | | | llvm-svn: 352298
* AMDGPU/GlobalISel: Use scalarize instead of clampMaxNumElementsMatt Arsenault2019-01-261-2/+1
| | | | llvm-svn: 352297
* [GlobalISel][IRTranslator] Fix crash on translation of fneg.Amara Emerson2019-01-261-1/+1
| | | | | | | When the fneg IR instruction was added the code to do translation wasn't tested, and tried to get an invalid operand. llvm-svn: 352296
* AMDGPU/GlobalISel: Legalize more bit opsMatt Arsenault2019-01-262-4/+10
| | | | llvm-svn: 352295
* AMDGPU/GlobalISel: Widen small uaddo/usuboMatt Arsenault2019-01-261-1/+2
| | | | llvm-svn: 352294
* [ValueTracking] Look through casts when determining non-nullnessJohannes Doerfert2019-01-261-0/+22
| | | | | | | | | | Bitcast and certain Ptr2Int/Int2Ptr instructions will not alter the value of their operand and can therefore be looked through when we determine non-nullness. Differential Revision: https://reviews.llvm.org/D54956 llvm-svn: 352293
* [X86] combineAddOrSubToADCOrSBB/combineCarryThroughADD - use oneuse for ↵Simon Pilgrim2019-01-261-2/+3
| | | | | | | | | | entire SDNode Fix issue noted in D57281 that only tested the one use for the SDValue (the result flag), not the entire SUB. I've added the getNode() to make it clearer what is intended than just the -> redirection. llvm-svn: 352291
* [X86] combineCarryThroughADD - add support for X86::COND_A commutations ↵Simon Pilgrim2019-01-261-6/+25
| | | | | | | | | | (PR24545) As discussed on PR24545, we should try to commute X86::COND_A 'icmp ugt' cases to X86::COND_B 'icmp ult' to more optimally bind the carry flag output to a SBB instruction. Differential Revision: https://reviews.llvm.org/D57281 llvm-svn: 352289
* [X86] Fold X86ISD::SBB(ISD::SUB(X,Y),0) -> X86ISD::SBB(X,Y) (PR25858)Simon Pilgrim2019-01-261-0/+9
| | | | | | | | | | We often generate X86ISD::SBB(X, 0) for carry flag arithmetic. I had tried to create test cases for the ADC equivalent (which often uses the same pattern) but haven't managed to find anything yet. Differential Revision: https://reviews.llvm.org/D57169 llvm-svn: 352288
* [X86][SSE] Generalized unsigned compares to support nonsplat constant ↵Simon Pilgrim2019-01-261-7/+10
| | | | | | vectors (PR39859) llvm-svn: 352283
* [x86] add helper for creating a half-width shuffle; NFCSanjay Patel2019-01-261-28/+39
| | | | | | | | | | This reduces a bit of duplication between the combining and lowering places that use it, but the primary motivation is to make it easier to rearrange the lowering logic and solve PR40434: https://bugs.llvm.org/show_bug.cgi?id=40434 llvm-svn: 352280
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