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* [ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2014-05-152-10/+25
| | | | llvm-svn: 208860
* [mips][mips64r6] Add addiupc, aluipc, and auipcDaniel Sanders2014-05-157-4/+93
| | | | | | | | | | | | | | | | Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
* [mips][mips64r6] Add aui, daui, dahi, and datiDaniel Sanders2014-05-153-5/+59
| | | | | | | | | | | | Summary: Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3759 llvm-svn: 208857
* Teach the constant folder to look through bitcast constant expressionsChandler Carruth2014-05-151-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | much more effectively when trying to constant fold a load of a constant. Previously, we only handled bitcasts by trying to find a totally generic byte representation of the constant and use that. Now, we look through the bitcast to see what constant we might fold the load into, and then try to form a constant expression cast of the found value that would be equivalent to loading the value. You might wonder why on earth this actually matters. Well, turns out that the Itanium ABI causes us to create a single array for a vtable where the first elements are virtual base offsets, followed by the virtual function pointers. Because the array is homogenous the element type is consistently i8* and we inttoptr the virtual base offsets into the initial elements. Then constructors bitcast these pointers to i64 pointers prior to loading them. Boom, no more constant folding of virtual base offsets. This is the first fix to LLVM to address the *insane* performance Eric Niebler discovered with Clang on his range comprehensions[1]. There is more to come though, this doesn't *really* fix the problem fully. [1]: http://ericniebler.com/2014/04/27/range-comprehensions/ llvm-svn: 208856
* [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.Daniel Sanders2014-05-151-2/+0
| | | | | | | | | | | | | | | Summary: They aren't implemented for any ISA at the moment. Depends on D3670 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3671 llvm-svn: 208855
* Reverting r208848, reason: build failure: ↵Dinesh Dwivedi2014-05-151-37/+5
| | | | | | sanitizer-x86_64-linux-bootstrap/builds/3399 llvm-svn: 208852
* Added instcombine for 'MIN(MIN(A, 27), 93)' and 'MAX(MAX(A, 93), 27)'Dinesh Dwivedi2014-05-151-2/+18
| | | | | | | | | MIN(MIN(A, 23), 97) -> MIN(A, 23) MAX(MAX(A, 97), 23) -> MAX(A, 97) Differential Revision: http://reviews.llvm.org/D3629 llvm-svn: 208849
* Added inst combine transforms for single bit tests from Chris's noteDinesh Dwivedi2014-05-151-5/+37
| | | | | | | | | | | | | | | if ((x & C) == 0) x |= C becomes x |= C if ((x & C) != 0) x ^= C becomes x &= ~C if ((x & C) == 0) x ^= C becomes x |= C if ((x & C) != 0) x &= ~C becomes x &= ~C if ((x & C) == 0) x &= ~C becomes nothing Z3 Verifications code for above transform http://rise4fun.com/Z3/Pmsh Differential Revision: http://reviews.llvm.org/D3717 llvm-svn: 208848
* Fix some dyslexia in an assert messageJonathan Roelofs2014-05-151-2/+2
| | | | llvm-svn: 208842
* Fix typosAlp Toker2014-05-156-10/+10
| | | | llvm-svn: 208839
* [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out ↵Jiangning Liu2014-05-155-101/+377
| | | | | | argument stack from callee. llvm-svn: 208837
* Move the TargetMachine MC options to MCTargetOptions. No functionalEric Christopher2014-05-152-5/+3
| | | | | | change. llvm-svn: 208832
* InstCombine: Optimize -x s< cstDavid Majnemer2014-05-151-0/+10
| | | | | | | | | | | | | | Summary: This gets rid of a sub instruction by moving the negation to the constant when valid. Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3773 llvm-svn: 208827
* DwarfDebug: Don't set frame index locations on abstract variables.David Blaikie2014-05-141-2/+0
| | | | | | | | Abstract variables should never have/use locations. In this case the data wasn't used, so no functional change intended here, just simplification. llvm-svn: 208820
* DebugInfo: Sure up subprogram variable list handling with more assertions ↵David Blaikie2014-05-141-33/+31
| | | | | | | | | | | | and fewer conditionals. Many old tests using prior schemas still had some brokenness here (both indirect arrays and arrays with single bogus elements). Fixed those up so they don't hit the new assertions. Also reduced nesting in some places, etc. llvm-svn: 208817
* DebugInfo: Assert that a CU's subprogram list contains only subprograms.David Blaikie2014-05-141-2/+2
| | | | llvm-svn: 208816
* Teach llvm-nm to know about fat archives (aka MachOUniversal filesKevin Enderby2014-05-141-0/+20
| | | | | | containing archives). First step as other tools will be updated next. llvm-svn: 208812
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-1438-292/+291
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* InstSimplify: Optimize signed icmp of -(zext V)David Majnemer2014-05-141-0/+22
| | | | | | | | | | | | | | | | Summary: We know that -(zext V) will always be <= zero, simplify signed icmps that have these. Uncovered using http://www.cs.utah.edu/~regehr/souper/ Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3754 llvm-svn: 208809
* DebugInfo: Do not delay attaching DW_AT_inline attribute to abstract ↵David Blaikie2014-05-142-18/+5
| | | | | | | | | | definitions. This is just unneccessary - we only create abstract definitions when we're inlining anyway, so there's no reason to delay this to see if we're going to inline anything. llvm-svn: 208798
* ARM-BE: test files for vector argument passingChristian Pirker2014-05-141-1/+2
| | | | | | Reviewed at http://reviews.llvm.org/D3766 llvm-svn: 208793
* [ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker2014-05-141-0/+17
| | | | | | Reviewed at http://reviews.llvm.org/D3741 llvm-svn: 208792
* Fix ARM EHABI when function has landingpad and nounwind.Logan Chien2014-05-141-8/+7
| | | | | | | | | | | | | | | | | | | | If the function has the landingpad instruction, then the handlerdata should be emitted even if the function has nouwnind attribute. Otherwise, following code will not work: void test1() noexcept { try { throw_exception(); } catch (...) { log_unexpected_exception(); } } Since the cantunwind was incorrectly emitted and the LSDA is not available. llvm-svn: 208791
* X86: If we have an instruction that sets a flag and a zero test on the input ↵Benjamin Kramer2014-05-141-3/+63
| | | | | | | | | | | | | | | | | | | | | of that instruction try to eliminate the test. For example tzcntl %edi, %ebx testl %edi, %edi je .label can be rewritten into tzcntl %edi, %ebx jb .label A minor complication is that tzcnt sets CF instead of ZF when the input is zero, we have to rewrite users of the flags from ZF to CF. Currently we recognize patterns using lzcnt, tzcnt and popcnt. Differential Revision: http://reviews.llvm.org/D3454 llvm-svn: 208788
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-142-4/+52
| | | | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208784
* ARM64: remove unneeded InstPrinter hacksTim Northover2014-05-141-32/+0
| | | | | | | Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. llvm-svn: 208781
* [asan] Fix compiler warnings.Evgeniy Stepanov2014-05-141-5/+3
| | | | llvm-svn: 208769
* [asan] Set debug location in ASan function prologue.Evgeniy Stepanov2014-05-141-2/+14
| | | | | | | | | Most importantly, it gives debug location info to the coverage callback. This change also removes 2 cases of unnecessary setDebugLoc when IRBuilder is created with the same debug location. llvm-svn: 208767
* Fix the case when reordering shuffle and binop produces a constant.Serge Pavlov2014-05-141-13/+13
| | | | | | This resolves PR19737. llvm-svn: 208762
* Update the comments for ComputeMaskedBits, which lost its Mask parameterJay Foad2014-05-142-5/+4
| | | | | | in r154011. llvm-svn: 208757
* [obj2yaml] Support ELF input format in the obj2yaml tool.Simon Atanasyan2014-05-141-1/+2
| | | | | | | | | | The ELF header e_flags field in the MIPS related test cases handled incorrectly. The obj2yaml prints too many flags. I will fix that in the next patches. The patch reviewed by Michael Spencer and Sean Silva. llvm-svn: 208752
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-144-2/+37
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* Optimize integral reciprocal (udiv 1, x and sdiv 1, x) to not use division. ↵Nick Lewycky2014-05-141-1/+20
| | | | | | This fires exactly once in a clang bootstrap, but covers a few different results from http://www.cs.utah.edu/~regehr/souper/ llvm-svn: 208750
* Recommit r208506: DebugInfo: Include lexical scopes in inlined subroutines.David Blaikie2014-05-142-17/+34
| | | | | | | | | | | | | | | | | | | | This was reverted in r208642 due to regressions surrounding file changes within lexical scopes causing inlining information to be lost. The issue was in LexicalScopes::getOrCreateInlinedScope, where I was previously testing "isLexicalBlock" which is false for "DILexicalBlockFile" (a scope used to represent changes in the current file name) and assuming it was then a function (breaking out of the inlined scope path and reaching for the parent non-inlined scopes). By inverting the condition and testing for "isSubprogram" the correct behavior is attained. (also found some weirdness in Clang, see r208742 when reducing this test case - the resulting test case doesn't apply with the Clang fix, but I've added a more realistic test case to inline-scopes.ll which does reproduce the issue and demonstrate the fix) llvm-svn: 208748
* Fix typo in function name.Eric Christopher2014-05-141-5/+5
| | | | llvm-svn: 208743
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
| | | | | | This was broken by r208479 llvm-svn: 208740
* [RuntimeDyld] Fix handling of i386 PC-rel external relocations. This fixesLang Hames2014-05-131-0/+11
| | | | | | | | several more i386 MCJIT regression test failures. <rdar://problem/16889891> llvm-svn: 208735
* Add missing line breaks to debug output in CodeGenPrepareLouis Gerbarg2014-05-131-3/+3
| | | | llvm-svn: 208731
* GVN: Fix non-determinism in map iteration.Benjamin Kramer2014-05-131-4/+7
| | | | | | | | | Iterating over a DenseMaop is non-deterministic and results to unpredictable IR output. Based on a patch by Daniel Reynaud! llvm-svn: 208728
* GVN: rangify a couple of loops.Benjamin Kramer2014-05-131-13/+9
| | | | | | No functionality change. llvm-svn: 208727
* Save the optimization level the subtarget was created with in aEric Christopher2014-05-132-15/+14
| | | | | | | | | | member variable and sink the initialization of crbits into the subtarget feature reset code. No functional change, but this refactor will be used in a future commit. llvm-svn: 208726
* Make the split function use StringRef::split.Eric Christopher2014-05-131-19/+3
| | | | llvm-svn: 208723
* Split GlobalValue into GlobalValue and GlobalObject.Rafael Espindola2014-05-136-42/+39
| | | | | | | | | This allows code to statically accept a Function or a GlobalVariable, but not an alias. This is already a cleanup by itself IMHO, but the main reason for it is that it gives a lot more confidence that the refactoring to fix the design of GlobalAlias is correct. That will be a followup patch. llvm-svn: 208716
* Check explicitly for EHABI and just use the default settings.Joerg Sonnenberger2014-05-131-0/+4
| | | | | | Code depends on the assembler and linker to fix things up... llvm-svn: 208715
* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-131-4/+14
| | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. llvm-svn: 208711
* [CGP] r205941 changed the logic, so that a cast happens *before* 'Result' isJoey Gouly2014-05-131-1/+1
| | | | | | | | | | | compared to 'AddrMode.BaseReg'. In the case that 'AddrMode.BaseReg' is nullptr, 'Result' will also be nullptr, so the cast causes an assertion. We should use dyn_cast_or_null here to check 'Result' is not null and it is an instruction. Bug found by Mats Petersson, and I reduced his IR to get a test case. llvm-svn: 208705
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-131-14/+4
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. llvm-svn: 208704
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-137-21/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-131-4/+14
| | | | llvm-svn: 208689
* [mips] Free up two values in SubtargetFeatureFlag by folding the redundant ↵Daniel Sanders2014-05-132-6/+5
| | | | | | | | | | | | | | | | | | | | | IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 llvm-svn: 208685
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