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* Test commit.Hiroshi Inoue2017-03-161-1/+1
| | | | llvm-svn: 297959
* [AMDGPU] Run always inliner early in optStanislav Mekhanoshin2017-03-161-0/+1
| | | | | | | | | | We can mark functions to always inline early in the opt. Since we do not have call support this early inlining creates opportunities for inter-procedural optimizations which would not occur otherwise. Differential Revision: https://reviews.llvm.org/D31016 llvm-svn: 297958
* Fix: Refactor SimplifyCFG:canSinkInstructions [NFC]Aditya Kumar2017-03-161-18/+17
| | | | | | Differential Revision: https://reviews.llvm.org/D30116 llvm-svn: 297955
* [InstCombine] Liberate assert in InstCombiner::visitZExtBjorn Pettersson2017-03-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The call to canEvaluateZExtd in InstCombiner::visitZExt may return with BitsToClear == SrcTy->getScalarSizeInBits(), but there is an assert that BitsToClear should be smaller than SrcTy->getScalarSizeInBits(). I have a test case that triggers the assert, but it only happens for my downstream target. I've not been able to trigger it for any upstream target. The assert triggered for a piece of code such as this %shr1 = lshr i16 undef, 15 ... %shr2 = lshr i16 %shr1, 1 %conv = zext i16 %shr2 to i32 Normally the lshr instructions are constant folded before we visit the zext (that is why it is so hard to reproduce). The original pattern, before instcombine, is of course a lot more complicated in my test case. The shift count in the second lshr is for example determined by the outcome of a PHI instruction. It seems like other rewrites by instcombine leads up to the pattern above. And then the zext is pulled from the worklist, and visited (hitting the assert), before we detect that the lshr instrucions can be constant folded. Anyway, since the canEvaluateZExtd may return with BitsToClear equal to SrcTy->getScalarSizeInBits(), and since the rewrite that converts the expression type to avoid a zero extend works also for the case where SrcBitsKept ends up being zero, then it should be OK to liberate the assert to assert(BitsToClear <= SrcTy->getScalarSizeInBits() && "Unreasonable BitsToClear"); Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D30993 llvm-svn: 297952
* Revert "[PGO] Value profile for size of memory intrinsic calls"Eric Liu2017-03-162-158/+13
| | | | | | This commit reverts r297897 and r297909. llvm-svn: 297951
* [Support] Add support for getting file system permissions on Windows and ↵James Henderson2017-03-163-8/+58
| | | | | | | | | | | | | | | | | | implement sys::fs::set/getPermissions to work with them This change adds support for functions to set and get file permissions, in a similar manner to the C++17 permissions() function in <filesystem>. The setter uses chmod on Unix systems and SetFileAttributes on Windows, setting the permissions as passed in. The getter simply uses the existing status() function. Prior to this change, status() would always return an unknown value for the permissions on a Windows file, making it impossible to test the new function on Windows. I have therefore added support for this as well. On Linux, prior to this change, the permissions included the file type, which should actually be accessed via a different member of the file_status class. Note that on Windows, only the *_write permission bits have any affect - if any are set, the file is writable, and if not, the file is read-only. This is in common with what MSDN describes for their behaviour of std::filesystem::permissions(), and also what boost::filesystem does. The motivation behind this change is so that we can easily test behaviour on read-only files in LLVM unit tests, but I am sure that others may find it useful in some situations. Reviewers: zturner, amccarth, aaron.ballman Differential Revision: https://reviews.llvm.org/D30736 llvm-svn: 297945
* [PM/Inliner] Fix a bug in r297374 where we would leave stale calls inChandler Carruth2017-03-161-0/+6
| | | | | | | the work queue and crash when trying to visit them after deleting the function containing those calls. llvm-svn: 297940
* Fixing typos.Oren Ben Simhon2017-03-161-4/+5
| | | | llvm-svn: 297932
* [SelectionDAG] Optimize VSELECT->SETCC of incompatible or illegal types.Jonas Paulsson2017-03-165-31/+247
| | | | | | | | | | | | | | | | | | | | | | | | Don't scalarize VSELECT->SETCC when operands/results needs to be widened, or when the type of the SETCC operands are different from those of the VSELECT. (VSELECT SETCC) and (VSELECT (AND/OR/XOR (SETCC,SETCC))) are handled. The previous splitting of VSELECT->SETCC in DAGCombiner::visitVSELECT() is no longer needed and has been removed. Updated tests: test/CodeGen/ARM/vuzp.ll test/CodeGen/NVPTX/f16x2-instructions.ll test/CodeGen/X86/2011-10-19-widen_vselect.ll test/CodeGen/X86/2011-10-21-widen-cmp.ll test/CodeGen/X86/psubus.ll test/CodeGen/X86/vselect-pcmp.ll Review: Eli Friedman, Simon Pilgrim https://reviews.llvm.org/D29489 llvm-svn: 297930
* [ADCE] Remove redundent code [NFC]Tobias Grosser2017-03-161-19/+0
| | | | | | | | | | | | | | | | | | | | | Summary: In commit r289548 ([ADCE] Add code to remove dead branches) a redundant loop nest was accidentally introduced, which implements exactly the same functionality as has already been available right after. This redundancy has been found when inspecting the ADCE code in the context of our recent discussions on post-dominator modeling. This redundant code was also eliminated by r296535 (which sparked the discussion), but only as part of a larger semantic change of the post-dominance modeling. As this redundency in [ADCE] is really just an oversight completely independent of the post-dominance changes under discussion, we remove this redundancy independently. Reviewers: dberlin, david2050 Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31023 llvm-svn: 297929
* Fix pessimising moves.Peter Collingbourne2017-03-161-2/+2
| | | | llvm-svn: 297928
* Support: Add a cache pruning policy parser.Peter Collingbourne2017-03-161-0/+68
| | | | | | | | | The idea is that the policy string fully specifies the policy and is portable between clients. Differential Revision: https://reviews.llvm.org/D31020 llvm-svn: 297927
* CodeGen: BlockPlacement: Reduce TriangleChainCount to 2Kyle Butt2017-03-161-1/+1
| | | | | | | | | This produces a 1% speedup on an important internal Google benchmark (protocol buffers), with no other regressions in google or in the llvm test-suite. Only 5 targets in the entire llvm test-suite are affected, and on those 5 targets the size increase is 0.027% llvm-svn: 297925
* Check that line table entries don't spill over between sections even if ↵David Blaikie2017-03-161-0/+1
| | | | | | they're empty at the end of a section llvm-svn: 297922
* Simplify/make more explicit (by making less explicit in some ways) some ↵David Blaikie2017-03-162-2/+2
| | | | | | function calls llvm-svn: 297921
* [Hexagon] Updating inline saturate lanes for v62 version.Colin LeMahieu2017-03-161-1/+4
| | | | llvm-svn: 297920
* [libFuzzer] add a dummy LLVMFuzzerMutate to afl/afl_driver.cpp ↵Kostya Serebryany2017-03-151-0/+7
| | | | | | (https://github.com/google/oss-fuzz/issues/460) llvm-svn: 297919
* [libFuzzer] call __sanitizer_print_memory_profile with two paramsKostya Serebryany2017-03-152-2/+2
| | | | llvm-svn: 297916
* Remove redundant condition (PR32263). NFCI.Simon Pilgrim2017-03-151-1/+1
| | | | llvm-svn: 297915
* AMDGPU: Allow sinking of addressing modes for atomic_inc/decMatt Arsenault2017-03-152-7/+28
| | | | llvm-svn: 297913
* Revert "[libFuzzer] Use ChooseUnitIdxToMutate to pick item for crossover."Vitaly Buka2017-03-152-3/+3
| | | | | | | | Fails LLVMFuzzer.LLVMFuzzer.value-profile-strncmp.test. This reverts commit r297891. llvm-svn: 297912
* Revert "Revert "[PGO] Minor cleanup for count instruction in ↵Vitaly Buka2017-03-151-1/+4
| | | | | | | | | | SelectInstVisitor."" Previously reverted wrong revision. This reverts commit r297910. llvm-svn: 297911
* Revert "[PGO] Minor cleanup for count instruction in SelectInstVisitor."Vitaly Buka2017-03-151-4/+1
| | | | | | | | Fails LLVMFuzzer.LLVMFuzzer.value-profile-strncmp.test This reverts commit r297892. llvm-svn: 297910
* Fix build failure from r297897.Rong Xu2017-03-151-3/+3
| | | | llvm-svn: 297909
* Support: Simplify the CachePruning API. NFCI.Peter Collingbourne2017-03-152-13/+15
| | | | | | | | | Change the function that implements the pruning into a free function that takes the policy as a struct argument. Differential Revision: https://reviews.llvm.org/D31009 llvm-svn: 297907
* [StackColoring] Remove unused header file for post-order traversal. Update ↵Craig Topper2017-03-151-4/+2
| | | | | | comment that indicated we were using it when we really use a depth-first search. NFC llvm-svn: 297904
* CodeGenPrepare: Sink addressing modes for atomicsMatt Arsenault2017-03-151-1/+30
| | | | llvm-svn: 297903
* [llvm-pdbdump] Add support for diffing the String Table.Zachary Turner2017-03-151-1/+12
| | | | llvm-svn: 297901
* [pdb] Write the module info and symbol record streams.Zachary Turner2017-03-155-66/+193
| | | | | | | | | | | Previously we did not have support for writing detailed module information for each module, as well as the symbol records. This patch adds support for this, and in doing so enables the ability to construct minimal PDBs from just a few lines of YAML. A test is added to illustrate this functionality. llvm-svn: 297900
* Fix up grammar in a comment.Eric Christopher2017-03-151-1/+1
| | | | llvm-svn: 297898
* [PGO] Value profile for size of memory intrinsic callsRong Xu2017-03-152-13/+158
| | | | | | | | | This patch adds the value profile support to profile the size parameter of memory intrinsic calls: memcpy, memcmp, and memmov. Differential Revision: http://reviews.llvm.org/D28965 llvm-svn: 297897
* [PGO] Minor cleanup for count instruction in SelectInstVisitor.Rong Xu2017-03-151-1/+4
| | | | | | | | | | | | | | | | | Summary: NSIs can be double-counted by different operations in SelectInstVisitor. Sink the the update to VM_counting mode only. Also reset the value for each counting operation. Reviewers: davidxl Reviewed By: davidxl Subscribers: xur, llvm-commits Differential Revision: https://reviews.llvm.org/D30999 llvm-svn: 297892
* [libFuzzer] Use ChooseUnitIdxToMutate to pick item for crossover.Vitaly Buka2017-03-152-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D30683 llvm-svn: 297891
* NFC: Corrects comments that were supposed to go in with earlier commit.Adrian McCarthy2017-03-151-4/+5
| | | | llvm-svn: 297887
* [EarlyCSE] reduce indent; NFCISanjay Patel2017-03-151-21/+22
| | | | llvm-svn: 297886
* Introduce NativeEnumModules and NativeCompilandSymbolAdrian McCarthy2017-03-154-2/+115
| | | | | | | | | | | Together, these allow lldb-pdbdump to list all the modules from a PDB using a native reader (rather than DIA). Note that I'll probably be specializing NativeRawSymbol in a subsequent patch. Differential Revision: https://reviews.llvm.org/D30956 llvm-svn: 297883
* [DAGCombine] Bail out if can't create a vector with at least two elementsZvi Rackover2017-03-151-2/+5
| | | | | | | | | | | | | | | | Summary: Fixes pr32278 Reviewers: igorb, craig.topper, RKSimon, spatel, hfinkel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30978 llvm-svn: 297878
* [WebAssembly] Update format of 'names' section.Derek Schuff2017-03-151-6/+11
| | | | | | | | | | | | This change updates to the format of the 'names' sectionin the generated wasm binary to match the latest changesto the design and 'wabt'. Differential Revision: https://reviews.llvm.org/D30950 Patch by Sam Clegg llvm-svn: 297877
* [X86] Add missing BITREVERSE costs for SSE2 vectors and i8/i16/i32/i64 scalarsSimon Pilgrim2017-03-151-0/+19
| | | | | | Prep work for PR31810 llvm-svn: 297876
* [GlobalISel] Avoid translating synthetic constants to new G_CONSTANTS.Ahmed Bougacha2017-03-151-17/+20
| | | | | | | | | | | | | | | | | | | | | Currently, we create a G_CONSTANT for every "synthetic" integer constant operand (for instance, for the G_GEP offset). Instead, share the G_CONSTANTs we might have created by going through the ValueToVReg machinery. When we're emitting synthetic constants, we do need to get Constants from the context. One could argue that we shouldn't modify the context at all (for instance, this means that we're going to use a tad more memory if the constant wasn't used elsewhere), but constants are mostly harmless. We currently do this for extractvalue and all. For constant fcmp, this does mean we'll emit an extra COPY, which is not necessarily more optimal than an extra materialized constant. But that preserves the current intended design of uniqued G_CONSTANTs, and the rematerialization problem exists elsewhere and should be resolved with a single coherent solution. llvm-svn: 297875
* [GlobalISel][AArch64] Select ADDXri.Ahmed Bougacha2017-03-151-0/+4
| | | | | | | We're now able to select ADDWri thanks to the new complex pattern support. Extend that to ADDXri. llvm-svn: 297874
* AMDGPU: Fix unnecessary ands when packing f16 vectorsMatt Arsenault2017-03-156-6/+25
| | | | | | | | | computeKnownBits didn't handle fp_to_fp16 to report the high bits as 0. ARM maps the generic node to an instruction that does not modify the high bits of the register, so introduce a target node where the high bits are known 0. llvm-svn: 297873
* ARM: avoid clobbering register in v6 jump-table expansion.Tim Northover2017-03-153-2/+12
| | | | | | | | | | | If we got unlucky with register allocation and actual constpool placement, we could end up producing a tTBB_JT with an index that's already been clobbered. Technically, we might be able to fix this situation up with a MOV, but I think the constant islands pass is complex enough without having to deal with more weird edge-cases. llvm-svn: 297871
* [PGO] Refactor the code for value profile annotationRong Xu2017-03-151-29/+38
| | | | | | | | | This patch refactors the code for value profile annotation to facilitate of adding other kind of value profiles. Differential Revision: http://reviews.llvm.org/D30989 llvm-svn: 297870
* [GlobalISel] Insert translated switch icmp blocks after switch parent.Ahmed Bougacha2017-03-151-1/+2
| | | | | | | | | Now that we preserve the IR layout, we would end up with all the newly synthesized switch comparison blocks at the end of the function. Instead, use a hopefully more reasonable layout, with the comparison blocks immediately following the switch comparison blocks. llvm-svn: 297869
* [GlobalISel] Preserve IR block layout.Ahmed Bougacha2017-03-151-20/+26
| | | | | | | | | | | | | | It makes the output function layout more predictable; the layout has an effect on performance, we don't want it to be at the mercy of the translator's visitation order and such. The predictable output is also easier to digest. getOrCreateBB isn't appropriately named anymore, as it never needs to create anything. Rename it and extract the MBB creation logic out of it. A couple tests were sensitive to the order. Update them. llvm-svn: 297868
* AMDGPU: Minor SIAnnotateControlFlow cleanupsMatt Arsenault2017-03-151-31/+35
| | | | | | Newline fixes, early return, range loops. llvm-svn: 297865
* [YAML] When outputting, provide the ability to write default values.Zachary Turner2017-03-151-12/+5
| | | | | | | | | Previously, if you attempted to write a key/value pair and the value was equal to the key's default value, we would not output the value. Sometimes it is useful to be able to see this value in the output anyway. llvm-svn: 297864
* [CodeGen] Use APInt::setLowBits/setHighBits/setBitsFrom in more placesCraig Topper2017-03-152-25/+19
| | | | | | | | | | This patch replaces ORs with getHighBits/getLowBits etc. with setLowBits/setHighBits/setBitsFrom. In a few of the places we weren't ORing, but the KnownZero/KnownOne vectors were already initialized to zero. We exploit this in most places already there were just some that were inconsistent. Differential Revision: https://reviews.llvm.org/D30965 llvm-svn: 297860
* [GlobalISel] Remove dead member. NFC.Ahmed Bougacha2017-03-151-1/+0
| | | | llvm-svn: 297855
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