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* LoopVectorizer: Calculate the number of pointers to disambiguate at runtime ↵Nadav Rotem2013-04-261-4/+11
| | | | | | based on the numbers of reads and writes. llvm-svn: 180593
* Revert "[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls ↵Michael Gottesman2013-04-261-38/+0
| | | | | | | | | | | | | | that were once autoreleaseRV instructions." This reverts commit r180222. I think this might tie in with a different problem which will require a different approach potentially. I am reverting this in the case I need to go down that second path. My apologies for the noise. = /. llvm-svn: 180590
* Mips assembler: .set reorder supportJack Carter2013-04-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
* Make function documentation conform to llvm standards.Preston Gurd2013-04-251-30/+32
| | | | | | Expunge all remaining traces and use of live variable information. llvm-svn: 180577
* ARM cost model: Integer div and rem is lowered to a function callArnold Schwaighofer2013-04-251-0/+68
| | | | | | | | Reflect this in the cost model. I observed this in MiBench/consumer-lame. radar://13354716 llvm-svn: 180576
* Re-enabling MCJIT object caching with memory leak fixedAndrew Kaylor2013-04-252-18/+68
| | | | llvm-svn: 180575
* revert r179735, it has no testcases, and doesn't really make sense.Chris Lattner2013-04-253-32/+28
| | | | llvm-svn: 180574
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-257-0/+270
| | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
* LoopVectorizer: No need to generate pointer disambiguation checks between ↵Nadav Rotem2013-04-251-4/+12
| | | | | | readonly pointers. llvm-svn: 180570
* [mc-coff] Forward Linker Option flags into the .drectve sectionReid Kleckner2013-04-251-0/+46
| | | | | | | | | | | | | | Summary: This is modelled on the Mach-O linker options implementation and should support a Clang implementation of #pragma comment(lib/linker). Reviewers: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D724 llvm-svn: 180569
* Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola2013-04-252-2/+17
| | | | | | Patch by Kai Nacke. This matches the gnu as output. llvm-svn: 180568
* Use a pointer as the relocation iterator.Rafael Espindola2013-04-251-24/+29
| | | | | | | | Since the relocation iterator walks only the relocations in one section, we can just use a pointer and avoid fetching information about the section at every reference. llvm-svn: 180262
* Clarify getRelocationAddress x getRelocationOffset a bit.Rafael Espindola2013-04-253-18/+3
| | | | | | | | | | getRelocationAddress is for dynamic libraries and executables, getRelocationOffset for relocatable objects. Mark the getRelocationAddress of COFF and MachO as not implemented yet. Add a test of ELF's. llvm-readobj -r now prints the same values as readelf -r. llvm-svn: 180259
* Fix constant folding for one lane vector types. Constant folding one lane ↵Silviu Baranga2013-04-251-1/+1
| | | | | | vector types not returns a vector instead of a scalar. llvm-svn: 180254
* Revert "Adding object caching support to MCJIT"Rafael Espindola2013-04-252-65/+18
| | | | | | | | | | This reverts commit 07f03923137a91e3cca5d7fc075a22f8c9baf33a. Looks like it broke the valgrind bot: http://lab.llvm.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/649 llvm-svn: 180249
* Revert "Exposing MCJIT through C API"Rafael Espindola2013-04-251-48/+0
| | | | | | | | | | This reverts commit 8c31b298149ca3c3f2bbd9e8aa9a01c4d91f3d74. It looks like this commit broke some bots: http://lab.llvm.org:8011/builders/llvm-ppc64-linux2/builds/5209 llvm-svn: 180248
* [mips] Add definitions of micromips load and store instructions.Akira Hatanaka2013-04-254-17/+43
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180241
* [mips] Add definitions of micromips shift instructions.Akira Hatanaka2013-04-254-12/+62
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180238
* R600: Initialize BooleanVectorContentsTom Stellard2013-04-241-0/+1
| | | | | | Fixes test/CodeGen/R600/setcc.ll llvm-svn: 180231
* R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard2013-04-241-1/+1
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. llvm-svn: 180230
* Exposing MCJIT through C APIAndrew Kaylor2013-04-241-0/+48
| | | | | | Patch by Filip Pizlo llvm-svn: 180229
* Fix for r180193 - MI Sched: eliminate local vreg.Andrew Trick2013-04-241-2/+6
| | | | | | | | | Fixes PR15838. Need to check for blocks with nothing but dbg.value. I'm not sure how to force this situation with a unit test. I tried to reduce the test case in PR15838 (1k lines of metadata) but gave up. llvm-svn: 180227
* [inline asm] Fix a crasher for an invalid value type/register class.Chad Rosier2013-04-241-4/+11
| | | | | | rdar://13731657 llvm-svn: 180226
* Making invalidateInstructionCache automatic in SectionMemoryManagerAndrew Kaylor2013-04-241-0/+5
| | | | llvm-svn: 180225
* [objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that ↵Michael Gottesman2013-04-241-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | were once autoreleaseRV instructions. Due to the semantics of ARC, we must be extremely conservative with autorelease calls inserted by the frontend since ARC gaurantees that said object will be in the autorelease pool after that point, an optimization invariant that the optimizer must respect. On the other hand, we are allowed significantly more flexibility with autoreleaseRV instructions. Often times though this flexibility is disrupted by early transformations which transform objc_autoreleaseRV => objc_autorelease if said instruction is no longer being used as part of an RV pair (generally due to inlining). Since we can not tell the difference in between an autorelease put into place by the frontend and one created through said ``strength reduction'' we can not perform these optimizations. The addition of this set gets around said issues by allowing us to differentiate in between said two cases. rdar://problem/13697741. llvm-svn: 180222
* Fixed comment typo.Michael Gottesman2013-04-241-1/+1
| | | | llvm-svn: 180221
* Use pointers to iterate over symbols.Rafael Espindola2013-04-241-30/+36
| | | | | | | | While here, don't report a dummy symbol for relocations that don't have symbols. We used to says such relocations were for the first defined symbol, but now we return end_symbols(). The llvm-readobj output change agrees with otool. llvm-svn: 180214
* LoopVectorizer: Change variable name Stride to ConsecutiveStrideArnold Schwaighofer2013-04-241-6/+6
| | | | | | | | This makes it easier to read the code. No functionality change. llvm-svn: 180197
* LoopVectorize: Scalarize padded typesArnold Schwaighofer2013-04-241-1/+9
| | | | | | | | | | | | | | | | | | This patch disables memory-instruction vectorization for types that need padding bytes, e.g., x86_fp80 has 10 bytes store size with 6 bytes padding in darwin on x86_64. Because the load/store vectorization is performed by the bit casting to a packed vector, which has incompatible memory layout due to the lack of padding bytes, the present vectorizer produces inconsistent result for memory instructions of those types. This patch checks an equality of the AllocSize of a scalar type and allocated size for each vector element, to ensure that there is no padding bytes and the array can be read/written using vector operations. Patch by Daisuke Takahashi! Fixes PR15758. llvm-svn: 180196
* LoopVectorizer: Bail out if we don't have datalayout we need itArnold Schwaighofer2013-04-241-0/+5
| | | | llvm-svn: 180195
* Revert r180189.Rafael Espindola2013-04-241-29/+24
| | | | | | | This should bring the ppc bots back. I will try to write a test that would have found the problem on a little endian system too. llvm-svn: 180194
* MI Sched: eliminate local vreg copies.Andrew Trick2013-04-241-7/+194
| | | | | | | | | | | | | | | | For now, we just reschedule instructions that use the copied vregs and let regalloc elliminate it. I would really like to eliminate the copies on-the-fly during scheduling, but we need a complete implementation of repairIntervalsInRange() first. The general strategy is for the register coalescer to eliminate as many global copies as possible and shrink live ranges to be extended-basic-block local. The coalescer should not have to worry about resolving local copies (e.g. it shouldn't attemp to reorder instructions). The scheduler is a much better place to deal with local interference. The coalescer side of this equation needs work. llvm-svn: 180193
* Register Coalescing: add a flag to disable rescheduling.Andrew Trick2013-04-241-2/+8
| | | | | | | | When MachineScheduler is enabled, this functionality can be removed. Until then, provide a way to disable it for test cases and designing MachineScheduler heuristics. llvm-svn: 180192
* MI Sched: regpressure tracing.Andrew Trick2013-04-241-0/+8
| | | | llvm-svn: 180191
* Formatting fixes.Rafael Espindola2013-04-241-31/+20
| | | | llvm-svn: 180190
* Use a pointer as the relocation iterator.Rafael Espindola2013-04-241-23/+28
| | | | | | | | Since the relocation iterator walks only the relocations in one section, we can just use a pointer and avoid fetching information about the section at every reference. llvm-svn: 180189
* Formatting.Eric Christopher2013-04-241-1/+1
| | | | llvm-svn: 180186
* Align the __LD,__compact_unwind section.Bill Wendling2013-04-241-7/+16
| | | | | | | | I know what would be cool! We should align the compact unwind section because aligned data access is faster. <rdar://problem/13723271> llvm-svn: 180171
* Fix dependency layering issues caused by r180112.Eric Christopher2013-04-231-1/+0
| | | | | | Patch by Tom Stellard. (Committed while he's afk per request) llvm-svn: 180157
* Adding object caching support to MCJITAndrew Kaylor2013-04-232-18/+65
| | | | llvm-svn: 180146
* Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma2013-04-232-176/+149
| | | | llvm-svn: 180145
* Hexagon: Define relations for GP-relative instructions.Jyotsna Verma2013-04-231-15/+17
| | | | | | No functionality change. llvm-svn: 180144
* Make sure the instruction right after an inlined function has aAdrian Prantl2013-04-231-4/+10
| | | | | | | | | | debug location. This solves a problem where range of an inlined subroutine is emitted wrongly. Patch by Manman Ren. Fixes rdar://problem/12415623 llvm-svn: 180140
* Add more tests for r179925 to verify correct handling of signext/zeroext; ↵Stephen Lin2013-04-231-3/+6
| | | | | | strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change) llvm-svn: 180138
* Lowercase "is" boolean variable prefix for consistency within function, no ↵Stephen Lin2013-04-231-12/+12
| | | | | | functionality change. llvm-svn: 180136
* Hexagon: Remove assembler mapped instruction definitions.Jyotsna Verma2013-04-235-108/+80
| | | | llvm-svn: 180133
* Change commentary for PowerPC Boolean vector contents.Bill Schmidt2013-04-231-1/+2
| | | | | | No functional change intended. llvm-svn: 180131
* [mips] Compare splat value with element size instead of calling isUIntN.Akira Hatanaka2013-04-231-2/+2
| | | | | | No intended changes in functionality. llvm-svn: 180130
* DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider ↵Owen Anderson2013-04-232-2/+4
| | | | | | | | | VSETCC without first checking the target's vector boolean contents. This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents. The included change fixes the PowerPC tests, and was OK'd by Hal. llvm-svn: 180129
* Testing for _XCR_XFEATURE_ENABLED_MASK instead of a specific MSVC version ↵Aaron Ballman2013-04-231-1/+1
| | | | | | because some MSVC 2010 SP1 installations do not have the _xgetbv intrinsic. Patch thanks to Serge Pavlov! llvm-svn: 180125
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