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* MC: Add support for mach-o build_versionMatthias Braun2017-12-145-81/+219
| | | | | | | | LC_BUILD_VERSION is a new load command superseding the previously used LC_XXX_MIN_VERSION commands. This adds an assembler directive along with encoding/streaming support. llvm-svn: 320661
* Recommit r320461 "[X86] Use regular expressions more aggressively to reduce ↵Craig Topper2017-12-134-1032/+48
| | | | | | | | | | | | | | the number of scheduler entries needed for FMA3 instructions." I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name. Original commit message: When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320655
* [EarlyCSE] recognize swapped variants of abs/nabs as equivalentSanjay Patel2017-12-131-9/+12
| | | | | | | | Extends https://reviews.llvm.org/rL320640 Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320653
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-133-11/+19
| | | | | | | | | | | | | | | | | Two issues were found about machine inst scheduler when compiling ProRender with -g for amdgcn target: GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it should not since DBG_VALUE is not mapped in LiveIntervals. when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D41132 llvm-svn: 320650
* [CodeView] Teach clang to emit the .debug$H COFF section.Zachary Turner2017-12-136-13/+186
| | | | | | | | | | | | | | | Currently this is an LLVM extension to the COFF spec which is experimental and intended to speed up linking. For now it is behind a hidden cl::opt flag, but in the future we can move it to a "real" cc1 flag and have the driver pass it through whenever it is appropriate. The patch to actually make use of this section in lld will come in a followup. Differential Revision: https://reviews.llvm.org/D40917 llvm-svn: 320649
* Recover some overzealously removed includes.Michael Zolotukhin2017-12-134-0/+4
| | | | llvm-svn: 320648
* Speculative build fix for lld on Linux after Michael's #include removalsHans Wennborg2017-12-131-0/+1
| | | | llvm-svn: 320645
* [WebAssembly] Use bitfield types in wasm YAML representationSam Clegg2017-12-131-0/+22
| | | | | | Differential Revision: https://reviews.llvm.org/D41202 llvm-svn: 320642
* Reverting [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-135-365/+89
| | | | | | | Stage 2 bootstrap failed: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434 llvm-svn: 320641
* [EarlyCSE] recognize commuted and swapped variants of min/max as equivalent ↵Sanjay Patel2017-12-131-0/+27
| | | | | | | | | | | | | (PR35642) As shown in: https://bugs.llvm.org/show_bug.cgi?id=35642 ...we can have different forms of min/max, so we should recognize those here in EarlyCSE similar to how we already handle binops and compares that can commute. Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320640
* Remove redundant includes from lib/Target/X86.Michael Zolotukhin2017-12-1312-31/+0
| | | | llvm-svn: 320636
* Remove redundant includes from lib/Target/ARM.Michael Zolotukhin2017-12-138-17/+0
| | | | llvm-svn: 320635
* Remove redundant includes from lib/Target/AArch64.Michael Zolotukhin2017-12-137-13/+0
| | | | llvm-svn: 320634
* Remove redundant includes from lib/Target/*.cpp.Michael Zolotukhin2017-12-133-5/+0
| | | | llvm-svn: 320633
* Remove redundant includes from various places.Michael Zolotukhin2017-12-134-7/+0
| | | | llvm-svn: 320629
* Remove redundant includes from lib/Transforms.Michael Zolotukhin2017-12-1331-48/+0
| | | | llvm-svn: 320628
* Remove redundant includes from lib/Support.Michael Zolotukhin2017-12-136-6/+0
| | | | llvm-svn: 320627
* Remove redundant includes from lib/ProfileData.Michael Zolotukhin2017-12-132-9/+0
| | | | llvm-svn: 320626
* Remove redundant includes from lib/Object.Michael Zolotukhin2017-12-133-13/+0
| | | | llvm-svn: 320625
* Remove redundant includes from lib/MC.Michael Zolotukhin2017-12-1310-19/+0
| | | | llvm-svn: 320624
* Remove redundant includes from lib/LTO.Michael Zolotukhin2017-12-133-9/+0
| | | | llvm-svn: 320623
* Remove redundant includes from lib/IR.Michael Zolotukhin2017-12-139-12/+0
| | | | llvm-svn: 320622
* Remove redundant includes from lib/ExecutionEngine.Michael Zolotukhin2017-12-133-4/+0
| | | | llvm-svn: 320621
* Remove redundant includes from lib/DebugInfo.Michael Zolotukhin2017-12-1324-33/+0
| | | | llvm-svn: 320620
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-1332-56/+0
| | | | llvm-svn: 320619
* Remove redundant includes from lib/Bitcode.Michael Zolotukhin2017-12-132-5/+0
| | | | llvm-svn: 320618
* Remove redundant includes from lib/Analysis.Michael Zolotukhin2017-12-1312-14/+0
| | | | llvm-svn: 320617
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-138-78/+128
| | | | | | | | | | | | | | | | | | | | | Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. llvm-svn: 320614
* [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-135-89/+365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: See D37528 for a previous (non-deferred) version of this patch and its description. Preserves dominance in a deferred manner using a new class DeferredDominance. This reduces the performance impact of updating the DominatorTree at every edge insertion and deletion. A user may call DDT->flush() within JumpThreading for an up-to-date DT. This patch currently has one flush() at the end of runImpl() to ensure DT is preserved across the pass. LVI is also preserved to help subsequent passes such as CorrelatedValuePropagation. LVI is simpler to maintain and is done immediately (not deferred). The code to perfom the preversation was minimally altered and was simply marked as preserved for the PassManager to be informed. This extends the analysis available to JumpThreading for future enhancements. One example is loop boundary threading. Reviewers: dberlin, kuhar, sebpop Reviewed By: kuhar, sebpop Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40146 llvm-svn: 320612
* [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases loadAditya Kumar2017-12-131-2/+2
| | | | | | | | | | | | | | w.r.t. the paper "A Practical Improvement to the Partial Redundancy Elimination in SSA Form" (https://sites.google.com/site/jongsoopark/home/ssapre.pdf) Proper dominance check was missing here, so having a loopinfo should not be required. Committing this diff as this fixes the bug, if there are further concerns, I'll be happy to work on them. Differential Revision: https://reviews.llvm.org/D39781 llvm-svn: 320607
* Ignore metainstructions during the shrink wrap analysisAdrian Prantl2017-12-131-0/+4
| | | | | | | | | | Shrink wrapping should ignore DBG_VALUEs referring to frame indices, since the presence of debug information must not affect code generation. Differential Revision: https://reviews.llvm.org/D41187 llvm-svn: 320606
* Fix link failure on one build bot introduced by r320584.Nemanja Ivanovic2017-12-131-1/+3
| | | | llvm-svn: 320589
* Reverted r320229. It broke tests on builder ↵Galina Kistanova2017-12-131-118/+4
| | | | | | llvm-clang-x86_64-expensive-checks-win. llvm-svn: 320588
* [PowerPC] MachineSSA pass to reduce the number of CR-logical operationsNemanja Ivanovic2017-12-135-0/+740
| | | | | | | | | | | | | | The initial implementation of an MI SSA pass to reduce cr-logical operations. Currently, the only operations handled by the pass are binary operations where both CR-inputs come from the same block and the single use is a conditional branch (also in the same block). Committing this off by default to allow for a period of field testing. Will enable it by default in a follow-up patch soon. Differential Revision: https://reviews.llvm.org/D30431 llvm-svn: 320584
* [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule testsSimon Pilgrim2017-12-133-1/+4
| | | | | | Add missing RDTSCP itinerary llvm-svn: 320581
* [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury2017-12-131-0/+3
| | | | | | | | Unfortunately these aren't defined explicitly in the privileged spec, but the GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the usual `sfence.vma rs, rt`. llvm-svn: 320575
* [FuzzMutate] Only generate loads and stores to the first class sized typesIgor Laevsky2017-12-131-1/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D41109 llvm-svn: 320573
* [FuzzMutate] Correctly split landingpad blocksIgor Laevsky2017-12-131-2/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D41112 llvm-svn: 320571
* [X86][SSE] MOVMSK only uses the sign bit from each vector elementSimon Pilgrim2017-12-131-0/+22
| | | | | | | | | | Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK We'd probably get more hits if SimplifyDemandedBits was better at handling vectors... Differential Revision: https://reviews.llvm.org/D41119 llvm-svn: 320570
* [RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury2017-12-132-0/+46
| | | | | | | | | | | | | | | Adds the assembler aliases for the floating point instructions which can be mapped to a single canonical instruction. The missing pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. This patch builds upon D40902. Differential Revision: https://reviews.llvm.org/D41071 Patch by Mario Werner. llvm-svn: 320569
* Reintroduce r320049, r320014 and r319894.Igor Laevsky2017-12-132-0/+32
| | | | | | OpenGL issues should be fixed by now. llvm-svn: 320568
* [DAG] Promote ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-12-131-1/+24
| | | | | | | | Add missing case that was not implemented yet. Differential Revision: https://reviews.llvm.org/D38942 llvm-svn: 320567
* [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and ↵Francis Visoiu Mistrih2017-12-133-6/+9
| | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`. Only debug syntax is affected. llvm-svn: 320566
* [CodeGen] Print target index operands as target-index(target-specific) + 8 ↵Francis Visoiu Mistrih2017-12-132-28/+24
| | | | | | | | | | in both MIR and debug output Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`. Only debug syntax is affected. llvm-svn: 320565
* [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and ↵Francis Visoiu Mistrih2017-12-132-9/+14
| | | | | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of `<cp#0-8>`. Only debug syntax is affected. Differential Revision: https://reviews.llvm.org/D41116 llvm-svn: 320564
* [mips] Provide additional DSP bitconvert patternsStefan Maksimovic2017-12-131-0/+4
| | | | | | | | | Previously, v2i16 -> f32 bitcast could not be matched. Add patterns to support matching this and similar types of bitcasts. Differential revision: https://reviews.llvm.org/D40959 llvm-svn: 320562
* [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming ↵Alex Bradbury2017-12-132-98/+100
| | | | | | | | | | | | | | convention When an instruction mnemonic contains a '.', we usually name the instruction with a _ in that place. e.g. fadd.s -> FADD_S. This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP. Also includes some minor formatting changes in RISCVInstrInfoC.td to better align it with the formatting conventions in the rest of the backend. llvm-svn: 320560
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-132-22/+22
| | | | | | | We sort these helper functions and td definitions by bit width. simm6 was previously out-of-order with respect to the others. llvm-svn: 320559
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-135-20/+390
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* Revert "[CGP] Enable select in complex addr mode"Serguei Katkov2017-12-131-1/+1
| | | | | | | | Causes: Assertion `ScaledReg == nullptr' failed. This actually a revert of rL320551. llvm-svn: 320553
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