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* Add a few more functions to TargetLibraryInfo. More of rdar://10500969.Chad Rosier2011-12-011-1/+16
| | | | llvm-svn: 145596
* For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher2011-12-011-1/+17
| | | | | | | | sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 llvm-svn: 145579
* Add some missing anchors.David Blaikie2011-12-013-0/+7
| | | | llvm-svn: 145578
* Pass AVX vectors which are arguments to varargs functions on the stack. ↵Eli Friedman2011-12-011-4/+9
| | | | | | <rdar://problem/10463281>. llvm-svn: 145573
* Added instcombine pattern to spot comparing -val or val against 0.Pete Cooper2011-12-011-0/+14
| | | | | | | | (val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0" Fixes <rdar://problem/10482509> llvm-svn: 145563
* Propagate TargetLibraryInfo throughout ConstantFolding.cpp and Chad Rosier2011-12-0113-259/+394
| | | | | | | InstructionSimplify.cpp. Other fixups as needed. Part of rdar://10500969 llvm-svn: 145559
* Make use of "getScalarType()". No functionality change.Nick Lewycky2011-12-011-8/+3
| | | | llvm-svn: 145556
* Small fix for assembler generation on Darwin PPC64. Patch by Michael ↵Eli Friedman2011-12-011-1/+1
| | | | | | Kostylev. PR11437. llvm-svn: 145553
* make asan work at -O0, llvm part. Patch by glider@google.comKostya Serebryany2011-11-301-1/+1
| | | | llvm-svn: 145530
* Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin2011-11-301-0/+349
| | | | | | remaining FMA4 instructions and intrinsics with tests. llvm-svn: 145525
* Make GlobalMerge honor the preferred alignment on globals without an ↵Eli Friedman2011-11-301-1/+1
| | | | | | | | explicitly specified alignment. <rdar://problem/10497732>. llvm-svn: 145523
* Remove unused variableMatt Beaumont-Gay2011-11-301-2/+0
| | | | llvm-svn: 145517
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-304-43/+82
| | | | llvm-svn: 145510
* Add a few functions to TargetLibraryInfo.Chad Rosier2011-11-301-2/+50
| | | | llvm-svn: 145508
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-305-5/+30
| | | | llvm-svn: 145504
* X86: Turns out bulldozer also supports sse42 and lzcnt.Benjamin Kramer2011-11-301-11/+6
| | | | | | | While at it remove the barcelona/instanbul/shanghai subtargets, they're unsupported by GCC and look pretty broken. llvm-svn: 145494
* X86: Add subtargets for AMD's bulldozer.Benjamin Kramer2011-11-301-0/+6
| | | | llvm-svn: 145493
* X86: PerformOrCombine introduced a vselect node with a wrong order of ↵Nadav Rotem2011-11-301-1/+1
| | | | | | operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). llvm-svn: 145488
* Add instruction selection support for AVX2 horizontal add/sub instructions.Craig Topper2011-11-301-24/+49
| | | | llvm-svn: 145487
* Merge VPERM2F128/VPERM2I128 ISD node types.Craig Topper2011-11-304-71/+50
| | | | llvm-svn: 145485
* Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node ↵Craig Topper2011-11-307-142/+135
| | | | | | type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. llvm-svn: 145483
* LSR: handle the expansion of phi operands that use postinc forms of the IV.Andrew Trick2011-11-301-36/+68
| | | | | | Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed. llvm-svn: 145482
* Whitespace.Chad Rosier2011-11-301-3/+1
| | | | llvm-svn: 145470
* Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functionalChad Rosier2011-11-301-6/+6
| | | | | | change intended. llvm-svn: 145468
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-305-6/+141
| | | | llvm-svn: 145464
* Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable Chad Rosier2011-11-293-3/+9
| | | | | | | | (fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is specified. rdar://10466410 llvm-svn: 145460
* Tidy up a bit.Jim Grosbach2011-11-292-33/+10
| | | | llvm-svn: 145458
* Add comment.Jim Grosbach2011-11-291-0/+1
| | | | llvm-svn: 145456
* ARM parsing aliases for data-size suffices on VST1.Jim Grosbach2011-11-291-19/+56
| | | | llvm-svn: 145454
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-292-4/+4
| | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" llvm-svn: 145451
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-294-52/+47
| | | | llvm-svn: 145450
* Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it ↵Evan Cheng2011-11-291-0/+6
| | | | | | was generating poor code for some SSE builtins. llvm-svn: 145448
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-294-44/+47
| | | | llvm-svn: 145442
* Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen2011-11-295-28/+15
| | | | | | | | | Like V_SET0, these instructions are expanded by ExpandPostRA to xorps / vxorps so they can participate in execution domain swizzling. This also makes the AVX variants redundant. llvm-svn: 145440
* Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should ↵Stepan Dyatkovskiy2011-11-291-1/+5
| | | | | | not be changed inside the uses enumeration loop. llvm-svn: 145432
* If fast-isel fails, remove dead instructions generated during the failed Chad Rosier2011-11-291-0/+27
| | | | | | attempt. llvm-svn: 145425
* comment.Andrew Trick2011-11-291-0/+4
| | | | llvm-svn: 145422
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-2976-563/+0
| | | | llvm-svn: 145420
* Fix a theoretical problem (not seen in the wild): if different instances of aDuncan Sands2011-11-292-1/+5
| | | | | | | | | | | | | | | weak variable are compiled by different compilers, such as GCC and LLVM, while LLVM may increase the alignment to the preferred alignment there is no reason to think that GCC will use anything more than the ABI alignment. Since it is the GCC version that might end up in the final program (as the linkage is weak), it is wrong to increase the alignment of loads from the global up to the preferred alignment as the alignment might only be the ABI alignment. Increasing alignment up to the ABI alignment might be OK, but I'm not totally convinced that it is. It seems better to just leave the alignment of weak globals alone. llvm-svn: 145413
* MC/X86/COFF: Allow quotes in names when targeting MS/Windows,Michael J. Spencer2011-11-294-5/+31
| | | | | | | | | | as MC is the only assembler we support. This splits MS/Windows and GNU/Windows ASM infos into two seperate classes. While there is currently only one difference, full MS C++ ABI support will require many more. llvm-svn: 145409
* Fixed ObjectFile functions:Danil Malyshev2011-11-294-32/+140
| | | | | | | | | | | - getSymbolOffset() renamed as getSymbolFileOffset() - getSymbolFileOffset(), getSymbolAddress(), getRelocationAddress() returns same result for ELFObjectFile, MachOObjectFile and COFFObjectFile. - added getRelocationOffset() - fixed MachOObjectFile::getSymbolSize() - fixed MachOObjectFile::getSymbolSection() - fixed MachOObjectFile::getSymbolOffset() for symbols without section data. llvm-svn: 145408
* Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.Elena Demikhovsky2011-11-291-1/+1
| | | | | | | Added a test. Thanks Bruno for reviewing the patch. llvm-svn: 145403
* Fix shuffle decoding for memory forms for (V)SHUFPS/D.Craig Topper2011-11-291-6/+12
| | | | llvm-svn: 145392
* Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle ↵Craig Topper2011-11-295-30/+82
| | | | | | decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. llvm-svn: 145390
* [Win32] Catch exceptions (eg. segfault) on waiting for invoked clang from ↵NAKAMURA Takumi2011-11-292-2/+12
| | | | | | | | | | | | the driver. clang/lib/Driver/Driver.cpp: Don't pass through negative exit status, or parent would be confused. llvm::sys::Program::Wait(): Suppose 0x8000XXXX and 0xC000XXXX as abnormal exit code and pass it as negative value. Win32 Exception Handler: Exit with ExceptionCode on an unhandle exception. llvm-svn: 145389
* Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow ↵Craig Topper2011-11-292-5/+9
| | | | | | execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. llvm-svn: 145376
* Correctly mark VPERM2F128 as being an FP instruction and add execution ↵Craig Topper2011-11-292-1/+3
| | | | | | domain fixing support to convert it to VPERM2I128 for AVX2. llvm-svn: 145370
* MachO doesn't support the protected visibility. Don't default to 'global' ↵Bill Wendling2011-11-291-1/+2
| | | | | | here. <rdar://problem/10396775> llvm-svn: 145368
* SCEV fix. In general, Add/Mul expressions should not inherit NSW/NUW.Andrew Trick2011-11-292-10/+14
| | | | | | | This reverts r139450, fixes r139453, and adds much needed comments and a unit test. llvm-svn: 145367
* Make SCEV print <nsw><nuw> for Add/MulExpr.Andrew Trick2011-11-291-0/+8
| | | | llvm-svn: 145364
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