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* [X86] Emit more efficient >= comparisons against 0David Majnemer2015-08-191-1/+49
| | | | | | | | | | | | | | | | | | | | | | | We don't do a great job with >= 0 comparisons against zero when the result is used as an i8. Given something like: void f(long long LL, bool *B) { *B = LL >= 0; } We used to generate: shrq $63, %rdi xorb $1, %dil movb %dil, (%rsi) Now we generate: testq %rdi, %rdi setns (%rsi) Differential Revision: http://reviews.llvm.org/D12136 llvm-svn: 245498
* [WebAssembly] Use the default alignment for SIMD types.Dan Gohman2015-08-191-2/+2
| | | | | | | | | Previously WebAssembly's datalayout string had -v128:8:128. This had been an attempt to declare a certain level of support for unaligned SIMD accesses. However, clang makes its own determinations for SIMD alignment that are independent of the datalayout string, so this wasn't actually meaningful. llvm-svn: 245494
* [DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to ↵Simon Pilgrim2015-08-191-5/+79
| | | | | | | | | | VECTOR_SHUFFLE. Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle. Differential Revision: http://reviews.llvm.org/D12125 llvm-svn: 245490
* Replace some calls to isa<LandingPadInst> with isEHPad()David Majnemer2015-08-194-7/+7
| | | | | | No functionality change is intended. llvm-svn: 245487
* [Sparc]: asm-only support for the ldstub instruction.Douglas Katzman2015-08-191-0/+11
| | | | llvm-svn: 245485
* MIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.Alex Lorenz2015-08-191-14/+13
| | | | | | | Besides storing the operand's source range, this structure now stores other attributes as well, so the name should reflect this fact. llvm-svn: 245483
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-194-19/+119
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* Temporary fix for the self-host failures introduced by rL244921.Nemanja Ivanovic2015-08-191-1/+2
| | | | | | | | | This revision has introduced an issue that only affects bootstrapped compiler when it is printing the ASM. I am working on resolving the issue, but in the meantime, I'm disabling the legalization of scalar_to_vector operation for v2i64 and the associated testing until I can get this fixed. llvm-svn: 245481
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-194-6/+17
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-08-192-86/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reintroduce r245442. Remove an overly conservative assertion introduced in r245442. We could replace the assertion to use `shareSameRegisterFile` instead, but in that point in `insertPHI` we already lost the original Def subreg to check against. So drop the assertion completely. Original commit message: - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 245479
* [SPARC] Enable writing to floating-point-state register.Douglas Katzman2015-08-193-0/+27
| | | | llvm-svn: 245475
* [AArch64] Improve short-form diags on long-form Match_InvalidOperand.Ahmed Bougacha2015-08-191-10/+18
| | | | | | | | | Since r244955, we try to use the short-form ErrorInfo when both tries failed, and the long-form match failed on a suffix operand. However, this means we sometimes mix ErrorInfo and MatchResult (one manifestation of this being PR24498). Instead, restore both. llvm-svn: 245469
* [SCEV] Fix GCC 4.8.0 ICE in lambda functionHal Finkel2015-08-191-7/+3
| | | | | | | | | Rewrite some code to not use a lambda function. The non-lambda code is just about as clean as the original, and not any longer. The lambda function causes an internal compiler error in GCC 4.8.0, and it is not worth breaking support for that compiler over this. NFC. llvm-svn: 245466
* [LAA] Comment how memchecks are codegenedAdam Nemet2015-08-191-0/+2
| | | | llvm-svn: 245465
* Revert "[AArch64] Simplify/refactor code to ease code review. NFC."Renato Golin2015-08-191-32/+18
| | | | | | | This reverts commit r245443, as it broke AArch64 test-suite tramp3d with an assert "Reg && "Null register has no regunits". llvm-svn: 245455
* x32. Fixes a bug in x32 exception handling.Derek Schuff2015-08-191-1/+1
| | | | | | | | | | | | This patch updates the X86 lowering so that the Exception Pointer and Selector are 64-bit wide only if Subtarget.isTarget64BitLP64. Patch by João Porto Reviewers: dschuff, rnk Differential Revision: http://reviews.llvm.org/D12111 llvm-svn: 245454
* x32. Fixes jmp %reg in x32JF Bastien2015-08-191-0/+21
| | | | | | | | | | | | | | x32 has 32-bit pointers; x86-64 can't jmp %r32. This patch addresses this issue by explicitly zero-extending brind's target to 64-bits. Author: jpp Reviewers: jfb, dschuff, pavel.v.chupin Subscribers: llvm-commits Differential revision: http://reviews.llvm.org/D12112 llvm-svn: 245452
* [Sparc] Rename LoadASR and StoreASR from r245360 to *ASI, as was intended.James Y Knight2015-08-191-10/+10
| | | | llvm-svn: 245450
* Revert "[PeepholeOptimizer] Look through PHIs to find additional register ↵Bruno Cardoso Lopes2015-08-192-290/+86
| | | | | | | | | sources" Revert r245442 while investigating a fix. An assertion hit in http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/11380 llvm-svn: 245446
* [SPARC] Fix BooleanContents, so that select of a trunc doesn'tJames Y Knight2015-08-191-0/+8
| | | | | | | | eliminate the trunc. Differential Revision: http://reviews.llvm.org/D10442 llvm-svn: 245444
* [AArch64] Simplify/refactor code to ease code review. NFC.Chad Rosier2015-08-191-18/+32
| | | | llvm-svn: 245443
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-08-192-86/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reapply r243486. - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 245442
* [ARM] Add instruction selection patterns for vmin/vmaxSilviu Baranga2015-08-192-6/+24
| | | | | | | | | | | | | | | | Summary: The mid-end was generating vector smin/smax/umin/umax nodes, but we were using vbsl to generatate the code. This adds the vmin/vmax patterns and a test to check that we are now generating vmin/vmax instructions. Reviewers: rengolin, jmolloy Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D12105 llvm-svn: 245439
* Map %fprs to %asr6 in the Sparc assembler parser.Joerg Sonnenberger2015-08-191-0/+7
| | | | llvm-svn: 245437
* Emit <regmask R1 R2 R3 ...> instead of just <regmask> in IR dumps.Daniel Sanders2015-08-191-2/+25
| | | | | | | | | | Reviewers: qcolombet Subscribers: kparzysz, qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11644 llvm-svn: 245433
* Revert "[X86] Widen the 'AND' mask if doing so shrinks the encoding size"Tobias Grosser2015-08-191-61/+2
| | | | | | | This reverts commit 245169 which miscompiles MultiSource/Applications/siod from LNT. llvm-svn: 245432
* [X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when ↵Michael Kuperstein2015-08-192-0/+13
| | | | | | | | | | | | | optimizing for minsize There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
* [TLI] Refactor "is integer division cheap" queries.Michael Kuperstein2015-08-195-18/+7
| | | | | | | | | | | | | This removes the isPow2SDivCheap() query, as it is not currently used in any meaningful way. isIntDivCheap() no longer relies on a state variable (as all in-tree target set it to false), but the interface allows querying based on the type optimization level. NFC. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245430
* More clean up, still NFC. Remove dead variables now that the casts are gone.Nick Lewycky2015-08-191-5/+4
| | | | llvm-svn: 245420
* Clean up this file a little. Remove dead casts, casting Values to Values. ↵Nick Lewycky2015-08-191-8/+8
| | | | | | Adjust some comments for typos and whitespace. NFC. llvm-svn: 245419
* Exposed findDefsUsedOutsideOfLoop as a loop utility functionAshutosh Nema2015-08-192-19/+20
| | | | | | | | | Exposed findDefsUsedOutsideOfLoop as a loop utility function by moving it from LoopDistribute to LoopUtils. Reviewed By: anemet llvm-svn: 245416
* [LPM] Teach the legacy pass manager to support *using* an analysisChandler Carruth2015-08-191-16/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | without *requiring* it. This allows a pass indicate that it will use an analysis if available (through getAnalysisIfAvailable). When the pass manager knows this, it will refrain from deleting that analysis if it can. Naturally, it will still get invalidated at the correct time. These passes are not considered when scheduling the pass pipeline, so typically they will require manual scheduling, but this may also allow passes with getAnalysisIfAvailable to find the analysis more often if nothing after them requires that analysis and it wasn't invalidated. I don't have a particular use case with the current passes, but with my new structure for alias analyses, this will be very useful. We want to allow people to customize the set of AAs available by scheduling additional passes. These's aren't ever *required* for obvious reasons. So we need some way to mark in the legacy pass manager that they will still be used if available. This is essentially how analysis groups already work. But this makes the feature generally available and more explicit. It should allow the AA change to not impact how people trigger a custom alias analysis being available at a certain point in compilation. Differential Revision: http://reviews.llvm.org/D12114 llvm-svn: 245409
* Fix how DependenceAnalysis calls delinearizationHal Finkel2015-08-191-17/+34
| | | | | | | | | | Fix how DependenceAnalysis calls delinearization, mirroring what is done in Delinearization.cpp (mostly by making sure to call getSCEVAtScope before delinearizing, and by removing the unnecessary 'Pairs == 1' check). Patch by Vaivaswatha Nagaraj! llvm-svn: 245408
* Revert "Fix PR24469 resulting from r245025 and re-enable dead store ↵Eric Christopher2015-08-191-231/+51
| | | | | | | | | | elimination across basicblocks." This is causing bootstrap problems, e.g.: http://bb.pgr.jp/builders/clang-3stage-i686-linux/builds/2960 This reverts r245195. llvm-svn: 245402
* Make ScalarEvolution::isKnownPredicate a little smarterHal Finkel2015-08-191-1/+38
| | | | | | | | | | | | | | | | | | | | | | Here we make ScalarEvolution::isKnownPredicate, indirectly, a little smarter. Given some relational comparison operator OP, and two AddRec SCEVs, {I,+,S} OP {J,+,T}, we can reduce this to the comparison I OP J when S == T, both AddRecs are for the same loop, and both are known not to wrap. As it turns out, because of the way that backedge-guard expressions can be leveraged when computing known predicates, this allows indvars to simplify the if-statement comparison in this loop: void foo (int *a, int *b, int n) { for (int i = 0; i < n; ++i) { if (i > n) a[i] = b[i] + 1; } } which, somewhat surprisingly, we were not previously optimizing away. llvm-svn: 245400
* MIR Serialization: Serialize MMI's variable debug information.Alex Lorenz2015-08-194-2/+111
| | | | llvm-svn: 245396
* [BasicAA] Revert r221876 because it can produce incorrect aliasingQuentin Colombet2015-08-191-51/+4
| | | | | | information: see PR24468. llvm-svn: 245394
* Fix backward operands in call to isTruncateFree() and improve comments.Steve King2015-08-181-2/+2
| | | | llvm-svn: 245385
* MIR Parser: Return true on error when parsing standalone registers.Alex Lorenz2015-08-181-2/+2
| | | | llvm-svn: 245384
* MIR Serialization: Serialize the operand's bit mask target flags.Alex Lorenz2015-08-184-9/+123
| | | | | | | | | This commit adds support for bit mask target flag serialization to the MIR printer and the MIR parser. It also adds support for the machine operand's target flag serialization to the AArch64 target. Reviewers: Duncan P. N. Exon Smith llvm-svn: 245383
* use TLI.allowsMemoryAccess() to check if memory accesses are fast; NFCISanjay Patel2015-08-181-6/+11
| | | | | | | | | This consolidates use of isUnalignedMem32Slow() in one place. There is a slight change in logic although I'm not sure that it would ever come up in the real world: we were assuming that an alignment of the type size is always fast; now, we actually check the data layout to confirm that. llvm-svn: 245382
* Fix three typos in comments; "easilly" -> "easily".Nick Lewycky2015-08-182-2/+2
| | | | llvm-svn: 245379
* Support: Clean up TSan annotations.Peter Collingbourne2015-08-183-20/+2
| | | | | | | | | | | Remove support for Valgrind-based TSan, which hasn't been maintained for a few years. We now use the TSan annotations only if LLVM is compiled with -fsanitize=thread. We no longer need the weak function definitions as we are guaranteed that our program is linked directly with the TSan runtime. Differential Revision: http://reviews.llvm.org/D12121 llvm-svn: 245374
* MIR Serialization: Serialize the frame information's stack protector index.Alex Lorenz2015-08-184-2/+48
| | | | llvm-svn: 245372
* MIR Parser: Extract the code that parses stack object references into a newAlex Lorenz2015-08-181-2/+11
| | | | | | | | | | method. This commit extracts the code that parses the stack object references into a new method named 'parseStackFrameIndex', so that it can be reused when parsing standalone stack object references. llvm-svn: 245370
* [InstSimplify] Remove unused variableDavid Majnemer2015-08-181-6/+2
| | | | | | No functionality change is intended. llvm-svn: 245369
* [InstSimplify] Don't assume getAggregateElement will succeedDavid Majnemer2015-08-182-9/+4
| | | | | | | It isn't always possible to get a value from getAggregateElement. This fixes PR24488. llvm-svn: 245365
* [VectorUtils] Replace 'llvm::' qualification with 'using llvm'David Majnemer2015-08-181-18/+15
| | | | | | | No funcitonal change is intended, this just makes the file look more like the rest of LLVM. llvm-svn: 245364
* Load/store instructions for floating points with address space require SparcV9.Joerg Sonnenberger2015-08-181-19/+39
| | | | | | | | To properly handle this, define the *a instructions as separate instruction classes by refactoring the LoadA and StoreA multiclasses. Move the instruction tests into the sparcv9 file to test the difference. llvm-svn: 245360
* DAGCombiner: Improve DAGCombiner select normalizationMatthias Braun2015-08-181-20/+30
| | | | | | | | | | | | | | | | The current code normalizes select(C0, x, select(C1, x, y)) towards select(C0|C1, x, y) if the targets prefers that form. This patch adds an additional rule that if the select(C1, x, y) part already exists in the function then we want to normalize into the other direction because the effects of reusing the existing value are bigger than transforming into the target preferred form. This addresses regressions following r238793, see also: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150727/290272.html Differential Revision: http://reviews.llvm.org/D11616 llvm-svn: 245350
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