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* AMDGPU: Fix unreachable when counting register usage of SGPR96Matt Arsenault2019-04-151-0/+3
| | | | llvm-svn: 358447
* AMDGPU: Fix printed format of SReg_96Matt Arsenault2019-04-151-0/+3
| | | | | | | These are artificial, so I think this should only come up with inline asm comments. llvm-svn: 358446
* [X86] Block i32/i64 for 'k' and 'Yk' in getRegForInlineAsmConstraint without ↵Craig Topper2019-04-151-24/+21
| | | | | | | | avx512bw. 32 and 64 bit k-registers require avx512bw. If we don't block this properly, it leads to a crash. llvm-svn: 358436
* [LoopPred] Stop passing around builders [NFC]Philip Reames2019-04-151-31/+49
| | | | | | | | | | | | This is a preparatory patch for D60093. This patch itself is NFC, but while preparing this I noticed and committed a small hoisting change in rL358419. The basic structure of the new scheme is that we pass around the guard ("the using instruction"), and select an optimal insert point by examining operands at each construction point. This seems conceptually a bit cleaner to start with as it isolates the knowledge about insertion safety at the actual insertion point. Note that the non-hoisting path is not actually used at the moment. That's not exercised until D60093 is rebased on this one. Differential Revision: https://reviews.llvm.org/D60718 llvm-svn: 358434
* [DEBUGINFO] Prevent Instcombine from dropping debuginfo when removing zextsWolfgang Pieb2019-04-151-5/+4
| | | | | | | | | | | Zexts can be treated like no-op casts when it comes to assessing whether their removal affects debug info. Reviewer: aprantl Differential Revision: https://reviews.llvm.org/D60641 llvm-svn: 358431
* Add explicit dependency to MCDwarf.h in ARC backend.Pete Couperus2019-04-151-0/+1
| | | | llvm-svn: 358430
* [CommandLineParser] Add DefaultOption flagDon Hinton2019-04-151-5/+45
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add DefaultOption flag to CommandLineParser which provides a default option or alias, but allows users to override it for some other purpose as needed. Also, add `-h` as a default alias to `-help`, which can be seamlessly overridden by applications like llvm-objdump and llvm-readobj which use `-h` as an alias for other options. (relanding after revert, r358414) Added DefaultOptions.clear() to reset(). Reviewers: alexfh, klimek Reviewed By: klimek Subscribers: kristina, MaskRay, mehdi_amini, inglorion, dexonsmith, hiraditya, llvm-commits, jhenderson, arphaman, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D59746 llvm-svn: 358428
* [X86] Restore the pavg intrinsics.Craig Topper2019-04-152-21/+21
| | | | | | | | | | | | | | | The pattern we replaced these with may be too hard to match as demonstrated by PR41496 and PR41316. This patch restores the intrinsics and then we can start focusing on the optimizing the intrinsics. I've mostly reverted the original patch that removed them. Though I modified the avx512 intrinsics to not have masking built in. Differential Revision: https://reviews.llvm.org/D60674 llvm-svn: 358427
* Add slbfee instruction.Sean Fertile2019-04-154-0/+7
| | | | llvm-svn: 358425
* [PGO] Profile guided code size optimization.Hiroshi Yamauchi2019-04-1512-39/+180
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Enable some of the existing size optimizations for cold code under PGO. A ~5% code size saving in big internal app under PGO. The way it gets BFI/PSI is discussed in the RFC thread http://lists.llvm.org/pipermail/llvm-dev/2019-March/130894.html Note it doesn't currently touch loop passes. Reviewers: davidxl, eraman Reviewed By: eraman Subscribers: mgorny, javed.absar, smeenai, mehdi_amini, eraman, zzheng, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59514 llvm-svn: 358422
* llvm-undname: Fix nullptr deref on invalid conversion operator names in ↵Nico Weber2019-04-151-1/+10
| | | | | | | | | | | | | | | | | template args A ConversionOperatorIdentifierNode has a TargetType which is read when printing it, but if the ConversionOperatorIdentifierNode appears in a template argument there's nothing that can provide the TargetType. Normally the COIN is a symbol (leaf) name and takes its TargetType from the symbol's type, but in a template argument context the COIN can only be either a non-leaf name piece or a type, and must hence be invalid. Similar to the COIN check in demangleDeclarator(). Found by oss-fuzz. llvm-svn: 358421
* [LoopPred] Hoist and of predicated checks where legalPhilip Reames2019-04-151-2/+16
| | | | | | If we have multiple range checks which can be predicated, hoist the and of the results outside the loop. This minorly cleans up the resulting IR, but the main motivation is as a building block for D60093. llvm-svn: 358419
* Revert r358337: "[CommandLineParser] Add DefaultOption flag"Ilya Biryukov2019-04-151-43/+5
| | | | | | | The change causes test failures under asan. Reverting to unbreak our integrate. llvm-svn: 358414
* [InstCombine] canonicalize fdiv after fmul if reassociation is allowedSanjay Patel2019-04-151-0/+8
| | | | | | | | (X / Y) * Z --> (X * Z) / Y This can allow other optimizations/reassociations as shown in the test diffs. llvm-svn: 358404
* DAG: propagate ConsecutiveRegs flags to returns too.Tim Northover2019-04-151-0/+18
| | | | | | | | | | Arguments already have a flag to inform backends when they have been split up. The AArch64 arm64_32 ABI makes use of these on return types too, so that code emitted for armv7k can be ABI-compliant. There should be no CodeGen changes yet, just making more information available. llvm-svn: 358399
* DAG: propagate whether an arg is a pointer for CallingConv decisions.Tim Northover2019-04-152-5/+30
| | | | | | | | | | | | | | | The arm64_32 ABI specifies that pointers (despite being 32-bits) should be zero-extended to 64-bits when passed in registers for efficiency reasons. This means that the SelectionDAG needs to be able to tell the backend that an argument was originally a pointer, which is implmented here. Additionally, some memory intrinsics need to be declared as taking an i8* instead of an iPTR. There should be no CodeGen change yet, but it will be triggered when AArch64 backend support for ILP32 is added. llvm-svn: 358398
* [AMDGPU] Fixed incorrect test in vcnd/vcmp optimizationTim Renouf2019-04-151-1/+1
| | | | | | | | | | | | This fixes a test I introduced in change D59191 (that added src0 and src1 modifiers to the v_cndmask instruction for disassembly purposes). Spotted by David Binderman in bug 41488. Differential Revision: https://reviews.llvm.org/D60652 Change-Id: I6ac95e66cd84e812ed3359ad57bcd0e13198ba0c llvm-svn: 358392
* FileCheck [1/12]: Move variable table in new objectThomas Preud'homme2019-04-151-85/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch is part of a patch series to add support for FileCheck numeric expressions. This specific patch adds a new class to hold pattern matching global state. The table holding the values of FileCheck variable constitutes some sort of global state for the matching phase, yet is passed as parameters of all functions using it. This commit create a new FileCheckPatternContext class pointed at from FileCheckPattern. While it increases the line count, it separates local data from global state. Later commits build on that to add numeric expression global state to that class. Copyright: - Linaro (changes up to diff 183612 of revision D55940) - GraphCore (changes in later versions of revision D55940 and in new revision created off D55940) Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield Tags: #llvm Differential Revision: https://reviews.llvm.org/D60381 llvm-svn: 358390
* [DWARF] Fix DWARFVerifier::DieRangeInfo::containsFangrui Song2019-04-151-19/+18
| | | | | | | | | It didn't handle empty LHS correctly. If two ranges of LHS were contiguous and jointly contained one range of RHS, it could also be incorrect. DWARFAddressRange::contains can be removed and its tests can be merged into DWARFVerifier::DieRangeInfo::contains llvm-svn: 358387
* [Transforms][ASan] Move findAllocaForValue() to Utils/Local.cpp. NFCAlexander Potapenko2019-04-152-39/+41
| | | | | | | | | | | | | | | | Summary: Factor out findAllocaForValue() from ASan so that we can use it in MSan to handle lifetime intrinsics. Reviewers: eugenis, pcc Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60615 llvm-svn: 358380
* [NewPM] Add Option handling for SimplifyCFGSerguei Katkov2019-04-152-1/+39
| | | | | | | | | | | This patch enables passing options to SimplifyCFGPass via the passes pipeline. Reviewers: chandlerc, fedor.sergeev, leonardchan, philip.pfaffe Reviewed By: fedor.sergeev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D60675 llvm-svn: 358379
* [DWARF] Fix DWARFVerifier::DieRangeInfo::intersectsFangrui Song2019-04-151-16/+9
| | | | | | It was incorrect if RHS had more than 1 ranges and one of the ranges interacted with *this llvm-svn: 358376
* [DWARF] Make DWARFDebugLine::ParsingState::RowNumber a local variableFangrui Song2019-04-151-2/+2
| | | | llvm-svn: 358374
* [SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarryBjorn Pettersson2019-04-151-58/+21
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Use KnownBits::computeForAddSub/computeForAddCarry in SelectionDAG::computeKnownBits when doing value tracking for addition/subtraction. This should improve the precision of the known bits, as we only used to make a simple estimate of known zeroes. The KnownBits support functions are also able to deduce bits that are known to be one in the result. Reviewers: spatel, RKSimon, nikic, lebedev.ri Reviewed By: nikic Subscribers: nikic, javed.absar, lebedev.ri, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60460 llvm-svn: 358372
* [Sparc] Fix typo. NFC.Jim Lin2019-04-151-2/+2
| | | | llvm-svn: 358370
* [GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with ↵Amara Emerson2019-04-157-34/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constants only. Other opcodes shouldn't be CSE'd until we can be sure debug info quality won't be degraded. This change also improves the IRTranslator so that in most places, but not all, it creates constants using the MIRBuilder directly instead of first creating a new destination vreg and then creating a constant. By doing this, the buildConstant() method can just return the vreg of an existing G_CONSTANT instead of having to create a COPY from it. I measured a 0.2% improvement in compile time and a 0.9% improvement in code size at -O0 ARM64. Compile time: Program base cse diff test-suite...ark/tramp3d-v4/tramp3d-v4.test 9.04 9.12 0.8% test-suite...Mark/mafft/pairlocalalign.test 2.68 2.66 -0.7% test-suite...-typeset/consumer-typeset.test 5.53 5.51 -0.4% test-suite :: CTMark/lencod/lencod.test 5.30 5.28 -0.3% test-suite :: CTMark/Bullet/bullet.test 25.82 25.76 -0.2% test-suite...:: CTMark/ClamAV/clamscan.test 6.92 6.90 -0.2% test-suite...TMark/7zip/7zip-benchmark.test 34.24 34.17 -0.2% test-suite :: CTMark/SPASS/SPASS.test 6.25 6.24 -0.1% test-suite...:: CTMark/sqlite3/sqlite3.test 1.66 1.66 -0.1% test-suite :: CTMark/kimwitu++/kc.test 13.61 13.60 -0.0% Geomean difference -0.2% Code size: Program base cse diff test-suite...-typeset/consumer-typeset.test 1315632 1266480 -3.7% test-suite...:: CTMark/ClamAV/clamscan.test 1313892 1297508 -1.2% test-suite :: CTMark/lencod/lencod.test 1439504 1423112 -1.1% test-suite...TMark/7zip/7zip-benchmark.test 2936980 2904172 -1.1% test-suite :: CTMark/Bullet/bullet.test 3478276 3445460 -0.9% test-suite...ark/tramp3d-v4/tramp3d-v4.test 8082868 8033492 -0.6% test-suite :: CTMark/kimwitu++/kc.test 3870380 3853972 -0.4% test-suite :: CTMark/SPASS/SPASS.test 1434904 1434896 -0.0% test-suite...Mark/mafft/pairlocalalign.test 764528 764528 0.0% test-suite...:: CTMark/sqlite3/sqlite3.test 782092 782092 0.0% Geomean difference -0.9% Differential Revision: https://reviews.llvm.org/D60580 llvm-svn: 358369
* [GlobalISel] Introduce a CSEConfigBase class to allow targets to define ↵Amara Emerson2019-04-159-8/+54
| | | | | | | | | | | | | | their own CSE configs. Because CodeGen can't depend on GlobalISel, we need a way to encapsulate the CSE configs that can be passed between TargetPassConfig and the targets' custom pass configs. This CSEConfigBase allows targets to create custom CSE configs which is then used by the GISel passes for the CSEMIRBuilder. This support will be used in a follow up commit to allow constant-only CSE for -O0 compiles in D60580. llvm-svn: 358368
* llvm-undname: Fix oss-fuzz-foudn crash-on-invalid with incomplete special ↵Nico Weber2019-04-141-0/+4
| | | | | | table nodes llvm-svn: 358367
* llvm-undname: Fix another crash-on-invalid found by oss-fuzzNico Weber2019-04-141-1/+4
| | | | llvm-svn: 358363
* [X86] Redefine KUNPCK instructions to take a narrower source register class ↵Craig Topper2019-04-141-11/+9
| | | | | | | | | than destination register class. Remove copies from the isel output pattern. There's no reason for the inputs to be the destination register class. This just forces an unnecessary copy in the output patterns. llvm-svn: 358362
* [X86] Put the locked mi8 instrutions above the locked mi/mi32 so they will ↵Craig Topper2019-04-141-24/+26
| | | | | | | | | be prefered. We want 64mi8 to be prefered over 64mi32. The order for 16mi/32mi doesn't really matter. llvm-svn: 358361
* [X86] Change IMUL with immediate instruction order to ri8 instructions come ↵Craig Topper2019-04-141-31/+34
| | | | | | | | | | before ri/ri32 instructions. This will ensure IMUL64ri8 is tried before IMUL64ri32. For IMUL32 and IMUL16 the order doesn't really matter because only the ri8 versions use a predicate. That automatically gives them priority. llvm-svn: 358360
* [X86] Move VPTESTM matching from the isel table to custom code in ↵Craig Topper2019-04-142-251/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | X86ISelDAGToDAG. We had many tablegen patterns for these instructions. And due to the commutability of the patterns, tablegen expands them to even more patterns. All together VPTESTMD patterns accounted for more the 50K of the 610K isel table. This had gotten bad when we stopped canonicalizing AND to vXi64. This required a pattern for every combination of bitcast input type. This change moves the matching to custom code where it is easier to look through the bitcasts without being concerned with the specific types. The test changes are because we are now stricter with one use checks as its required to make load folding legal. We now require the AND and any BITCAST to only have a single use. This prevents forming VPTESTM and a VPAND with the same inputs. We now support broadcast loads for 128/256 patterns without VLX. We'll widen to 512-bit like and still fold the broadcast since the amount of memory read doesn't change. There are a few tests that got slightly longer because are now prefering load + VPTESTM over XOR+VPCMPEQ for (seteq (load), allzeros). Previously we were able to share the XOR with multiple VPTESTM instructions. llvm-svn: 358359
* [X86] Don't form masked vpcmp/vcmp/vptestm operations if the setcc node has ↵Craig Topper2019-04-141-148/+256
| | | | | | | | | | | | | | more than one use. We're better of emitting a single compare + kand rather than a compare for the other use and a masked compare. I'm looking into using custom instruction selection for VPTESTM to reduce the ridiculous number of permutations of patterns in the isel table. Putting a one use check on all masked compare folding makes load fold matching in the custom code easier. llvm-svn: 358358
* [Mem2Reg] Delete unused PointerAllocaValuesFangrui Song2019-04-141-5/+0
| | | | | | It is unused after AliasSetTracker support was removed. llvm-svn: 358352
* [Mem2Reg] Simplify and micro optimizeFangrui Song2019-04-141-13/+9
| | | | | | | | * Rearrange continu/break * BBNumbers.lookup(A) -> BBNumbers.find(A)->second BBNumbers has been computed, thus we can assume the value exists in the predicate. llvm-svn: 358351
* [Mem2Reg] Don't call LBI.deleteValue on AllocInst/DbgVariableIntrinsicFangrui Song2019-04-141-6/+1
| | | | | | Only StoreInst/LoadInst are assigned numbers. Other types of instructions are not in LBI. llvm-svn: 358350
* [Mem2Reg] Simplify rewriteSingleStoreAllocaFangrui Song2019-04-141-5/+2
| | | | llvm-svn: 358349
* [ConstantRange] Delete unused getSetSizeFangrui Song2019-04-141-8/+0
| | | | | | getSetSize returns an APInt that is 1 bit wider. The APInt is typically 65-bit and requires memory allocation. isSizeStrictlySmallerThan and isSizeLargerThan are preferred. The last use of this helper method was removed by rL302385. llvm-svn: 358347
* [X86] Remove some unused tablegen multiclasses. NFCCraig Topper2019-04-141-27/+0
| | | | llvm-svn: 358345
* [X86] Use PC-relative mode for the kernel code modelBill Wendling2019-04-131-9/+14
| | | | | | | | | | | | | | | | | | Summary: The Linux kernel uses PC-relative mode, so allow that when the code model is "kernel". Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, kees, nickdesaulniers Tags: #llvm Differential Revision: https://reviews.llvm.org/D60643 llvm-svn: 358343
* [ConstantRange] Disallow NUW | NSW in makeGuaranteedNoWrapRegion()Nikita Popov2019-04-131-18/+14
| | | | | | | | | | | | | | | As motivated in D60598, this drops support for specifying both NUW and NSW in makeGuaranteedNoWrapRegion(). None of the users of this function currently make use of this. When both NUW and NSW are specified, the exact nowrap region has two disjoint parts and makeGNWR() returns one of them. This result doesn't seem to be useful for anything, but makes the semantics of the function fuzzier. Differential Revision: https://reviews.llvm.org/D60632 llvm-svn: 358340
* [InstCombine] Remove redundant/bogus mul_with_overflow combinesNikita Popov2019-04-131-8/+0
| | | | | | | | | | | | As pointed out in D60518 folding mulo(%x, undef) to {undef, undef} isn't correct. As a correct version of this already exists in InstructionSimplify (https://github.com/llvm-mirror/llvm/blob/bd8056ef326e075cc500f3f0cfcd1193bc200594/lib/Analysis/InstructionSimplify.cpp#L4750-L4757) this is just dead code though. Drop it together with the mul(%x, 0) -> {0, false} fold that is also already handled by InstSimplify. Differential Revision: https://reviews.llvm.org/D60649 llvm-svn: 358339
* [X86] Use int64_t and isInt<N> instead of APInt operations in ↵Craig Topper2019-04-131-8/+6
| | | | | | | | | | foldLoadStoreIntoMemOperand. NFC We know all our values are limited to 64 bits here so we don't need an APInt. This should save some generated code checking between large and small size. llvm-svn: 358338
* [CommandLineParser] Add DefaultOption flagDon Hinton2019-04-131-5/+43
| | | | | | | | | | | | | | | | | | | | | | Summary: Add DefaultOption flag to CommandLineParser which provides a default option or alias, but allows users to override it for some other purpose as needed. Also, add `-h` as a default alias to `-help`, which can be seamlessly overridden by applications like llvm-objdump and llvm-readobj which use `-h` as an alias for other options. Reviewers: alexfh, klimek Reviewed By: klimek Subscribers: MaskRay, mehdi_amini, inglorion, dexonsmith, hiraditya, llvm-commits, jhenderson, arphaman, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D59746 llvm-svn: 358337
* [WebAssembly] Use Function::hasOptSize() (NFC)Heejin Ahn2019-04-131-2/+1
| | | | | | | | | | | | | | | | Summary: Use member function. Reviewers: aheejin Subscribers: sunfish, hiraditya, sbc100, jgravelle-google, dschuff, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60651 Patch by Hideto Ueno (uenoku) llvm-svn: 358336
* [Mem2Reg] Delete unused AllocaPointerValFangrui Song2019-04-131-4/+0
| | | | | | It is no longer used after the AliasSetTracker updating logic was removed. llvm-svn: 358334
* [InstCombine] Canonicalize (-X srem Y) to -(X srem Y).Chen Zheng2019-04-131-0/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D60647 llvm-svn: 358328
* [AArch64][GlobalISel] Enable copy elision in the pre-legalizer combine and ↵Amara Emerson2019-04-132-0/+3
| | | | | | | | | | | | | fix a crash. This enables the simple copy combine that already exists in the CombinerHelper. However, it exposed a bug in the GISelChangeObserver where it wouldn't clear a set of MIs to process, and so would end up causing a crash when deleted MIs were being added to the combiner worklist again. Differential Revision: https://reviews.llvm.org/D60579 llvm-svn: 358318
* [WebAssembly] Add DataCount section to object filesThomas Lively2019-04-123-0/+34
| | | | | | | | | | | | | | | | | | | Summary: This ensures that object files will continue to validate as WebAssembly modules in the presence of bulk memory operations. Engines that don't support bulk memory operations will not recognize the DataCount section and will report validation errors, but that's ok because object files aren't supposed to be run directly anyway. Reviewers: aheejin, dschuff, sbc100 Subscribers: jgravelle-google, hiraditya, sunfish, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60623 llvm-svn: 358315
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