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* Properly model the latency of register defs which are 1) function returns orEvan Cheng2010-10-232-16/+85
| | | | | | | | | | | 2) live-outs. Previously the post-RA schedulers completely ignore these dependencies since returns, branches, etc. are all scheduling barriers. This patch model the latencies between instructions being scheduled and the barriers. It also handle calls by marking their register uses. llvm-svn: 117193
* Latency between CPSR def and branch is zero.Evan Cheng2010-10-231-0/+6
| | | | llvm-svn: 117192
* Verify LiveIntervals against the CFG, ensuring that live-in values are live-outJakob Stoklund Olesen2010-10-231-1/+77
| | | | | | of all predecessors. llvm-svn: 117191
* Trailing whitespace.Jim Grosbach2010-10-221-5/+5
| | | | llvm-svn: 117188
* Nonvirtual dtor that was accessible enough to be bad.Andrew Trick2010-10-221-0/+2
| | | | llvm-svn: 117180
* fix memory-layout assumption which only holds on little-endian systemsGabor Greif2010-10-221-1/+1
| | | | llvm-svn: 117176
* This is a prototype of an experimental register allocationAndrew Trick2010-10-226-1/+801
| | | | | | | | | | | | | | | | framework. It's purpose is not to improve register allocation per se, but to make it easier to develop powerful live range splitting. I call it the basic allocator because it is as simple as a global allocator can be but provides the building blocks for sophisticated register allocation with live range splitting. A minimal implementation is provided that trivially spills whenever it runs out of registers. I'm checking in now to get high-level design and style feedback. I've only done minimal testing. The next step is implementing a "greedy" allocation algorithm that does some register reassignment and makes better splitting decisions. llvm-svn: 117174
* Add more verification of LiveIntervals.Jakob Stoklund Olesen2010-10-221-0/+29
| | | | llvm-svn: 117170
* Be more strict about detecting multi-use blocks for isolation.Jakob Stoklund Olesen2010-10-221-28/+29
| | | | | | | | | | | When a block has exactly two uses and the register is both live-in and live-out, don't isolate the block. We would be inserting two copies, so we haven't really made any progress. If the live-in and live-out values separate into disconnected components after splitting, we would be making progress. We can't detect that for now. llvm-svn: 117169
* ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.Jim Grosbach2010-10-222-72/+73
| | | | llvm-svn: 117165
* Unbreak build.Evan Cheng2010-10-222-10/+11
| | | | llvm-svn: 117155
* Teach instcombine to set the alignment arguments for NEON load/store intrinsics.Bob Wilson2010-10-221-0/+26
| | | | llvm-svn: 117154
* Transfer implicit ops when forming load multiple and return instructions.Evan Cheng2010-10-222-1/+2
| | | | llvm-svn: 117151
* Be more strict when detecting critical edges before loop splitting.Jakob Stoklund Olesen2010-10-221-19/+15
| | | | | | | | An exit block with a critical edge must only have predecessors in the loop, or just before the loop. This guarantees that the inserted copies in the loop predecessors dominate the exit block. llvm-svn: 117144
* Add print methodsJakob Stoklund Olesen2010-10-222-18/+32
| | | | llvm-svn: 117143
* Add correct NEON encodings for vqdmlal.Owen Anderson2010-10-221-4/+4
| | | | llvm-svn: 117134
* Add the encoding information for the rest of the ARM mode multiply instructions.Jim Grosbach2010-10-221-20/+41
| | | | llvm-svn: 117133
* Provide correct encodings for NEON vmlal.Owen Anderson2010-10-221-5/+5
| | | | llvm-svn: 117131
* Silence compiler warnings.Evan Cheng2010-10-221-1/+5
| | | | llvm-svn: 117128
* Provide correct NEON encodings for vmla.Owen Anderson2010-10-221-14/+15
| | | | llvm-svn: 117126
* More ARM multiply instuction binary encodings.Jim Grosbach2010-10-222-110/+121
| | | | llvm-svn: 117121
* Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by ↵Evan Cheng2010-10-222-12/+51
| | | | | | -arm-fastcc for now. llvm-svn: 117119
* Parameterize a bit of ARM encoding information, simplifying some instructionJim Grosbach2010-10-222-50/+29
| | | | | | definitions. llvm-svn: 117114
* Make some symbols static, move classes into anonymous namespaces.Benjamin Kramer2010-10-225-18/+19
| | | | llvm-svn: 117111
* More ARM multiply instruction encoding information.Jim Grosbach2010-10-222-34/+41
| | | | llvm-svn: 117108
* Making the e_machine configurable by the target backend in ELFObjectWriter.Wesley Peck2010-10-224-9/+16
| | | | llvm-svn: 117099
* Reverting r117031 to cleanup valgrind errors.Andrew Trick2010-10-223-14/+9
| | | | | | | It doesn't look like anything is wrong with the checkin, but the new test cases expose a mem bug in AsmParser. llvm-svn: 117087
* Add some basic ret instruction support to arm fast-isel.Eric Christopher2010-10-221-0/+66
| | | | llvm-svn: 117085
* Fixed handling of immediate operand sizes, whichSean Callanan2010-10-221-1/+1
| | | | | | | | | weren't properly reflecting the OperandSize attribute of the instruction leading to improper decoding of certain instructions with the 66H prefix. Also added a test case for this. llvm-svn: 117084
* Win32/Signals.inc: DontRemoveFileOnSignal(): Please acquire the CriticalSection.NAKAMURA Takumi2010-10-221-0/+2
| | | | | | It choked BugPoint on Mingw. llvm-svn: 117083
* ARM binary encoding for some of the multiply instructions.Jim Grosbach2010-10-211-26/+68
| | | | llvm-svn: 117080
* ARM binary encodings for MVN variants.Jim Grosbach2010-10-211-10/+27
| | | | llvm-svn: 117076
* Trailing whitespace.Jim Grosbach2010-10-211-25/+25
| | | | llvm-svn: 117073
* ARM Binary encoding information for BFC/BFI instructions.Jim Grosbach2010-10-213-6/+35
| | | | llvm-svn: 117072
* Add some more documentation.Dan Gohman2010-10-211-15/+21
| | | | llvm-svn: 117070
* These don't need to be virtual.Eric Christopher2010-10-211-13/+13
| | | | llvm-svn: 117068
* Fix Warnings.Michael J. Spencer2010-10-211-1/+1
| | | | llvm-svn: 117062
* X86: Base _fltused on the FunctionType of the called value instead of the ↵Michael J. Spencer2010-10-211-19/+20
| | | | | | | | potentially null "CalledFunction". Thanks Duncan! This is needed for indirect calls. llvm-svn: 117061
* Move the encoding logic for Q registers into getMachineOpValue().Owen Anderson2010-10-212-25/+36
| | | | llvm-svn: 117060
* Trailing whitespace.Mikhail Glushenkov2010-10-211-5/+5
| | | | llvm-svn: 117058
* ARM encodes Q registers as 2xregno (i.e. the number of the D register that ↵Owen Anderson2010-10-213-115/+45
| | | | | | | | | corresponds to the lower half of the Q register), rather than with just regno. This allows us to unify the encodings for a lot of different NEON instrucitons that differ only in whether they have Q or D register operands. llvm-svn: 117056
* Handle storing args to the stack for calls.Eric Christopher2010-10-211-4/+6
| | | | llvm-svn: 117055
* Adding initial AsmParser implementation for the MBlaze backend. It isWesley Peck2010-10-2118-454/+1419
| | | | | | | | | | | | | | | | | | | | | | | | mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. llvm-svn: 117054
* Explain what "constant" means here.Dan Gohman2010-10-211-1/+3
| | | | llvm-svn: 117053
* More load/store refactoring, call reg+offset simplification from withinEric Christopher2010-10-211-28/+36
| | | | | | | | the emitter to handle the addresses. Only simplify the offset if we need to - also fix bug where in addrmode 5 we weren't dividing the offset by 4, which showed up due to not always lowering. llvm-svn: 117051
* trailing whitespaceJim Grosbach2010-10-211-4/+4
| | | | llvm-svn: 117050
* Update comments.Dan Gohman2010-10-211-3/+23
| | | | llvm-svn: 117048
* Add correct NEON encodings for vhadd and vrhadd.Owen Anderson2010-10-211-6/+33
| | | | llvm-svn: 117047
* Don't include the destination interval in the union when computingJakob Stoklund Olesen2010-10-211-2/+4
| | | | | | Parent - union(Y, ...). Doh. llvm-svn: 117042
* Permit landing pad successor blocks when verifying basic blocks that end in anJakob Stoklund Olesen2010-10-211-5/+13
| | | | | | unconditional branch. llvm-svn: 117041
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