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* [ValueTracking] recognize variations of 'clamp' to improve codegen (PR31693)Sanjay Patel2017-01-201-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By enhancing value tracking, we allow an existing min/max canonicalization to kick in and improve codegen for several targets that have min/max instructions. Unfortunately, recognizing min/max in value tracking may cause us to hit a hack in InstCombiner::visitICmpInst() more often: http://lists.llvm.org/pipermail/llvm-dev/2017-January/109340.html ...but I'm hoping we can remove that soon. Correctness proofs based on Alive: Name: smaxmin Pre: C1 < C2 %cmp2 = icmp slt i8 %x, C2 %min = select i1 %cmp2, i8 %x, i8 C2 %cmp3 = icmp slt i8 %x, C1 %r = select i1 %cmp3, i8 C1, i8 %min => %cmp2 = icmp slt i8 %x, C2 %min = select i1 %cmp2, i8 %x, i8 C2 %cmp1 = icmp sgt i8 %min, C1 %r = select i1 %cmp1, i8 %min, i8 C1 Name: sminmax Pre: C1 > C2 %cmp2 = icmp sgt i8 %x, C2 %max = select i1 %cmp2, i8 %x, i8 C2 %cmp3 = icmp sgt i8 %x, C1 %r = select i1 %cmp3, i8 C1, i8 %max => %cmp2 = icmp sgt i8 %x, C2 %max = select i1 %cmp2, i8 %x, i8 C2 %cmp1 = icmp slt i8 %max, C1 %r = select i1 %cmp1, i8 %max, i8 C1 ---------------------------------------- Optimization: smaxmin Done: 1 Optimization is correct! ---------------------------------------- Optimization: sminmax Done: 1 Optimization is correct! Name: umaxmin Pre: C1 u< C2 %cmp2 = icmp ult i8 %x, C2 %min = select i1 %cmp2, i8 %x, i8 C2 %cmp3 = icmp ult i8 %x, C1 %r = select i1 %cmp3, i8 C1, i8 %min => %cmp2 = icmp ult i8 %x, C2 %min = select i1 %cmp2, i8 %x, i8 C2 %cmp1 = icmp ugt i8 %min, C1 %r = select i1 %cmp1, i8 %min, i8 C1 Name: uminmax Pre: C1 u> C2 %cmp2 = icmp ugt i8 %x, C2 %max = select i1 %cmp2, i8 %x, i8 C2 %cmp3 = icmp ugt i8 %x, C1 %r = select i1 %cmp3, i8 C1, i8 %max => %cmp2 = icmp ugt i8 %x, C2 %max = select i1 %cmp2, i8 %x, i8 C2 %cmp1 = icmp ult i8 %max, C1 %r = select i1 %cmp1, i8 %max, i8 C1 ---------------------------------------- Optimization: umaxmin Done: 1 Optimization is correct! ---------------------------------------- Optimization: uminmax Done: 1 Optimization is correct! llvm-svn: 292660
* [ThinLTO] Drop non-prevailing non-ODR weak to declarationsTeresa Johnson2017-01-202-11/+33
| | | | | | | | | | | | | | | Summary: Allow non-ODR weak/linkonce non-prevailing copies to be marked as available_externally in the index. Add support for dropping these to declarations in the backend. Reviewers: mehdi_amini, pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28806 llvm-svn: 292656
* LowerTypeTests: Implement importing of type identifiers.Peter Collingbourne2017-01-201-2/+84
| | | | | | | | | To import a type identifier we read the summary and create external references to the symbols defined when exporting. Differential Revision: https://reviews.llvm.org/D28546 llvm-svn: 292654
* [libFuzzer] add an assert to protect against LLVMFuzzerInitialize changing ↵Kostya Serebryany2017-01-204-0/+22
| | | | | | argv[0] llvm-svn: 292652
* AMDGPU/R600: Serialize vector trunc stores to private ASJan Vesely2017-01-205-3/+44
| | | | | | | | | | | Add DUMMY_CHAIN SDNode to denote stores of interest Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=28915 Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=30411 Differential Revision: https://reviews.llvm.org/D27964 llvm-svn: 292651
* NewGVN: Fix PR 31686 and PR 31698 by rewriting store leader handling.Daniel Berlin2017-01-201-36/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This rewrites store expression/leader handling. We no longer use the value operand as the leader, instead, we store it separately. We also now store the stored value as part of the expression, and compare it when comparing stores for equality. This enables us to get rid of a bunch of our previous hacks and machinations, as the existing machinery takes care of everything *except* updating the stored value on classes. The only time we have to update it is if the storecount goes to 0, and when we do, we destroy it. Since we no longer use the value operand as the leader, during elimination, we have to use the value operand. Doing this also fixes a bunch of store forwarding cases we were missing. Any value operand we use is guaranteed to either be updated by previous eliminations, or minimized by future ones. (IE the fact that we don't use the most dominating value operand when it's not a constant does not affect anything). Sadly, this change also exposes that we didn't pay attention to the output of the pr31594.ll test, as it also very clearly exposes the same store leader bug we are fixing here. (I added pr31682.ll anyway, but maybe we think that's too large to be useful) On the plus side, propagate-ir-flags.ll now passes due to the corrected store forwarding. This change was 3 stage'd on darwin and linux, with the full test-suite. Reviewers: davide Subscribers: llvm-commits llvm-svn: 292648
* LowerTypeTests: Compute SizeM1BitWidth in exportTypeId. NFCI.Peter Collingbourne2017-01-201-7/+6
| | | | | | This avoids needing to store it in a separate field in TypeIdLowering. llvm-svn: 292647
* [libFuzzer] experimental support for 'equivalance fuzzing'Kostya Serebryany2017-01-2010-7/+243
| | | | llvm-svn: 292646
* [WebAssembly] Don't create bitcast-wrappers for varargs.Dan Gohman2017-01-201-0/+5
| | | | | | | | | WebAssembly varargs functions use a significantly different ABI than non-varargs functions, and the current code in WebAssemblyFixFunctionBitcasts doesn't handle that difference. For now, just avoid creating wrapper functions in the presence of varargs. llvm-svn: 292645
* [ThinLTO] Fix lazy-loading of MDString instruction attachmentsMehdi Amini2017-01-203-6/+19
| | | | | | | | | CFI is using intrinsics that takes MDString as arguments, and this was broken during lazy-loading of metadata. Differential Revision: https://reviews.llvm.org/D28916 llvm-svn: 292641
* [DWARF] [ObjectYAML] Adding APIs for unittestingChris Bieneman2017-01-202-34/+85
| | | | | | | | | | | | Summary: This patch adds some new APIs to enable using the YAML DWARF representation in unit tests. The most basic new API is DWARFYAML::EmitDebugSections which converts a YAML string into a series of owned MemoryBuffer objects stored in a StringMap. The string map can then be used to construct a DWARFContext for parsing in place of an ObjectFile. Reviewers: dblaikie, clayborg Subscribers: mgorny, fhahn, jgosnell, aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D28828 llvm-svn: 292634
* Recommit "[InlineCost] Use TTI to check if GEP is free." #3Haicheng Wu2017-01-201-2/+18
| | | | | | | | | | | | This is the third attemp to recommit r292526. The original summary: Currently, a GEP is considered free only if its indices are all constant. TTI::getGEPCost() can give target-specific more accurate analysis. TTI is already used for the cost of many other instructions. llvm-svn: 292633
* ARM: tLDR_postidx should be marked mayLoadMatthias Braun2017-01-201-1/+1
| | | | | | This fixes -verify-machineinstrs complaints. llvm-svn: 292629
* [InstCombine][X86] Add MULDQ/MULUDQ undef handlingSimon Pilgrim2017-01-202-0/+21
| | | | llvm-svn: 292627
* AArch64LoadStoreOptimizer: Update kill flags when merging storesMatthias Braun2017-01-201-2/+23
| | | | | | | | | | | | | | Kill flags need to be updated correctly when moving stores up/down to form store pair instructions. Those invalid flags have been ignored before but as of r290014 they are recognized when using -mllvm -verify-machineinstrs. Also simplifies test/CodeGen/AArch64/ldst-opt-dbg-limit.mir, renames it to ldst-opt.mir test and adds a new tests for this change. Differential Revision: https://reviews.llvm.org/D28875 llvm-svn: 292625
* [mips] Fix debug information for __thread variablePetar Jovanovic2017-01-206-1/+37
| | | | | | | | | | | This patch fixes debug information for __thread variable on Mips using .dtprelword and .dtpreldword directives. Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D28770 llvm-svn: 292624
* [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-01-2011-200/+300
| | | | | | other minor fixes (NFC). llvm-svn: 292623
* [RegisterCoalescing] Recommit the patch "Remove partial redundent copy".Wei Mi2017-01-201-0/+171
| | | | | | | | | | | | | | | The recommit fixes a bug related with live interval update after the partial redundent copy is moved. The original patch is to solve the performance problem described in PR27827. Register coalescing sometimes cannot remove a copy because of interference. But if we can find a reverse copy in one of the predecessor block of the copy, the copy is partially redundent and we may remove the copy partially by moving it to the predecessor block without the reverse copy. Differential Revision: https://reviews.llvm.org/D28585 llvm-svn: 292621
* Revert "Recommit "[InlineCost] Use TTI to check if GEP is free." #2"Haicheng Wu2017-01-201-18/+2
| | | | | | This reverts commit r292616 because the test case still has problem. llvm-svn: 292618
* Recommit "[InlineCost] Use TTI to check if GEP is free." #2Haicheng Wu2017-01-201-2/+18
| | | | | | | | | | | | This is the second attemp to recommit r292526. The original summary: Currently, a GEP is considered free only if its indices are all constant. TTI::getGEPCost() can give target-specific more accurate analysis. TTI is already used for the cost of many other instructions. llvm-svn: 292616
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-01-201-1/+1
| | | | llvm-svn: 292613
* [CostModel][X86] Removed unused cost. NFCI.Simon Pilgrim2017-01-201-1/+0
| | | | | | SHL v8i32 is already handled in the SSE41 cost table llvm-svn: 292612
* [Thumb] Add support for tMUL in the compare instruction peephole optimizer.Sjoerd Meijer2017-01-201-169/+206
| | | | | | | | | | | | | | | | | We also want to optimise tests like this: return a*b == 0. The MULS instruction is flag setting, so we don't need the CMP instruction but can instead branch on the result of the MULS. The generated instructions sequence for this example was: MULS, MOVS, MOVS, CMP. The MOVS instruction load the boolean values resulting from the select instruction, but these MOVS instructions are flag setting and were thus preventing this optimisation. Now we first reorder and move the MULS to before the CMP and generate sequence MOVS, MOVS, MULS, CMP so that the optimisation could trigger. Reordering of the MULS and MOVS is safe to do because the subsequent MOVS instructions just set the CPSR register and don't use it, i.e. the CPSR is dead. Differential Revision: https://reviews.llvm.org/D27990 llvm-svn: 292608
* Pacify -Wreorder.Benjamin Kramer2017-01-201-1/+1
| | | | llvm-svn: 292599
* Add an assertion to PlaceholderQueue destructor, ensuring it has been flushedMehdi Amini2017-01-201-0/+3
| | | | llvm-svn: 292597
* [AMDGPU] Add subtarget features for SDWA/DPPSam Kolton2017-01-208-13/+50
| | | | | | | | | | Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28900 llvm-svn: 292596
* [InstCombine][SSE] Add DemandedElts support for PACKSS/PACKUS instructionsSimon Pilgrim2017-01-201-0/+54
| | | | | | | | Simplify a packss/packus truncation based on the elements of the mask that are actually demanded. Differential Revision: https://reviews.llvm.org/D28777 llvm-svn: 292591
* [PM] Port LoopSink to the new pass manager.Chandler Carruth2017-01-203-0/+39
| | | | | | | | | | | | | | | | | | | | | | Like several other loop passes (the vectorizer, etc) this pass doesn't really fit the model of a loop pass. The critical distinction is that it isn't intended to be pipelined together with other loop passes. I plan to add some documentation to the loop pass manager to make this more clear on that side. LoopSink is also different because it doesn't really need a lot of the infrastructure of our loop passes. For example, if there aren't loop invariant instructions causing a preheader to exist, there is no need to form a preheader. It also doesn't need LCSSA because this pass is only involved in sinking invariant instructions from a preheader into the loop, not reasoning about live-outs. This allows some nice simplifications to the pass in the new PM where we can directly walk the loops once without restructuring them. Differential Revision: https://reviews.llvm.org/D28921 llvm-svn: 292589
* [LoopSink] Trivial comment cleanup.Chandler Carruth2017-01-201-1/+2
| | | | llvm-svn: 292588
* [ARM] Use helpers for adding pred / CC operands. NFCDiana Picus2017-01-209-108/+128
| | | | | | | | | | | Hunt down some of the places where we use bare addReg(0) or addImm(AL).addReg(0) and replace with add(condCodeOp()) and add(predOps()). This should make it easier to understand what those operands represent (without having to look at the definition of the instruction that we're adding to). Differential Revision: https://reviews.llvm.org/D27984 llvm-svn: 292587
* NewGVN: Fix PR 31682, an overactive assert.Daniel Berlin2017-01-201-10/+16
| | | | | | | | Part of the assert has been left active for further debugging. The other part has been turned into a stat for tracking for the moment. llvm-svn: 292583
* Revert "LiveRegUnits: Add accumulateBackward() function"Matthias Braun2017-01-202-42/+32
| | | | | | | | This seems to be breaking some bots. This reverts commit r292543. llvm-svn: 292574
* Revert "Demangle: only demangle mangled symbols"Saleem Abdulrasool2017-01-201-10/+1
| | | | | | | | This reverts SVN r286795. This was incorrect the demangler is expected to be able to demangle types as well as functions. This makes the behaviour of itaniumDemangle similar to __cxa_demangle once more. llvm-svn: 292573
* Revert "Recommit "[InlineCost] Use TTI to check if GEP is free.""Haicheng Wu2017-01-201-18/+2
| | | | | | This reverts commit r292570. The test still has problem. llvm-svn: 292572
* Recommit "[InlineCost] Use TTI to check if GEP is free."Haicheng Wu2017-01-201-2/+18
| | | | | | | | | | | | This recommits r292526 which is reverted in r292529 after fixing the test case. The original summary: Currently, a GEP is considered free only if its indices are all constant. TTI::getGEPCost() can give target-specific more accurate analysis. TTI is already used for the cost of many other instructions. llvm-svn: 292570
* [LoopInfo] Add helper methods to compute two useful orderings of theChandler Carruth2017-01-201-18/+4
| | | | | | | | | | | | | | | | | | | | | | loops in a function. These are relatively confusing to talk about and compute correctly so it seems really good to write down their implementation in one place. I've replaced one place we needed this in the loop PM infrastructure and I have another place in a pending patch that wants it. We can't quite use this for the core loop PM walk because there we're sometimes working on a sub-forest. I'll add the expected unittests before committing this but wanted to make sure folks were happy with these names / comments. Credit goes to Richard Smith for the idea for naming the order where siblings are in reverse program order but the tree traversal remains preorder. Differential Revision: https://reviews.llvm.org/D28932 llvm-svn: 292569
* [AArch64][GlobalISel] Widen scalar int->fp conversions.Ahmed Bougacha2017-01-202-1/+29
| | | | | | | It's incorrect to ignore the higher bits of the integer source. Teach the legalizer how to widen it. llvm-svn: 292563
* [AMDGPU] Prevent spills before exec mask is restoredStanislav Mekhanoshin2017-01-203-2/+15
| | | | | | | | | | | | | Inline spiller can decide to move a spill as early as possible in the basic block. It will skip phis and label, but we also need to make sure it skips instructions in the basic block prologue which restore exec mask. Added isPositionLike callback in TargetInstrInfo to detect instructions which shall be skipped in addition to common phis, labels etc. Differential Revision: https://reviews.llvm.org/D27997 llvm-svn: 292554
* GlobalISel: Add a note about how we're being a bit loose with memory operandsJustin Bogner2017-01-201-0/+4
| | | | | | | The logic in r292461 is conservatively correct, but we should revisit this later. Add a TODO so we don't forget. llvm-svn: 292553
* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-12/+16
| | | | | | | | This completes r292321 by adding support for generic registers, e.g.: %2:_(s32) = G_ADD %0, %1 llvm-svn: 292550
* GlobalISel: Only set FailedISel on dropped dbg intrinsics when using fallbackJustin Bogner2017-01-201-2/+2
| | | | | | | | | It's easier to test the non-fallback path if we just drop these intrinsics for now, like we did before we added the fallback path. We'll obviously need to fix this properly, but the fixme for that is already here. llvm-svn: 292547
* [AliasAnalysis] Fences do not modify constant memory locationAnna Thomas2017-01-201-0/+8
| | | | | | | | | | | | | | | | | | | Summary: Fence instructions are currently marked as `ModRef` for all memory locations. We can improve this for constant memory locations (such as constant globals), since fence instructions cannot modify these locations. This helps us to forward constant loads across fences (added test case in GVN). There were no changes in behaviour for similar test cases in early-cse and licm. Reviewers: dberlin, sanjoy, reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28914 llvm-svn: 292546
* GlobalISel: Pass the MachineFunction in to reportSelectionError directlyJustin Bogner2017-01-201-6/+6
| | | | | | | | Rather than trying to find MF based on the possibly-null MI we've passed in here, just pass it in directly. It's already available at all callers anyway. llvm-svn: 292544
* LiveRegUnits: Add accumulateBackward() functionMatthias Braun2017-01-202-32/+42
| | | | | | | | | | | | | | | | This function can be used to accumulate the set of all read and modified register in a sequence of instructions. Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove the concept. - The AArch64A57LoadBalancing code is using a backwards analysis now which is irrespective of kill flags. This is the main motivation for this change. Differential Revision: http://reviews.llvm.org/D22082 llvm-svn: 292543
* CodeGen: Add/Factor out LiveRegUnits class; NFCIMatthias Braun2017-01-203-59/+106
| | | | | | | | | | | | | This is a set of register units intended to track register liveness, it is similar in spirit to LivePhysRegs. You can also think of this as the liveness tracking parts of the RegisterScavenger factored out into an own class. This was proposed in http://llvm.org/PR27609 Differential Revision: http://reviews.llvm.org/D21916 llvm-svn: 292542
* AArch64: fall back to DAG ISel for inline assembly.Tim Northover2017-01-191-0/+3
| | | | | | | We can't currently handle "calls" to inlineasm strings so it's better to let the DAG handle it than generate rubbish. llvm-svn: 292540
* Fix a few more build errors.Zachary Turner2017-01-191-0/+2
| | | | llvm-svn: 292538
* Fix incorrectly formed assert statement.Zachary Turner2017-01-191-1/+1
| | | | llvm-svn: 292537
* [pdb] Add HashTable data structure.Zachary Turner2017-01-194-170/+331
| | | | | | | | | | | | | | | | This was being parsed / serialized ad-hoc inside the code for a specific PDB stream. But this data structure is used in multiple ways / places within the PDB format. To be able to re-use it we need to raise this code out and make it more generic. In doing so, a number of bugs are fixed in the original implementation, and support is added for growing the hash table and deleting items from the hash table, which had either been omitted or incorrect implemented in the initial version. Differential Revision: https://reviews.llvm.org/D28715 llvm-svn: 292535
* clang-format SampleProfile.cpp (NFC)Dehao Chen2017-01-191-6/+4
| | | | llvm-svn: 292533
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