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* [MachO] Fix codegen of alias of alias.Evgeniy Stepanov2017-06-081-0/+4
| | | | | | Fixes PR33316. llvm-svn: 305012
* Do not early-inline recursive calls in sample profile loader.Dehao Chen2017-06-081-0/+7
| | | | | | | | | | | | | | Summary: Early-inlining of recursive call makes the code size bloat exponentially. We should not disable it. Reviewers: davidxl, dnovillo, iteratee Reviewed By: iteratee Subscribers: iteratee, llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D34017 llvm-svn: 305009
* fix formatting; NFCSanjay Patel2017-06-081-6/+6
| | | | llvm-svn: 305008
* [CGP] don't expand a memcmp with nobuiltin attributeSanjay Patel2017-06-081-6/+4
| | | | | | | | | | | | | | | | This matches the behavior used in the SDAG when expanding memcmp. For reference, we're intentionally treating the earlier fortified call transforms differently after: https://bugs.llvm.org/show_bug.cgi?id=23093 https://reviews.llvm.org/rL233776 One motivation for not transforming nobuiltin calls is that it can interfere with sanitizers: https://reviews.llvm.org/D19781 https://reviews.llvm.org/D19801 Differential Revision: https://reviews.llvm.org/D34043 llvm-svn: 305007
* AMDGPU: Work around build special casing .inc filesMatt Arsenault2017-06-083-1/+7
| | | | | | | It complains because it assumes these were autogenerated files in the source directory. llvm-svn: 305005
* AMDGPU: Use correct register names in inline assemblyMatt Arsenault2017-06-083-0/+410
| | | | | | Fixes using physical registers in inline asm from clang. llvm-svn: 305004
* [Hexagon] Speedup NumNodesBlocking calculation. NFCI.Nirav Dave2017-06-081-32/+25
| | | | llvm-svn: 305003
* [PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64Guozhi Wei2017-06-081-12/+26
| | | | | | | | | | In PPCBoolRetToInt bool value is changed to i32 type. On ppc64 it may introduce an extra zero extension for the return value. This patch changes the integer type to i64 to avoid the zero extension on ppc64. This patch fixed PR32442. Differential Revision: https://reviews.llvm.org/D31407 llvm-svn: 305001
* [AMDGPU] Force qsads instrs to use different dest register than source registersMark Searles2017-06-081-0/+5
| | | | | | | | The V_MQSAD_PK_U16_U8, V_QSAD_PK_U16_U8, and V_MQSAD_U32_U8 take more than 1 pass in hardware. For these three instructions, the destination registers must be different than all sources, so that the first pass does not overwrite sources for the following passes. Differential Revision: https://reviews.llvm.org/D33783 llvm-svn: 304998
* Changed a comparison operator for std::stable_sort to implement strict weak ↵Galina Kistanova2017-06-081-3/+3
| | | | | | | | | ordering. This is a temporarily fix which needs additional work, as it triggers a test3 failure. test3 is commented out till then. llvm-svn: 304993
* [Power9] Exploit vector integer extend instructionsZaara Syeda2017-06-081-0/+51
| | | | | | | | | | | | | | This patch adds build vector patterns to exploit the vector integer extend instructions: vextsb2w - Vector Extend Sign Byte To Word vextsb2d - Vector Extend Sign Byte To Doubleword vextsh2w - Vector Extend Sign Halfword To Word vextsh2d - Vector Extend Sign Halfword To Doubleword vextsw2d - Vector Extend Sign Word To Doubleword Differential Revision: https://reviews.llvm.org/D33510 llvm-svn: 304992
* [LazyValueInfo] Make LVILatticeVal intersect method take arguments by ↵Craig Topper2017-06-081-1/+1
| | | | | | reference so we don't copy ConstantRanges unless we need to. llvm-svn: 304990
* [CGP / PowerPC] avoid multi-block overhead for simple memcmp expansionSanjay Patel2017-06-081-21/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test diff for PowerPC shows we can better optimize if this case is one block. For x86, there's would be a substantial difference if CGP expansion was enabled because branches are assumed cheap and SDAG can't optimize across blocks. Instead of this: _cmp_eq8: movq (%rdi), %rax cmpq (%rsi), %rax je LBB23_1 ## BB#2: ## %res_block movl $1, %ecx jmp LBB23_3 LBB23_1: xorl %ecx, %ecx LBB23_3: ## %endblock xorl %eax, %eax testl %ecx, %ecx sete %al retq We get this: cmp_eq8: movq (%rdi), %rcx xorl %eax, %eax cmpq (%rsi), %rcx sete %al retq And that matches the optimal codegen that we get from the current expansion in SelectionDAGBuilder::visitMemCmpCall(). If this looks right, then I just need to confirm that vector-sized expansion will work from here, and we can enable CGP memcmp() expansion for x86. Ie, we'll bypass the power-of-2 special cases currently optimized in SDAG because we can lower the IR produced here optimally. Differential Revision: https://reviews.llvm.org/D34005 llvm-svn: 304987
* Add scheduler classes to integer/float horizontal operations.Andrew V. Tischenko2017-06-086-5/+126
| | | | | | | This patch will close PR32801. Differential Revision: https://reviews.llvm.org/D33203 llvm-svn: 304986
* [PDB] Don't crash on /debug:fastlink PDBs.Zachary Turner2017-06-081-2/+5
| | | | | | | | | | Apparently support for /debug:fastlink PDBs isn't part of the DIA SDK (!), and it was causing llvm-pdbdump to crash because we weren't checking for a null pointer return value. This manifests when calling findChildren on the IDiaSymbol, and it returns E_NOTIMPL. llvm-svn: 304982
* InferAddressSpaces: Avoid assertion failure with replacing identicalNirav Dave2017-06-081-0/+7
| | | | | | | | | | | | | | | cloned constexpr Have cloneConstantExprWithNewAddressSpaces return nullptr when returning initial ConstantExpr. Reviewers: arsenm Subscribers: jholewinski, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D33995 llvm-svn: 304975
* This patch closes PR28513: an optimization of multiplication by different ↵Andrew V. Tischenko2017-06-081-1/+81
| | | | | | | | constants. The initial patch was rejected: I fixed the issue and re-apply it. llvm-svn: 304972
* [BPI] Don't assume that strcmp returning >0 is more likely than <0John Brawn2017-06-083-9/+50
| | | | | | | | | | | | | | | | | | | | The zero heuristic assumes that integers are more likely positive than negative, but this also has the effect of assuming that strcmp return values are more likely positive than negative. Given that for nonzero strcmp return values it's the ordering of arguments that determines the sign of the result there's no reason to assume that's true. Fix this by inspecting the LHS of the compare and using TargetLibraryInfo to decide if it's strcmp-like, and if so only assume that nonzero is more likely than zero i.e. strings are more often different than the same. This causes a slight code generation change in the spec2006 benchmark 403.gcc, but with no noticeable performance impact. The intent of this patch is to allow better optimisation of dhrystone on Cortex-M cpus, but currently it won't as there are also some changes that need to be made to if-conversion. Differential Revision: https://reviews.llvm.org/D33934 llvm-svn: 304970
* Object: Factor out the code for creating the irsymtab for an arbitrary ↵Peter Collingbourne2017-06-083-45/+69
| | | | | | | | | | | bitcode file. This code now lives in lib/Object. The idea is that it can now be reused by IRObjectFile among other things. Differential Revision: https://reviews.llvm.org/D31921 llvm-svn: 304958
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-078-83/+113
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 304954
* GlobalsModRef: Ensure optnone+readonly/readnone attributes are respectedDavid Blaikie2017-06-071-8/+5
| | | | llvm-svn: 304945
* [InstCombine] fold lshr (sext X), C1 --> zext (lshr X, C2)Sanjay Patel2017-06-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was discussed in D33338. We have larger pattern-matching ending in a truncate that we can reduce or remove by handling these smaller patterns first. Further motivation is that narrower shift ops are easier for value tracking and zext is better than sext. http://rise4fun.com/Alive/rhh Name: boolshift %sext = sext i1 %x to i8 %r = lshr i8 %sext, 7 => %r = zext i1 %x to i8 Name: noboolshift %sext = sext i3 %x to i8 %r = lshr i8 %sext, 7 => %sh = lshr i3 %x, 2 %r = zext i3 %sh to i8 Differential Revision: https://reviews.llvm.org/D33879 llvm-svn: 304939
* [Hexagon] Generate 'inbounds' GEPs in HexagonCommonGEPKrzysztof Parzyszek2017-06-071-4/+12
| | | | llvm-svn: 304937
* [DAG] Improve Store Merge candidate pruning. NFC.Nirav Dave2017-06-071-3/+15
| | | | | | | | | When considering merging stores values are the results of loads only consider stores whose values come from loads from the same base. This fixes much of the longer compile times in PR33330. llvm-svn: 304934
* Fix builin_expect lowering bugXinliang David Li2017-06-071-1/+3
| | | | | | | | PR33346 Skip cases when expected value is not constant int. llvm-svn: 304933
* [mssa] Fix case when there is no definition in a block prior to an inserted use.Alina Sbirlea2017-06-071-11/+6
| | | | | | | | | | | | | | | Summary: Check that the first access before one being tested is valid. Before this patch, if there was no definition prior to the Use being tested, the first time Iter was deferenced, it hit the sentinel. Reviewers: dberlin, gbiv Subscribers: sanjoy, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D33950 llvm-svn: 304926
* [CGP] avoid zext/trunc of a memcmp expansion compareSanjay Patel2017-06-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This could be viewed as another shortcoming of the DAGCombiner: when both operands of a compare are zexted from the same source type, we should be able to compare the original types. The effect on PowerPC perf is likely unnoticeable, but there's a visible regression for x86 if we feed the suboptimal IR for memcmp expansion to the DAG: _cmp_eq4_zexted_to_i64: movl (%rdi), %ecx movl (%rsi), %edx xorl %eax, %eax cmpq %rdx, %rcx sete %al _cmp_eq4_better: movl (%rdi), %ecx xorl %eax, %eax cmpl (%rsi), %ecx sete %al llvm-svn: 304923
* [AMDGPU][MC] Corrected error message for s_waitcnt helpersDmitry Preobrazhensky2017-06-071-12/+16
| | | | | | | | | | See Bug 32711: https://bugs.llvm.org//show_bug.cgi?id=32711 Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D33781 llvm-svn: 304922
* LowerTypeTests: Generate simpler IR for br(llvm.type.test, then, else).Peter Collingbourne2017-06-071-2/+19
| | | | | | | | | | | | | This makes it so that the code quality for CFI checks when compiling with -O2 and linking with --lto-O0 is similar to that of the rest of the code. Reduces the size of a chrome binary built with -O2/--lto-O0 by about 750KB. Differential Revision: https://reviews.llvm.org/D33925 llvm-svn: 304921
* [CGP] pass size as param in MemCmpExpansion; NFCISanjay Patel2017-06-071-10/+5
| | | | | | Avoid extracting the constant int twice. llvm-svn: 304920
* [mips][dsp] Modify repl.ph to accept signed immediate valuesPetar Jovanovic2017-06-071-2/+3
| | | | | | | | | | | | Changed immediate type for repl.ph from uimm10 to simm10 as per the specs. Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33594 llvm-svn: 304918
* [CGP] pass size as param in MemCmpExpansion; NFCISanjay Patel2017-06-071-13/+8
| | | | | | Avoid extracting the constant int twice. llvm-svn: 304917
* [CGP] getParent()->getParent() --> getFunction(); NFCISanjay Patel2017-06-071-5/+4
| | | | llvm-svn: 304916
* [SystemZ] Propagate MachineMemOperandsJonas Paulsson2017-06-071-6/+19
| | | | | | | In emitCondStore() and emitMemMemWrapper(). Review: Ulrich Weigand llvm-svn: 304913
* [DAG] Move SelectionDAG::isCommutativeBinOp to TargetLowering.Simon Pilgrim2017-06-073-7/+7
| | | | | | | | This will allow commutation of target-specific DAG nodes in future patches Differential Revision: https://reviews.llvm.org/D33882 llvm-svn: 304911
* AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legalTom Stellard2017-06-071-0/+3
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33949 llvm-svn: 304910
* [x86] avoid flipping sign bits for vector icmp by using known bitsSanjay Patel2017-06-071-1/+7
| | | | | | | | | | | | | | | | If we know that both operands of an unsigned integer vector comparison are non-negative, then it's safe to directly use a signed-compare-greater-than instruction (the only non-equality integer vector compare predicate provided by SSE/AVX). We're intentionally not changing the condition code to signed in order to preserve the existing transforms that use min/max/psubus below here. This should solve PR33276: https://bugs.llvm.org/show_bug.cgi?id=33276 Differential Revision: https://reviews.llvm.org/D33862 llvm-svn: 304909
* [CGP] add helper function for generating compare of load pairs; NFCISanjay Patel2017-06-071-5/+16
| | | | | | | | In the special (but also the likely common) case, we can avoid the multi-block complexity of the general algorithm, so moving this part off on its own will make it re-usable. llvm-svn: 304908
* [PowerPC] Eliminate integer compare instructions - vol. 5Nemanja Ivanovic2017-06-071-0/+26
| | | | | | | | Adds handling for i64 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33720 llvm-svn: 304907
* [mips] do not use FastISel when -mxgot is presentPetar Jovanovic2017-06-071-2/+3
| | | | | | | | | | | | | | | The clang compiler by default uses FastISel when invoked with -O0, which is also the default. In that case, passing of -mxgot does not get honored, i.e. the code path that is to deal with large got is not taken. Clang produces same output regardless of -mxgot being present or not. This change checks whether -mxgot is passed as an option, and turns off FastISel if it is. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33593 llvm-svn: 304906
* [ARM] Use FixupKind variable in processFixupValue (cleanup, NFC).Florian Hahn2017-06-071-10/+10
| | | | llvm-svn: 304905
* [CGP] fix formatting in MemCmpExpansion; NFCSanjay Patel2017-06-071-8/+6
| | | | llvm-svn: 304903
* [ARM] GlobalISel: Purge G_SEQUENCEDiana Picus2017-06-073-53/+52
| | | | | | | | | | | | | | | | | According to the commit message from r296921, G_MERGE_VALUES and G_INSERT are to be preferred over G_SEQUENCE. Therefore, stop generating G_SEQUENCE in the ARM backend and remove the code dealing with it. This boils down to the code breaking up double values for the soft float calling convention. Use G_MERGE_VALUES + G_UNMERGE_VALUES instead of G_SEQUENCE + G_EXTRACT for it. This maps very nicely to VMOVDRR + VMOVRRD and simplifies the code in the instruction selector. There's one occurence of G_SEQUENCE left in arm-irtranslator.ll, but that is part of the target-independent code for translating constant structs. Therefore, it is beyond the scope of this commit. llvm-svn: 304902
* [PowerPC] Eliminate integer compare instructions - vol. 3Nemanja Ivanovic2017-06-071-0/+35
| | | | | | | | Adds handling for i32 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33718 llvm-svn: 304901
* [ARM] GlobalISel: Support G_XORDiana Picus2017-06-072-1/+2
| | | | | | | | | Same as the other binary operators: - legalize to 32 bits - map to GPRs - select to EORrr via TableGen'erated code llvm-svn: 304898
* evert "[mips] Fix test mips64fpldst.ll with machine verifier enabled"Simon Dardis2017-06-071-1/+5
| | | | | | | This reverts commit r301394. It broke some internal buildbots, reverting while the issue is being investigated. llvm-svn: 304896
* [X86][SSE] Fix an issue with PEXTRW/PEXTRB indices during shuffle combiningSimon Pilgrim2017-06-071-3/+6
| | | | | | We were checking that the index was in range of the destination vector type, not the (larger) source vector type llvm-svn: 304894
* [ARM] GlobalISel: Support G_ORDiana Picus2017-06-072-1/+2
| | | | | | | | | Same as the other binary operators: - legalize to 32 bits - map to GPRs - select ORRrr thanks to TableGen'erated code llvm-svn: 304890
* [ARM] GlobalISel: Support G_ANDDiana Picus2017-06-072-1/+2
| | | | | | | | | This is identical to the support for the other binary operators: - widen to s32 - map into GPR - select ANDrr (via TableGen'erated code) llvm-svn: 304885
* [Linker] Remove warning when linking ARM and Thumb IR modules.Florian Hahn2017-06-071-0/+15
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch updates Triple::isCompatibleWith to make armxx and thumbxx triples compatible, as long as the subarch, vendor, os, envorionment and object format match. Thumb/ARM code generation should be controlled using the thumb-mode per-function target feature rather than by the triple to allow mixing Thumb and ARM functions. D33448 updates Clang's codegen to add thumb-mode for all functions with armxx or thumbxx triples. Reviewers: echristo, t.p.northover, rafael, kristof.beyls, rengolin, tejohnson Reviewed By: tejohnson Subscribers: rinon, eugenis, pcc, srhines, aemerson, mehdi_amini, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33287 llvm-svn: 304884
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