summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* MC: Simplify main section layout process by moving alignment into LayoutSection.Daniel Dunbar2010-03-251-30/+31
| | | | llvm-svn: 99529
* MC: Sink Section address assignment into LayoutSection.Daniel Dunbar2010-03-251-6/+6
| | | | llvm-svn: 99528
* Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain ↵Jakob Stoklund Olesen2010-03-259-21/+223
| | | | | | | | | | | | | | | | | | | | | | crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. llvm-svn: 99524
* Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,Johnny Chen2010-03-252-20/+31
| | | | | | | instead of the current N2V. Format of NVDupLane instances are set to NEONFrm currently. llvm-svn: 99518
* Reapply Kevin's change 94440, now that Chris has fixed the limitation onBob Wilson2010-03-252-0/+48
| | | | | | opcode values fitting in one byte (svn r99494). llvm-svn: 99514
* Add comment.Devang Patel2010-03-251-0/+3
| | | | llvm-svn: 99507
* MC/Mach-O: Switch to MCSectionData::getOrdinal.Daniel Dunbar2010-03-251-18/+4
| | | | llvm-svn: 99504
* Scheduler assumes SDDbgValue nodes are in source order. That's true ↵Evan Cheng2010-03-251-0/+8
| | | | | | currently. But add an assertion to verify it. llvm-svn: 99501
* MC: Explicity track section and fragment ordinals.Daniel Dunbar2010-03-251-0/+13
| | | | llvm-svn: 99500
* Fix -Asserts warning.Daniel Dunbar2010-03-251-2/+1
| | | | llvm-svn: 99499
* Change tblgen to emit FOOISD opcode names as twoChris Lattner2010-03-251-3/+9
| | | | | | | | | | | | | | bytes instead of one byte. This is important because we're running up to too many opcodes to fit in a byte and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE making the numbering sparse. This just bites the bullet and bloats out the table. In practice, this increases the size of the x86 isel table from 74.5K to 76K. I think we'll cope :) This fixes rdar://7791648 llvm-svn: 99494
* Include isFunctionLocal while calculating folding node set profile for a MDNode.Devang Patel2010-03-251-13/+14
| | | | llvm-svn: 99490
* Remove a fixme that doesn't make sense any more.Evan Cheng2010-03-251-2/+0
| | | | llvm-svn: 99489
* fix PR6642, GVN forwarding from memset to load of the base of the memset.Chris Lattner2010-03-251-7/+7
| | | | llvm-svn: 99488
* Make sure SDDbgValue.Invalid is initialized to false by all the constructors.Evan Cheng2010-03-251-2/+2
| | | | llvm-svn: 99487
* eliminate a bunch more parallels now that schedulingChris Lattner2010-03-251-205/+150
| | | | | | | handles dead implicit results more aggressively. More to come, I think this is now just a data entry problem. llvm-svn: 99486
* Make the NDEBUG assertion stronger and more clear what is Chris Lattner2010-03-251-5/+20
| | | | | | | | | | | | | | | | | | | | | happening. Enhance scheduling to set the DEAD flag on implicit defs more aggressively. Before, we'd set an implicit def operand to dead if it were present in the SDNode corresponding to the machineinstr but had no use. Now we do it in this case AND if the implicit def does not exist in the SDNode at all. This exposes a couple of problems: one is the FIXME, which causes a live intervals crash on CodeGen/X86/sibcall.ll. The second is that it makes machinecse and licm more aggressive (which is a good thing) but also exposes a case where licm hoists a set0 and then it doesn't get resunk. Talking to codegen folks about both these issues, but I need this patch in in the meantime. llvm-svn: 99485
* Include isFunctionLocal while calculating folding node set provide for a MDNode.Devang Patel2010-03-251-0/+1
| | | | llvm-svn: 99484
* Reapply r99451 with a fix to move the NoInline check to the cost functionsEric Christopher2010-03-252-4/+17
| | | | | | instead of InlineFunction. llvm-svn: 99483
* reapply 99444/99445, which I speculatively reverted inChris Lattner2010-03-252-78/+95
| | | | | | r99453. llvm-svn: 99482
* MC: Route access to SectionData offset and file size through MCAsmLayout.Daniel Dunbar2010-03-252-17/+42
| | | | llvm-svn: 99474
* MC: Route access to Fragment offset and effective size through MCAsmLayout.Daniel Dunbar2010-03-252-34/+58
| | | | llvm-svn: 99473
* Change how dbg_value sdnodes are converted into machine instructions. Their ↵Evan Cheng2010-03-256-112/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. Here is a theoretical example that illustrates why the placement is important. tmp1 = store tmp1 -> x ... tmp2 = add ... ... call ... store tmp2 -> x Now mem2reg comes along: tmp1 = dbg_value (tmp1 -> x) ... tmp2 = add ... ... call ... dbg_value (tmp2 -> x) When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1. Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers"). This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed. llvm-svn: 99469
* MC: Eliminate MC{Fragment,{Section,Symbol}Data}::getAddress.Daniel Dunbar2010-03-251-9/+7
| | | | llvm-svn: 99467
* MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment ↵Daniel Dunbar2010-03-251-2/+2
| | | | | | | | address with a symbol address. - This fixes the integrated-as nightly test regressions. llvm-svn: 99466
* Avoid being influenced by dbg_value instructions.Evan Cheng2010-03-252-2/+2
| | | | llvm-svn: 99465
* Disable folding loads into tail call in 32-bit PIC mode. It can introduce ↵Evan Cheng2010-03-251-1/+5
| | | | | | | | | | | | | | | | | illegal code like this: addl $12, %esp popl %esi popl %edi popl %ebx popl %ebp jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class. The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit. llvm-svn: 99455
* revert 99444/99445. This doesn't cause the failure of Chris Lattner2010-03-242-95/+78
| | | | | | | | 2006-07-19-stwbrx-crash.ll for me, but it's the only likely patch in the blame list of several bots. Lets see if this fixes it. llvm-svn: 99453
* Temporarily revert this, it's causing an issue with an internal project.Eric Christopher2010-03-242-16/+3
| | | | llvm-svn: 99451
* Speculatively revert this to see if it fixes buildbot failures.Bob Wilson2010-03-242-48/+0
| | | | | | | | | | | | --- Reverse-merging r99440 into '.': U test/MC/AsmParser/X86/x86_32-bit_cat.s U test/MC/AsmParser/X86/x86_32-encoding.s U include/llvm/IntrinsicsX86.td U include/llvm/CodeGen/SelectionDAGNodes.h U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86ISelLowering.h llvm-svn: 99450
* remove dead argument.Chris Lattner2010-03-242-5/+3
| | | | llvm-svn: 99445
* split EmitNode in half to reduce indentation.Chris Lattner2010-03-242-78/+97
| | | | llvm-svn: 99444
* Added the Advanced Encryption Standard (AES) Instructions.Kevin Enderby2010-03-242-0/+48
| | | | llvm-svn: 99440
* Make the use of the vmla and vmls VFP instructions controllable via cmd line.Jim Grosbach2010-03-245-4/+30
| | | | | | | Preliminary testing shows significant performance wins by not using these instructions. llvm-svn: 99436
* Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it doesKevin Enderby2010-03-241-1/+1
| | | | | | | | not get an "Unknown immediate size" assert failure when used. All instructions of this form have an 8-bit immediate. Also added a test case of an example instruction that is of this form. llvm-svn: 99435
* Per chris's request, add some comments.Nate Begeman2010-03-241-2/+17
| | | | llvm-svn: 99434
* Use SP filename directly instead of SP's context's filename.Devang Patel2010-03-241-2/+2
| | | | llvm-svn: 99429
* Trivial formating change.Johnny Chen2010-03-241-2/+2
| | | | llvm-svn: 99428
* BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.Nate Begeman2010-03-241-75/+68
| | | | llvm-svn: 99423
* Revert Edwin's change that is breaking MultiSource/Applications/ClamAV/clamscan.Bob Wilson2010-03-241-3/+1
| | | | | | | | --- Reverse-merging r99400 into '.': D test/CodeGen/Generic/2010-03-24-liveintervalleak.ll U lib/CodeGen/LiveIntervalAnalysis.cpp llvm-svn: 99419
* Move OptChkCall off LibCallOptimization into StrCpyOpt.Evan Cheng2010-03-241-7/+6
| | | | llvm-svn: 99418
* Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.Johnny Chen2010-03-242-25/+9
| | | | | | NVCVTFrm will later be used to describe "vcvt with fractional bits". llvm-svn: 99415
* Fix minor style issues.Dan Gohman2010-03-246-211/+206
| | | | llvm-svn: 99414
* Reverted r99376. The disassembler will deal with the 2-reg format of these twoJohnny Chen2010-03-241-3/+0
| | | | | | N3VX instructions using special case code. llvm-svn: 99409
* tweak the arm if conversion heuristicJim Grosbach2010-03-241-7/+1
| | | | llvm-svn: 99402
* Fix memory leak in liveintervals: the destructor for VNInfos must be called,Torok Edwin2010-03-241-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | otherwise the SmallVector it contains doesn't free its memory. In most cases LiveIntervalAnalysis could get away by not calling the destructor, because VNInfos are bumpptr-allocated, and smallvectors usually don't grow. However when the SmallVector does grow it always leaks. This is the valgrind shown leak from the original testcase: ==8206== 18,304 bytes in 151 blocks are definitely lost in loss record 164 of 164 ==8206== at 0x4A079C7: operator new(unsigned long) (vg_replace_malloc.c:220) ==8206== by 0x4DB7A7E: llvm::SmallVectorBase::grow_pod(unsigned long, unsigned long) (in /home/edwin/clam/git/builds/defaul t/libclamav/.libs/libclamav.so.6.1.0) ==8206== by 0x4F90382: llvm::VNInfo::addKill(llvm::SlotIndex) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libcl amav.so.6.1.0) ==8206== by 0x5126B5C: llvm::LiveIntervals::handleVirtualRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::M achineInstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int, llvm::LiveInterval&) (in /home/edwin/clam/git/builds/defau lt/libclamav/.libs/libclamav.so.6.1.0) ==8206== by 0x512725E: llvm::LiveIntervals::handleRegisterDef(llvm::MachineBasicBlock*, llvm::ilist_iterator<llvm::MachineI nstr>, llvm::SlotIndex, llvm::MachineOperand&, unsigned int) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav .so.6.1.0) ==8206== by 0x51278A8: llvm::LiveIntervals::computeIntervals() (in /home/edwin/clam/git/builds/default/libclamav/.libs/libc lamav.so.6.1.0) ==8206== by 0x5127CB4: llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&) (in /home/edwin/clam/git/builds/de fault/libclamav/.libs/libclamav.so.6.1.0) ==8206== by 0x4DAE935: llvm::FPPassManager::runOnFunction(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama v/.libs/libclamav.so.6.1.0) ==8206== by 0x4DAEB10: llvm::FunctionPassManagerImpl::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclama v/.libs/libclamav.so.6.1.0) ==8206== by 0x4DAED3D: llvm::FunctionPassManager::run(llvm::Function&) (in /home/edwin/clam/git/builds/default/libclamav/.l ibs/libclamav.so.6.1.0) ==8206== by 0x4D8BE8E: llvm::JIT::runJITOnFunctionUnlocked(llvm::Function*, llvm::MutexGuard const&) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0) ==8206== by 0x4D8CA72: llvm::JIT::getPointerToFunction(llvm::Function*) (in /home/edwin/clam/git/builds/default/libclamav/.libs/libclamav.so.6.1.0) llvm-svn: 99400
* Finally land the InvokeInst operand reordering.Gabor Greif2010-03-2411-29/+38
| | | | | | | | | | | | I have audited all getOperandNo calls now, fixing hidden assumptions. CallSite related uglyness will be eliminated successively. Note this patch has a long and griveous history, for all the back-and-forths have a look at CallSite.h's log. llvm-svn: 99399
* tighten a type and remove trailing whitespace, no functional changesGabor Greif2010-03-241-12/+12
| | | | llvm-svn: 99398
* increase const goodness and remove pointless getUser() callsGabor Greif2010-03-241-7/+9
| | | | llvm-svn: 99395
* cache result of UI.getOperandNo() instead of calling it twice, it is cheaper ↵Gabor Greif2010-03-241-2/+3
| | | | | | this way llvm-svn: 99394
OpenPOWER on IntegriCloud