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* R600/SI: Add a lower case alias for subtarget feature: +DumpCodeTom Stellard2015-04-281-0/+5
| | | | | | | llc converts all feature strings to lower case, while the LLVM C API does not, so we need a lower case alias in order to test this with llc. llvm-svn: 236003
* [NVPTX] Handle addrspacecast constant expressions in aggregate initializersJustin Holewinski2015-04-284-2/+268
| | | | | | | | | | | We need to track if an AddrSpaceCast expression was seen when generating an MCExpr for a ConstantExpr. This change introduces a custom lowerConstant method to the NVPTX asm printer that will create NVPTXGenericMCSymbolRefExpr nodes at the appropriate places to encode the information that a given symbol needs to be casted to a generic address. llvm-svn: 236000
* [opaque pointer type] Encode the allocated type of an alloca rather than its ↵David Blaikie2015-04-282-8/+16
| | | | | | pointer result type. llvm-svn: 235998
* move IR-level optimization flags into their own structSanjay Patel2015-04-283-9/+12
| | | | | | | | | | | | | | | | | | | | | | This is a preliminary step to using the IR-level floating-point fast-math-flags in the SDAG (D8900). In this patch, we introduce the optimization flags as their own struct. As noted in the TODO comment, we should eventually share this data between the IR passes and the backend. We also switch the existing nsw / nuw / exact bit functionality of the BinaryWithFlagsSDNode class to use the new struct. The tradeoff is that instead of using the free but limited space of SDNode's SubclassData, we add a data member to the subclass. This means we don't have to repeat all of the get/set methods per flag, but we're potentially adding size to all nodes of this subclassi type. In practice on 64-bit systems (measured on Linux and MacOS X), there is no size difference between an SDNode and BinaryWithFlagsSDNode after this change: they're both 80 bytes. This means that we had at least one free byte to play with due to struct alignment. Differential Revision: http://reviews.llvm.org/D9325 llvm-svn: 235997
* Use a std::vector to record the offsets of the sections. NFC.Rafael Espindola2015-04-281-10/+8
| | | | llvm-svn: 235995
* Avoid an extra loop for computing the section size. NFC.Rafael Espindola2015-04-281-29/+13
| | | | llvm-svn: 235994
* Fixed crash of variable shift inst on AVX2Elena Demikhovsky2015-04-281-3/+1
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=22955 llvm-svn: 235993
* [mips] [IAS] Do not generate redundant ORi in createLShiftOri.Toma Tabacu2015-04-281-0/+4
| | | | | | | | | | | | | | Summary: If the immediate is 0, the ORi is pointless. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8969 llvm-svn: 235990
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-2872-3681/+4271
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Use CIE version 4 for dwarf4.Rafael Espindola2015-04-281-4/+15
| | | | | | | According to http://www.dwarfstd.org/doc/DWARF4.pdf appendix F the CIE version for dwarf 4 is 4. llvm-svn: 235988
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-2872-4271/+3681
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.Toma Tabacu2015-04-281-13/+13
| | | | | | | | | | | | | | Summary: The new name is more accurate with regard to the functionality. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8968 llvm-svn: 235984
* [mips] [IAS] Store the expandLoadImm destination register in a variable. NFC.Toma Tabacu2015-04-281-11/+12
| | | | | | | | | | | | | | Summary: This removes multiple calls to getReg() and saves us column space in the source file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8924 llvm-svn: 235978
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-2872-3681/+4271
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* AVX-512: Added "pandn" intrinsics setElena Demikhovsky2015-04-281-0/+6
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 235971
* Masked gather and scatter: Added code for SelectionDAG.Elena Demikhovsky2015-04-283-0/+203
| | | | | | | | All other patches, including tests will follow. http://reviews.llvm.org/D7665 llvm-svn: 235970
* [opaque pointer type] Encode the pointee type in the bitcode for 'cmpxchg'David Blaikie2015-04-282-6/+9
| | | | | | | | | | | | | | | | | As a space optimization, this instruction would just encode the pointer type of the first operand and use the knowledge that the second and third operands would be of the pointee type of the first. When typed pointers go away, this assumption will no longer be available - so encode the type of the second operand explicitly and rely on that for the third. Test case added to demonstrate the backwards compatibility concern, which only comes up when the definition of the second operand comes after the use (hence the weird basic block sequence) - at which point the type needs to be explicitly encoded in the bitcode and the record length changes to accommodate this. llvm-svn: 235966
* [MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.Ahmed Bougacha2015-04-284-1/+14
| | | | | | | | | | This matches other assemblers and is less unexpected (e.g. PR23227). On ELF, I tried binutils gas v2.24 and nasm 2.10.09, and they both agree on LShr. On COFF, I couldn't get my hands on an assembler yet, so don't change the behavior. For now, don't change it on non-AArch64 Darwin either, as the other assembler is gas v1.38, which does an AShr. llvm-svn: 235963
* DebugInfo: Support up to 2^16 arguments in a subprogramDuncan P. N. Exon Smith2015-04-281-5/+2
| | | | | | | | | Support up to 2^16 arguments to a function. If we do hit the limit, assert out rather than restarting at 0 as we've done historically. This fixes PR23332. A clang test will follow. llvm-svn: 235955
* Cleanup, remove unused return valueMatthias Braun2015-04-282-6/+3
| | | | llvm-svn: 235952
* [MC] Split MCBinaryExpr::Shr into LShr and AShr.Ahmed Bougacha2015-04-283-5/+8
| | | | | | | | Defaulting to AShr without consulting the target MCAsmInfo isn't OK. Add a flag to fix that. Keep it off for now: target migrations will follow in separate commits. llvm-svn: 235951
* [MC] Move getBinOpPrecedence into AsmParser. NFC.Ahmed Bougacha2015-04-281-2/+5
| | | | | | In preparation for a future patch. llvm-svn: 235950
* Switch lowering: use uint32_t for weights everywhereHans Wennborg2015-04-272-6/+12
| | | | | | | | | I previously thought switch clusters would need to use uint64_t in case the weights of multiple cases overflowed a 32-bit int. It turns out that the weights on a terminator instruction are capped to allow for being added together, so using a uint32_t should be safe. llvm-svn: 235945
* LTO: Add API to choose whether to embed uselistsDuncan P. N. Exon Smith2015-04-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | Reverse libLTO's default behaviour for preserving use-list order in bitcode, and add API for controlling it. The default setting is now `false` (don't preserve them), which is consistent with `clang`'s default behaviour. Users of libLTO should call `lto_codegen_should_embed_uselists(CG,true)` prior to calling `lto_codegen_write_merged_modules()` whenever the output file isn't part of the production workflow in order to reproduce results with subsequent calls to `llc`. (I haven't added tests since `llvm-lto` (the test tool for LTO) doesn't support bitcode output, and even if it did: there isn't actually a good way to test whether a tool has passed the flag. If the order is already "natural" (if the order will already round-trip) then no use-list directives are emitted at all. At some point I'll circle back to add tests to `llvm-as` (etc.) that they actually respect the flag, at which point I can somehow add a test here as well.) llvm-svn: 235943
* Switch lowering: Take branch weight into account when ordering for fall-throughHans Wennborg2015-04-271-3/+4
| | | | | | | | | | | Previously, the code would try to put a fall-through case last, even if that meant moving a case with much higher branch weight further down the chain. Ordering by branch weight is most important, putting a fall-through block last is secondary. llvm-svn: 235942
* LTO: Simplify code generator initializationDuncan P. N. Exon Smith2015-04-271-15/+2
| | | | | | | Simplify `LTOCodeGenerator` initialization by initializing simple fields at their definition. llvm-svn: 235939
* remove obsolete pattern matches for scalar SSE opsSanjay Patel2015-04-271-15/+1
| | | | | | | | The blendi pattern should always replace the insertps pattern after: http://reviews.llvm.org/rL232850 http://reviews.llvm.org/rL235124 llvm-svn: 235930
* Use CIE version 1 for .eh_frame.Rafael Espindola2015-04-271-1/+2
| | | | | | | | | | According to http://www.linuxbase.org/betaspecs/lsb/LSB-Core-generic/LSB-Core-generic/ehframechpt.html we should always use 1. llvm-svn: 235923
* [AArch64] Also combine vector selects fed by non-i1 SETCCs.Ahmed Bougacha2015-04-271-3/+15
| | | | | | | | | | | | | | After legalization, scalar SETCC has an i32 result type on AArch64. The i1 requirement seems too conservative, replace it with an assert. This also means that we now can run after legalization. That should also be fine, since the ops legalizer runs again after each combine, and all types created all have the same sizes as the (legal) inputs. Exposed by r235917; while there, robustize its tests (bsl also uses the register it defines). llvm-svn: 235922
* Add missing library dependency in libPDB.Pete Cooper2015-04-271-1/+1
| | | | | | | | PDB uses COFFObjectFile::getPE32Header which lives in libObject. Make sure that LLVMBuild.txt reflects this dependency. llvm-svn: 235920
* [AArch64] Don't assert when combining (v3f32 select (setcc f64)).Ahmed Bougacha2015-04-271-0/+6
| | | | | | | | When the setcc has f64 operands, we can't build a vector setcc mask to feed a vselect, because f64 doesn't divide v3f32 evenly. Just bail out when that happens. llvm-svn: 235917
* Fixes a hang that can occur if a signal comes in during malloc calls.Chris Bieneman2015-04-271-0/+6
| | | | | | We need to dereference the signals mutex during handler registration so that we force its construction. This is to prevent the first use being during handling an actual signal because you can't safely allocate memory in a signal handler. llvm-svn: 235914
* Silence unused variable errors for no-asserts buildsBill Schmidt2015-04-271-0/+4
| | | | llvm-svn: 235913
* Switch lowering: order bit tests by branch weight.Hans Wennborg2015-04-271-1/+4
| | | | llvm-svn: 235912
* [opaque pointer type] encode the pointee type of global variablesDavid Blaikie2015-04-272-12/+20
| | | | | | | | | Use a few extra bits in the const field (after widening it from a fixed single bit) to stash the address space which is no longer provided by the type (and an extra bit in there to specify that we're using that new encoding). llvm-svn: 235911
* [PPC64LE] Remove unnecessary swaps from lane-insensitive vector computationsBill Schmidt2015-04-276-0/+824
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new SSA MI pass that runs on little-endian PPC64 code with VSX enabled. Loads and stores of 4x32 and 2x64 vectors without alignment constraints are accomplished for little-endian using lxvd2x/xxswapd and xxswapd/stxvd2x. The existence of the additional xxswapd instructions hurts performance in comparison with big-endian code, but they are necessary in the general case to support correct semantics. However, the general case does not apply to most vector code. Many vector instructions are lane-insensitive; they do not "care" which lanes the parallel computations are performed within, provided that the resulting data is stored into the correct locations. Thus this pass looks for computations that perform only lane-insensitive operations, and remove the unnecessary swaps from loads and stores in such computations. Future improvements will allow computations using certain lane-sensitive operations to also be optimized in this manner, by modifying the lane-sensitive operations to account for the permuted order of the lanes. However, this patch only adds the infrastructure to permit this; no lane-sensitive operations are optimized at this time. This code is heavily exercised by the various vectorizing applications in the projects/test-suite tree. For the time being, I have only added one simple test case to demonstrate what the pass is doing. Although it is quite simple, it provides coverage for much of the code, including the special case handling of copies and subreg-to-reg operations feeding the swaps. I plan to add additional tests in the future as I fill in more of the "special handling" code. Two existing tests were affected, because they expected the swaps to be present, but they are now removed. llvm-svn: 235910
* fix 80-cols; NFCSanjay Patel2015-04-271-2/+3
| | | | llvm-svn: 235902
* Fix build broken by incorrect class name.Zachary Turner2015-04-271-3/+3
| | | | llvm-svn: 235901
* Make llvm-symbolizer work on Windows.Zachary Turner2015-04-272-0/+104
| | | | | | | Differential Revision: http://reviews.llvm.org/D9234 Reviewed By: Alexey Samsonov llvm-svn: 235900
* Make an RAII com initializer.Zachary Turner2015-04-274-0/+88
| | | | | | | Differential Revision: http://reviews.llvm.org/D9267 Reviewed By: Aaron Ballman, David Majnemer llvm-svn: 235898
* fix typos; NFCSanjay Patel2015-04-271-1/+1
| | | | llvm-svn: 235896
* [mips] Correct bytes to bits in 2 comments. NFC.Toma Tabacu2015-04-271-2/+2
| | | | llvm-svn: 235891
* AVX-512: added calling conventions for i1 vectors.Elena Demikhovsky2015-04-272-3/+27
| | | | | | Fixed bug: https://llvm.org/bugs/show_bug.cgi?id=20724 llvm-svn: 235889
* [Hexagon] Use constant extenders to fix up hardware loopsBrendon Cahoon2015-04-276-72/+114
| | | | | | | | | | Use a loop instruction with a constant extender for a hardware loop instruction that is too far away from the start of the loop. This is cheaper than changing the SA register value. Differential Revision: http://reviews.llvm.org/D9262 llvm-svn: 235882
* [mips] [IAS] Improve warning for using AT with .set noat.Toma Tabacu2015-04-271-12/+7
| | | | | | | | | | | | | | | | | Summary: Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name. I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8479 llvm-svn: 235881
* Reapply "[mips][FastISel] Implement shift ops for Mips fast-isel.""Vasileios Kalintiris2015-04-271-0/+80
| | | | | | | | This reapplies r235194, which was reverted in r235495 because it was causing a failure in our out-of-tree buildbots for MIPS. With the sign-extension patch in r235718, this patch doesn't cause any problem any more. llvm-svn: 235878
* [mips] [IAS] Rename getATRegNum and setATReg to {g,s}etATRegIndex. NFC.Toma Tabacu2015-04-271-8/+8
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8480 llvm-svn: 235877
* AVX-512: Extend/Truncate operations for SKX,Elena Demikhovsky2015-04-272-36/+139
| | | | | | SETCC for bit-vectors llvm-svn: 235875
* [MC] [IAS] Add support for the \@ .macro pseudo-variable.Toma Tabacu2015-04-271-29/+53
| | | | | | | | | | | | | | | | | | Summary: When used, it is substituted with the number of .macro instantiations we've done up to that point in time. So if this is the 1st time we've instantiated a .macro (any .macro, regardless of name), \@ will instantiate to 0, if it's the 2nd .macro instantiation, it will instantiate to 1 etc. It can only be used inside a .macro definition, an .irp definition or an .irpc definition (those last 2 uses are undocumented). Reviewers: echristo, rafael Reviewed By: rafael Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D9197 llvm-svn: 235862
* Constfold insertelement to undef when index is out-of-boundsPawel Bylica2015-04-271-7/+14
| | | | | | | | | | | | | | | | | | | Summary: This patch adds constant folding of insertelement instruction to undef value when index operand is constant and is not less than vector size or is undef. InstCombine does not support this case, but I'm happy to add it there also if this change is accepted. Test Plan: Unittests and regression tests for ConstProp pass. Reviewers: majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9287 llvm-svn: 235854
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