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* [mips] N64 static relocation model supportSimon Dardis2017-01-2612-115/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293164
* [ARM] GlobalISel: Load i1, i8 and i16 args from stackDiana Picus2017-01-263-14/+44
| | | | | | | | | | | | | Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
* [PM] Use PoisoningVH correctly when merely deleting entries in a mapChandler Carruth2017-01-261-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | with it. This code was dereferencing the PoisoningVH which isn't allowed once it is poisoned. But the code itself really doesn't need to access the pointer, it is just doing the safe stuff of clearing out data structures keyed on the pointer value. Change the code to use iterators to erase directly from a DenseMap. This is also substantially more efficient as it avoids lots of hashing and lookups to do the erasure. DenseMap supports iterating behind the iteration which is fairly easy to implement. Sadly, I don't have a test case here. I'm not even close and I don't know that I ever will be. The issue is that several of the tricky aspects of fixing this only show up when you cause the stack's SmallVector to be in *EXACTLY* the right location. I only ever got a reproduction for those with Clang, and only with *exactly* the right command line flags. Any adjustment, even to seemingly unrelated flags, would make partial and half-way solutions magically start to "work". In good news, all of this was caught with the LLVM test suite. Also, there is no *specific* code here that is untested, just that the old pattern of code won't immediately fail on any test case I've managed to contrive. llvm-svn: 293160
* [AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last ↵Craig Topper2017-01-261-1/+1
| | | | | | DAG combine phase where I had originally meant to put it. llvm-svn: 293157
* [X86] When bitcasting INSERT_SUBVECTOR/EXTRACT_SUBVECTOR to match masked ↵Craig Topper2017-01-261-2/+2
| | | | | | operations, use the correct type for the immediate operand. llvm-svn: 293156
* [TargetTransformInfo] Refactor and improve getScalarizationOverhead()Jonas Paulsson2017-01-266-57/+26
| | | | | | | | | | | | | | | | | Refactoring to remove duplications of this method. New method getOperandsScalarizationOverhead() that looks at the present unique operands and add extract costs for them. Old behaviour was to just add extract costs for one operand of the type always, which still happens in getArithmeticInstrCost() if no operands are provided by the caller. This is a good start of improving on this, but there are more places that can be improved by using getOperandsScalarizationOverhead(). Review: Hal Finkel https://reviews.llvm.org/D29017 llvm-svn: 293155
* [DAGCombiner] Fold extract_subvector of undef to undef. Fold away inserting ↵Craig Topper2017-01-261-0/+8
| | | | | | undef subvectors. llvm-svn: 293152
* [X86] Add demanded elts support for the inputs to pclmul intrinsicCraig Topper2017-01-261-0/+38
| | | | | | | | This intrinsic uses bit 0 and bit 4 of an immediate argument to determine which bits of its inputs to read. This patch uses this information to simplify the demanded elements of the input vectors. Differential Revision: https://reviews.llvm.org/D28979 llvm-svn: 293151
* Revert test commitTaewook Oh2017-01-261-1/+0
| | | | llvm-svn: 293150
* test commitTaewook Oh2017-01-261-3/+4
| | | | llvm-svn: 293148
* [PM] Simplify the new PM interface to the loop unroller and expose twoChandler Carruth2017-01-262-4/+12
| | | | | | | | | | | | | | factory functions for the two modes the loop unroller is actually used in in-tree: simplified full-unrolling and the entire thing including partial unrolling. I've also wired these up to nice names so you can express both of these being in a pipeline easily. This is a precursor to actually enabling these parts of the O2 pipeline. Differential Revision: https://reviews.llvm.org/D28897 llvm-svn: 293136
* [libFuzzer] remove a bit of stale codeKostya Serebryany2017-01-262-6/+0
| | | | llvm-svn: 293129
* [libFuzzer] further simplify __sanitizer_cov_trace_pc_guardKostya Serebryany2017-01-262-9/+7
| | | | llvm-svn: 293128
* AMDGPU: Fold fneg into round instructionsMatt Arsenault2017-01-261-1/+7
| | | | llvm-svn: 293127
* [libFuzzer] simplify the code for __sanitizer_cov_trace_pc_guard and make ↵Kostya Serebryany2017-01-265-4/+31
| | | | | | sure it is not asan/msan-instrumented llvm-svn: 293125
* [LoopUnroll] Properly update loopinfo for runtime unrolling by 2Michael Kuperstein2017-01-263-10/+19
| | | | | | | | | | | Even when we don't create a remainder loop (that is, when we unroll by 2), we may duplicate nested loops into the remainder. This is complicated by the fact the remainder may itself be either inserted into an outer loop, or at the top level. In the latter case, we may need to create new top-level loops. Differential Revision: https://reviews.llvm.org/D29156 llvm-svn: 293124
* [NewGVN] Skip uses in unreachable blocks.Davide Italiano2017-01-261-0/+6
| | | | | | | | Otherwise we ask for a domtree node that's not there, and we crash. Differential Revision: https://reviews.llvm.org/D29145 llvm-svn: 293122
* [llc] Add -pass-remarks-outputAdam Nemet2017-01-261-5/+11
| | | | | | | This is the opt/llc counterpart of -fsave-optimization-record to output optimization remarks in a YAML file. llvm-svn: 293121
* LowerTypeTests: Ignore external globals with type metadata.Peter Collingbourne2017-01-261-3/+6
| | | | | | Thanks to Davide Italiano for finding the problem and providing a test case. llvm-svn: 293119
* [libFuzzer] don't call GetPreviousInstructionPc on the hot path -- only when ↵Kostya Serebryany2017-01-261-18/+22
| | | | | | dumping the PCs llvm-svn: 293117
* [APFloat] Fix comments. NFC.Tim Shen2017-01-261-28/+30
| | | | | | | | | | | | Summary: Fix comments in response to jlebar's comments in D27872. Reviewers: jlebar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29109 llvm-svn: 293116
* [ValueTracking] Implement SignBitMustBeZero correctly for sqrt.Justin Lebar2017-01-261-4/+12
| | | | | | | | | | | | | | Summary: Previously we assumed that the result of sqrt(x) always had 0 as its sign bit. But sqrt(-0) == -0. Reviewers: hfinkel, efriedma, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28928 llvm-svn: 293115
* [NewGVN] Simplify folding a lambda used only once. NFCI.Davide Italiano2017-01-251-5/+3
| | | | llvm-svn: 293112
* New OptimizationRemarkEmitter pass for MIRAdam Nemet2017-01-256-46/+235
| | | | | | | | | | | | | | | | | This allows MIR passes to emit optimization remarks with the same level of functionality that is available to IR passes. It also hooks up the greedy register allocator to report spills. This allows for interesting use cases like increasing interleaving on a loop until spilling of registers is observed. I still need to experiment whether reporting every spill scales but this demonstrates for now that the functionality works from llc using -pass-remarks*=<pass>. Differential Revision: https://reviews.llvm.org/D29004 llvm-svn: 293110
* [OptDiag] Split code region out of DiagnosticInfoOptimizationBaseAdam Nemet2017-01-252-21/+22
| | | | | | | | | | | | | | | | | | Code region is the only part of this class that is IR-specific. Code region is moved down in the inheritance tree to a new derived class, called DiagnosticInfoIROptimization. All the existing remarks are derived from this new class now. This allows the new MIR pass-remark classes to be derived from DiagnosticInfoOptimizationBase. Also because we keep the name DiagnosticInfoOptimizationBase, the clang parts don't need any adjustment. Differential Revision: https://reviews.llvm.org/D29003 llvm-svn: 293109
* NFC: Rename (PDB) RawSession to NativeSessionAdrian McCarthy2017-01-2526-176/+188
| | | | | | | | This eliminates one overload on the term Raw. Differential Revision: https://reviews.llvm.org/D29098 llvm-svn: 293104
* Revert "[PPC] Give unaligned memory access lower cost on processor that ↵Daniel Jasper2017-01-251-4/+0
| | | | | | | | | | supports it" This reverts commit r292680. It is causing significantly worse performance and test timeouts in our internal builds. I have already routed reproduction instructions your way. llvm-svn: 293092
* [pdb] Correctly parse the hash adjusters table from TPI stream.Zachary Turner2017-01-251-9/+6
| | | | | | | | | | | | | This is not a list of pairs, it is a hash table data structure. We now correctly parse this out and dump it from llvm-pdbdump. We still need to understand the conditions that lead to a type getting an entry in the hash adjuster table. That will be done in a followup investigation / patch. Differential Revision: https://reviews.llvm.org/D29090 llvm-svn: 293090
* SDag: fix how initial loads are formed when splitting vector ops.Tim Northover2017-01-251-1/+4
| | | | | | | | Later code expects the vector loads produced to be directly concatenable, which means we shouldn't pad anything except the last load produced with UNDEF. llvm-svn: 293088
* GlobalISel: rework getOrCreateVReg to avoid double lookup. NFC.Tim Northover2017-01-251-20/+20
| | | | | | Thanks to Quentin for suggesting the refactoring. llvm-svn: 293087
* DebugInfo: remove unused parameter from function. NFC.Tim Northover2017-01-252-4/+2
| | | | | | | I think it's a hold-over from some previous iteration, but it's never set to true in LLVM as it exists now. llvm-svn: 293086
* MemorySSA: Link all defs together into an intrusive defslist, to make ↵Daniel Berlin2017-01-251-36/+130
| | | | | | | | | | | | | | | | | | | | | | | updater easier Summary: This is the first in a series of patches to add a simple, generalized updater to MemorySSA. For MemorySSA, every def is may-def, instead of the normal must-def. (the best way to think of memoryssa is "everything is really one variable, with different versions of that variable at different points in the program). This means when updating, we end up having to do a bunch of work to touch defs below and above us. In order to support this quickly, i have ilist'd all the defs for each block. ilist supports tags, so this is quite easy. the only slightly messy part is that you can't have two iplists for the same type that differ only whether they have the ownership part enabled or not, because the traits are for the value type. The verifiers have been updated to test that the def order is correct. Reviewers: george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29046 llvm-svn: 293085
* [AMDGPU] Bump up n_type for metadata v2Konstantin Zhuravlyov2017-01-251-1/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D29115 llvm-svn: 293083
* AMDGPU: Set call_convention bit in kernel_code_tMatt Arsenault2017-01-251-0/+5
| | | | | | | According to the documentation this is supposed to be -1 if indirect calls are not supported. llvm-svn: 293081
* [XRay][AArch64] More staging for tail call support in XRay on AArch64 - in LLVMSerge Rogatch2017-01-252-0/+13
| | | | | | | | | | | | | | | | Summary: This patch prepares more for tail call support in XRay. Until the logging part supports tail calls, this is just staging, so it seems LLVM part is mostly ready with this patch. Related: https://reviews.llvm.org/D28948 (compiler-rt) Reviewers: dberris, rengolin Reviewed By: dberris Subscribers: llvm-commits, iid_iunknown, aemerson Differential Revision: https://reviews.llvm.org/D28947 llvm-svn: 293080
* Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFCKrzysztof Parzyszek2017-01-256-34/+17
| | | | llvm-svn: 293077
* Revert "Do not verify dominator tree if it has no roots"Chad Rosier2017-01-252-8/+0
| | | | | | | This reverts commit r293033, per Danny's comment. In short, we require domtrees to have roots at all times. llvm-svn: 293075
* PowerPC: Slight cleanup of getReservedRegs(); NFCMatthias Braun2017-01-251-19/+10
| | | | | | | | Change getReservedRegs() to not mark a register as reserved and then revert that decision in some cases. Motivated by the discussion in https://reviews.llvm.org/D29056 llvm-svn: 293073
* Add loop pass insertion point EP_LateLoopOptimizationsKrzysztof Parzyszek2017-01-251-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D28694 llvm-svn: 293067
* [Guards] Introduce loop-predication passArtur Pilipenko2017-01-255-0/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces guard based loop predication optimization. The new LoopPredication pass tries to convert loop variant range checks to loop invariant by widening checks across loop iterations. For example, it will convert for (i = 0; i < n; i++) { guard(i < len); ... } to for (i = 0; i < n; i++) { guard(n - 1 < len); ... } After this transformation the condition of the guard is loop invariant, so loop-unswitch can later unswitch the loop by this condition which basically predicates the loop by the widened condition: if (n - 1 < len) for (i = 0; i < n; i++) { ... } else deoptimize This patch relies on an NFC change to make ScalarEvolution::isMonotonicPredicate public (revision 293062). Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D29034 llvm-svn: 293064
* [AArch64] Minor code refactoring. NFC.Chad Rosier2017-01-251-9/+10
| | | | llvm-svn: 293063
* [InstCombine] Canonicalize guards for NOT OR conditionArtur Pilipenko2017-01-251-0/+12
| | | | | | | | | | | | This is a partial fix for Bug 31520 - [guards] canonicalize guards in instcombine Reviewed By: apilipenko Differential Revision: https://reviews.llvm.org/D29075 Patch by Maxim Kazantsev. llvm-svn: 293061
* [InstCombine][SSE] Add support for PACKSS/PACKUS constant foldingSimon Pilgrim2017-01-251-0/+94
| | | | | | Differential Revision: https://reviews.llvm.org/D28949 llvm-svn: 293060
* [ARM] GlobalISel: Fix stack-use-after-scope bug.Martin Bohme2017-01-251-1/+1
| | | | | | | | | | | | | | | | | Summary: Lifetime extension wasn't triggered on the result of BuildMI because the reference was non-const. However, instead of adding a const, I've removed the reference entirely as RVO should kick in anyway. Reviewers: rovka, bkramer Reviewed By: bkramer Subscribers: aemerson, rengolin, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29124 llvm-svn: 293059
* [InstCombine] Canonicalize guards for AND conditionArtur Pilipenko2017-01-251-0/+17
| | | | | | | | | | | | This is a partial fix for Bug 31520 - [guards] canonicalize guards in instcombine Reviewed By: apilipenko Differential Revision: https://reviews.llvm.org/D29074 Patch by Maxim Kazantsev. llvm-svn: 293058
* [InstCombine] Allow InstrCombine to remove one of adjacent guards if they ↵Artur Pilipenko2017-01-251-0/+10
| | | | | | | | | | | | | | are equivalent This is a partial fix for Bug 31520 - [guards] canonicalize guards in instcombine Reviewed By: majnemer, apilipenko Differential Revision: https://reviews.llvm.org/D29071 Patch by Maxim Kazantsev. llvm-svn: 293056
* [SLP] Improve horizontal vectorization for non-power-of-2 number ofAlexey Bataev2017-01-251-2/+4
| | | | | | | | | | | | | instructions. If number of instructions in horizontal reduction list is not power of 2 then only PowerOf2Floor(NumberOfInstructions) last elements are actually vectorized, other instructions remain scalar. Patch tries to vectorize the remaining elements either. Differential Revision: https://reviews.llvm.org/D28959 llvm-svn: 293042
* Mark @llvm.powi.* as safe to speculatively execute.whitequark2017-01-251-0/+4
| | | | | | | | | | | | Floating point intrinsics in LLVM are generally not speculatively executed, since most of them are defined to behave the same as libm functions, which set errno. However, the @llvm.powi.* intrinsics do not correspond to any libm function, and lacks any defined error handling semantics in LangRef. It most certainly does not alter errno. llvm-svn: 293041
* [X86] enable memory interleaving for X86\SLM arch. Mohammed Agabaria2017-01-251-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D28547 llvm-svn: 293040
* Fix buildbot failures introduced by 293036Artur Pilipenko2017-01-251-2/+5
| | | | | | Fix unused variable, specify types explicitly to make VC compiler happy. llvm-svn: 293039
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