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* [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FPAsaf Badouh2015-09-214-46/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D12524 llvm-svn: 248147
* [mips] Allow constant expressions in second argument of .cpsetup.Daniel Sanders2015-09-212-8/+11
| | | | | | | | | | | | | | Summary: Also tightened up the test and made a trivial fix to prevent double-newline after emitting .cpsetup directives. Reviewers: vkalintiris Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D12956 llvm-svn: 248143
* Use makeArrayRef or None to avoid unnecessarily mentioning the ArrayRef type ↵Craig Topper2015-09-215-18/+18
| | | | | | extra times. NFC llvm-svn: 248140
* Don't pass StringRefs around by const reference. Pass by value instead per ↵Craig Topper2015-09-212-6/+6
| | | | | | coding standards. NFC llvm-svn: 248136
* Cleanup places that passed SMLoc by const reference to pass it by value ↵Craig Topper2015-09-209-20/+15
| | | | | | instead. NFC llvm-svn: 248135
* [IndVars] Use C++11 style field initialization; NFCI.Sanjoy Das2015-09-201-14/+7
| | | | llvm-svn: 248131
* [IndVars] Don't add a level of indentation for namespace {. NFC.Sanjoy Das2015-09-201-77/+77
| | | | | | Whitespace-only change. llvm-svn: 248130
* AVX512: Implemented encoding and intrinsics for vcmpss/sd.Igor Breger2015-09-204-42/+129
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12593 llvm-svn: 248121
* [X86][AVX512] extend support in Scalar conversionAsaf Badouh2015-09-203-127/+231
| | | | | | | | | | add scalar FP to Int conversion with truncation intrinsics add scalar conversion FP32 from/to FP64 intrinsics add rounding mode and SAE mode encoding for these intrinsics Differential Revision: http://reviews.llvm.org/D12665 llvm-svn: 248117
* AVX512: vsqrtss/sd encoding and intrinsics implementation.Igor Breger2015-09-203-93/+63
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12102 llvm-svn: 248116
* [X86][AVX512DQ] Add fpclass instruction Asaf Badouh2015-09-205-2/+119
| | | | | | Differential Revision: http://reviews.llvm.org/D12931 llvm-svn: 248115
* [X86] Fix sitofp and uitofp instruction matching failures with long double ↵Michael Kuperstein2015-09-201-9/+14
| | | | | | | | | | | | and avx512 The operation action for i32 and i64 cannot be set to legal, as long double needs custom lowering. Patch by: mitch.l.bodart@intel.com Differential Revision: http://reviews.llvm.org/D12372 llvm-svn: 248114
* AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, ↵Igor Breger2015-09-201-0/+16
| | | | | | | | | | vshufi32x4 Added tests for intrinsics. Differential Revision: http://reviews.llvm.org/D12525 llvm-svn: 248113
* [IndVars] Don't repeat function names in comment; NFC.Sanjoy Das2015-09-201-65/+62
| | | | | | Only changes comments. llvm-svn: 248112
* AVX512: Implement instructions encoding, lowering and intrinsicsIgor Breger2015-09-204-65/+137
| | | | | | | | | vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4 Added tests for encoding, lowering and intrinsics. Differential Revision: http://reviews.llvm.org/D11893 llvm-svn: 248111
* ARM: cleanup formattingSaleem Abdulrasool2015-09-201-2/+2
| | | | | | clang-format a line which was poorly formatted. NFC. llvm-svn: 248110
* [IndVars] Fix a bug in r248045.Sanjoy Das2015-09-201-14/+19
| | | | | | | | | | | | | | Because -indvars widens induction variables through arithmetic, `NeverNegative` cannot be a property of the `WidenIV` (a `WidenIV` manages information for all transitive uses of an IV being widened, including uses of `-1 * IV`). Instead it must live on `NarrowIVDefUse` which manages information for a specific def-use edge in the transitive use list of an induction variable. This change also adds a test case that demonstrates the problem with r248045. llvm-svn: 248107
* [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEFSimon Pilgrim2015-09-191-4/+57
| | | | | | | | | | Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1)) Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x)) Differential Revision: http://reviews.llvm.org/D12663 llvm-svn: 248091
* [InstCombine] Use SimplifyDemandedVectorEltsLow helper function. NFCI.Simon Pilgrim2015-09-191-17/+8
| | | | | | Use the SimplifyDemandedVectorEltsLow helper function introduced in D12680. llvm-svn: 248089
* AMDGPU: Remove dead codeMatt Arsenault2015-09-195-18/+2
| | | | | | | getCFGStructurizerRegClass is not used for SI, so move it into R600 specific stuff. llvm-svn: 248087
* NFC: Fix indentation and add braces to clarify nested of else-statement.Bob Wilson2015-09-191-2/+3
| | | | llvm-svn: 248086
* [PrologEpilogInserter] Minor refactoring.Maksim Panchenko2015-09-191-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D12924 llvm-svn: 248084
* Test commit. Fix comment. NFC.Maksim Panchenko2015-09-191-1/+1
| | | | llvm-svn: 248082
* [InstCombine] FoldICmpCstShrCst failed for ashr when comparing against -1David Majnemer2015-09-191-1/+1
| | | | | | | | | (icmp eq (ashr C1, %V) -1) may have multiple answers if C1 is not a power of two and has the sign bit set. This fixes PR24873. llvm-svn: 248074
* [InstCombine] FoldICmpCstShrCst didn't handle icmps of -1 in the ashr case ↵David Majnemer2015-09-191-6/+10
| | | | | | correctly llvm-svn: 248073
* [IndVars] Widen more comparisons for non-negative induction varsSanjoy Das2015-09-181-3/+26
| | | | | | | | | | | | | | | | | | | | Summary: If an induction variable is provably non-negative, its sign extension is equal to its zero extension. This means narrow uses like icmp slt iNarrow %indvar, %rhs can be widened into icmp slt iWide zext(%indvar), sext(%rhs) Reviewers: atrick, mcrosier, hfinkel Subscribers: hfinkel, reames, llvm-commits Differential Revision: http://reviews.llvm.org/D12745 llvm-svn: 248045
* Update edge weights properly when merging blocks in if-conversion.Cong Hou2015-09-181-6/+70
| | | | | | | | In if-conversion, there is a utility function MergeBlocks() that is used to merge blocks. However, when new edges are built in this function the edge weight is either not provided or not updated properly, leading to a modified CFG with incorrect edge weights. This patch corrects this issue. Differential Revision: http://reviews.llvm.org/D12513 llvm-svn: 248030
* Limit the range of processors supported by ARM fast isel to v6 orEric Christopher2015-09-181-0/+4
| | | | | | | | later as that's all that is tested right now. Fixes PR24858. llvm-svn: 248027
* Clean up: Refactoring the hardcoded value of 6 for ↵Larisse Voufo2015-09-184-8/+23
| | | | | | FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886) llvm-svn: 248022
* Make MachineScheduler debug output less confusing.James Y Knight2015-09-182-6/+31
| | | | | | At least...a little bit. llvm-svn: 248020
* Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are ↵Cong Hou2015-09-181-10/+17
| | | | | | | | | | scaled by a probability to avoid precision issue. In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison. Differential Revision: http://reviews.llvm.org/D12742 llvm-svn: 248018
* SelectionDAGDumper: Leave out the <multiple use> markersMatthias Braun2015-09-181-3/+0
| | | | | | | | | They mostly clutter the output while it is still possible to see which node has multiple users without them. Differential Revision: http://reviews.llvm.org/D12569 llvm-svn: 248013
* SelectionDAGDumper: Avoid unnecessary newlinesMatthias Braun2015-09-181-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: t0 = EntryToken:ch t0: <multiple use> t0: <multiple use> t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0 t25 = IMPLICIT_DEF:v4f32 t26 = HADDPSrr:v4f32 t1, t25 t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26 t23: <multiple use> t23: <multiple use> t24 = RETQ:ch Register:v4f32 %XMM0, t23, t23:1 After: t0: <multiple use> t0: <multiple use> t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0 t26 = X86ISD::FHADD:v4f32 t1, undef:v4f32 t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26 t23: <multiple use> t21 = TargetConstant:i16<0> t23: <multiple use> t24 = X86ISD::RET_FLAG:ch t23, t21, Register:v4f32 %XMM0, t23:1 Differential Revision: http://reviews.llvm.org/D12568 llvm-svn: 248012
* SelectionDAGDumper: Hide [ID=X], [ORD=X] and source locations by default.Matthias Braun2015-09-181-16/+23
| | | | | | | | You can show them with the new -dag-dump-verbose switch. Differential Revision: http://reviews.llvm.org/D12566 llvm-svn: 248011
* SelectionDAG: Introduce PersistentID to SDNode for assert builds.Matthias Braun2015-09-182-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gives us more human readable numbers to identify nodes in debug dumps. Before: 0x7fcbd9700160: ch = EntryToken 0x7fcbd985c7c8: i64 = Register %RAX ... 0x7fcbd9700160: <multiple use> 0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2] 0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3] 0x7fcbd985c7c8: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3] Now: t0: ch = EntryToken t5: i64 = Register %RAX ... t0: <multiple use> t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2] t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3] t5: <multiple use> t6: <multiple use> t6: <multiple use> t7: ch = RETQ t5, t6, t6:1 [ORD=3] Differential Revision: http://reviews.llvm.org/D12564 llvm-svn: 248010
* [AArch64] Improved bitfield instruction selection.Geoff Berry2015-09-181-11/+67
| | | | | | | | | | | | | | | | | | Summary: For bitfield insert OR matching, check both operands for larger pattern first before checking for smaller pattern. Add pattern for unsigned bitfield insert-in-zero done with SHL+AND. Resolves PR21631. Reviewers: jmolloy, t.p.northover Subscribers: aemerson, rengolin, llvm-commits, mcrosier Differential Revision: http://reviews.llvm.org/D12908 llvm-svn: 248006
* Remove temporary file on signal.Rafael Espindola2015-09-181-1/+6
| | | | | | Without this lld leaves temporary files behind when it crashes. llvm-svn: 247994
* [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.Daniel Sanders2015-09-181-0/+6
| | | | | | | | | | | | | | | Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
* [AArch64] Reorder cases to improve readability. NFC.Chad Rosier2015-09-181-9/+9
| | | | llvm-svn: 247989
* [AArch64] Remove some redundant cases. NFC.Chad Rosier2015-09-181-16/+8
| | | | llvm-svn: 247988
* Silencing a -Wsign-compare warning; NFC.Aaron Ballman2015-09-181-1/+1
| | | | llvm-svn: 247986
* [LazyValueInfo] Report nonnull range for nonnull pointersIgor Laevsky2015-09-181-2/+4
| | | | | | | | | | | | Currently LazyValueInfo will report only alloca's as having nonnull range. For loads with !nonnull metadata it will bailout with no additional information. Same is true for calls returning nonnull pointers. This change extends LazyValueInfo to handle additional nonnull instructions. Differential Revision: http://reviews.llvm.org/D12932 llvm-svn: 247985
* Support align attribute for return valuesArtur Pilipenko2015-09-182-1/+9
| | | | | | | | Reviewed By: reames Differential Revision: http://reviews.llvm.org/D12844 llvm-svn: 247984
* [Support] Reapply r245289 "Always wait for GraphViz before opening the viewer"Michael Kruse2015-09-181-1/+1
| | | | | | | | | | | | | The change was accidentally undone by r245290. Original log message: When calling DisplayGraph and a PS viewer is chosen, two programs are executed: The GraphViz generator and the PostScript viewer. Always wait for the generator to finish to ensure that the .ps file is written before opening the viewer for that file. DisplayGraph's wait parameter refers to whether to wait until the user closes the viewer. This happened on Windows and if none of the options to open the .dot file directly applies, also on Linux. Differential Revision: http://reviews.llvm.org/D11876 llvm-svn: 247980
* [WinEH] Moved funclet pads should be in relative orderDavid Majnemer2015-09-181-9/+5
| | | | | | | | | | | We shifted the MachineBasicBlocks to the end of the MachineFunction in DFS order. This will not ensure that MachineBasicBlocks which fell through to one another will remain contiguous. Instead, implement a stable sort algorithm for iplist. This partially reverts commit r214150. llvm-svn: 247978
* Whitespace. Indent with spaces instead of a tab.Bob Wilson2015-09-181-1/+1
| | | | llvm-svn: 247969
* [ShrinkWrap] Refactor the handling of infinite loop in the analysis.Quentin Colombet2015-09-171-9/+11
| | | | | | | | | - Strenghten the logic to be sure we hoist the restore point out of the current loop. (The fixes a bug with infinite loop, added as part of the patch.) - Walk over the exit blocks of the current loop to conver to the desired restore point in one iteration of the update loop. llvm-svn: 247958
* [opaque pointer types] Add an explicit pointee type to alias records in the IRDavid Blaikie2015-09-172-24/+41
| | | | | | | | | | Since aliases actually use and verify their explicit type already, no further invalid testing is required here. The invalid.test:ALIAS-TYPE-MISMATCH case catches errors due to emitting a non-pointee type in the new format or a non-pointer type in the old format. llvm-svn: 247952
* [bpf] expand indirect branchesAlexei Starovoitov2015-09-171-0/+1
| | | | | | | | BPF instruction set doesn't have indirect branches. Expand them. Reported by John Fastabend. llvm-svn: 247951
* Revert "(HEAD -> master, origin/master, origin/HEAD) RegisterPressure: Move ↵Matthias Braun2015-09-172-34/+36
| | | | | | | | | | LiveInRegs/LiveOutRegs from RegisterPressure to PressureTracker" This reverts commit r247943. Accidental commit, code review was not finished yet. llvm-svn: 247945
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