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* Debug Info: Emit the dwo_name only in skeleton CUs, not in DWOs.Adrian Prantl2015-09-221-3/+5
| | | | llvm-svn: 248340
* LiveIntervalAnalysis: Avoid multiple connected liveness componentsMatthias Braun2015-09-221-8/+26
| | | | | | | | | | | | | We may have subregister defs which are unused but not discovered and cleaned up prior to liveness analysis. This creates multiple connected components in the resulting live range which are forbidden in the MachineVerifier because they would unnecesarily constrain the register allocator. Rewrite those dead definitions to define a newly created virtual register. Differential Revision: http://reviews.llvm.org/D13035 llvm-svn: 248335
* LiveInterval: Distribute subregister liveranges to new intervals in ↵Matthias Braun2015-09-221-29/+65
| | | | | | | | | | | | | | | | ConnectedVNInfoEqClasses::Distribute() This improves ConnectedVNInfoEqClasses::Distribute() to distribute the segments and value numbers in the subranges instead of conservatively clearing all subregister info. No separate test here, just clearing the subrange instead of properly distributing them would however break my upcoming fix regarding dead super register definitions. Differential Revision: http://reviews.llvm.org/D13075 llvm-svn: 248334
* [Unroll] Do not crash trying to propagate a value to vector load.Michael Zolotukhin2015-09-221-0/+6
| | | | llvm-svn: 248333
* [Unroll] Follow-up for r247769: fix a bug in UnrolledInstAnalyzer::visitLoad.Michael Zolotukhin2015-09-221-1/+1
| | | | | | | | Apart from checking that GlobalVariable is a constant, we should check that it's not a weak constant, in which case we can't propagate its value. llvm-svn: 248327
* [ARM] Emit clrex in the expanded cmpxchg fail block.Ahmed Bougacha2015-09-222-0/+8
| | | | | | | | | | | | | | | | | | | ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
* [AArch64] Emit clrex in the expanded cmpxchg fail block.Ahmed Bougacha2015-09-223-3/+23
| | | | | | | | | | | | | | | | | In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248291
* Make helper function static. NFC.Benjamin Kramer2015-09-221-3/+3
| | | | llvm-svn: 248278
* [mips][sched] Split IIBranch into specific instruction classes.Daniel Sanders2015-09-229-38/+83
| | | | | | | | | | | | | | | | | | | | | Summary: Almost no functional change since the InstrItinData's have been duplicated. The one functional change is to remove IIBranch from the MSA branches. The classes will be assigned to the MSA instructions as part of implementing the P5600 scheduler. II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've preserved the itinerary information for the corresponding pseudo instructions to avoid making a functional change to these pseudos in this patch. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12189 llvm-svn: 248273
* [mips][sched] Temporarily rename IIAlu to IIM16Alu. NFC.Daniel Sanders2015-09-222-61/+62
| | | | | | | | | | | | | | | Summary: The only instructions left in IIAlu are MIPS16 specific. We're not implementing a MIPS16 scheduler at this time so rename the class to make it obvious that they are MIPS16 instructions. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12188 llvm-svn: 248267
* Don't raise inexact when lowering ceil, floor, round, trunc.Stephen Canon2015-09-223-211/+51
| | | | | | | | The C standard has historically not specified whether or not these functions should raise the inexact flag. Traditionally on Darwin, these functions *did* raise inexact, and the llvm lowerings followed that conventions. n1778 (C bindings for IEEE-754 (2008)) clarifies that these functions should not set inexact. This patch brings the lowerings for arm64 and x86 in line with the newly specified behavior. This also lets us fold some logic into TD patterns, which is nice. Differential Revision: http://reviews.llvm.org/D12969 llvm-svn: 248266
* Prune trailing whitespaces.NAKAMURA Takumi2015-09-226-31/+31
| | | | llvm-svn: 248265
* Untabify.NAKAMURA Takumi2015-09-2233-125/+115
| | | | llvm-svn: 248264
* Reformat blank lines.NAKAMURA Takumi2015-09-2220-66/+32
| | | | llvm-svn: 248263
* Reformat comment lines.NAKAMURA Takumi2015-09-2211-46/+51
| | | | llvm-svn: 248262
* Reformat.NAKAMURA Takumi2015-09-2213-205/+176
| | | | llvm-svn: 248261
* ARMInstrInfo.cpp: Reformat.NAKAMURA Takumi2015-09-221-66/+65
| | | | llvm-svn: 248260
* Fix utf8 chars.NAKAMURA Takumi2015-09-221-1/+1
| | | | llvm-svn: 248259
* [mips][ias] Implement .cpreturn directive.Daniel Sanders2015-09-223-0/+54
| | | | | | | | | | | | | | | | | Summary: Based on a patch by David Chisnall. I've modified the original patch as follows: * Moved the expansion to the TargetStreamers so that the directive isn't expanded when emitting assembly. * Fixed an operand order bug. * Changed the move instructions from DADDu to OR to match recent changes to GAS. Reviewers: vkalintiris Subscribers: llvm-commits, emaste, seanbruno, theraven Differential Revision: http://reviews.llvm.org/D13017 llvm-svn: 248258
* [mips][sched] Added class for WSBHDaniel Sanders2015-09-223-6/+9
| | | | | | | | | | | | | Summary: No functional change since no InstrItinData is provided. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12190 llvm-svn: 248257
* [X86][SSE] Match zero/any extension shuffles that don't start from the first ↵Simon Pilgrim2015-09-221-26/+108
| | | | | | | | | | | | element This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
* AMDGPU: Remove unnecessary checkMatt Arsenault2015-09-221-4/+0
| | | | | | | If the instruction doesn't have enough operands, it either shouldn't be marked as isCommutable or is malformed. llvm-svn: 248242
* LiveIntervalAnalysis: Factor common code into splitSeparateComponents; NFCMatthias Braun2015-09-225-58/+51
| | | | llvm-svn: 248241
* Remove unused TargetTransformInfo dependency from SafeStack pass.Evgeniy Stepanov2015-09-221-2/+0
| | | | llvm-svn: 248233
* [LoopUnswitch] Require DominatorTree info.Michael Zolotukhin2015-09-221-11/+7
| | | | | | | | | | | | | | | | | | | | | Summary: We should either require the DT info to be available, or check if it's available in every place we use DT (and we already miss such check in one place, which causes failures in some cases). As other loop passes preserve DT and it's usually available, it makes sense to just require it here. There is no regression test, because the bug only shows up if pass manager decides to clean DT info right before LoopUnswitch. If loop-unswitch is run separately, DT is available, so bug isn't exposed. Reviewers: chandlerc, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13036 llvm-svn: 248230
* [SCEV] Use SaveAndRestore<T> instead of a hand rolled struct; NFCI.Sanjoy Das2015-09-221-13/+2
| | | | | | | `ClearWalkingBEDominatingCondsOnExit` is exactly `SaveAndRestore<bool>`, so use `SaveAndRestore<bool>` instead. llvm-svn: 248227
* function names should start with a lower case letter; NFCSanjay Patel2015-09-211-91/+91
| | | | llvm-svn: 248224
* don't repeat function/variable names in header comments; NFCSanjay Patel2015-09-211-87/+74
| | | | llvm-svn: 248222
* [LICM] Hoist calls to readonly argmemonly functions even with stores in the loopPhilip Reames2015-09-211-0/+11
| | | | | | | | | | | | We know that an argmemonly function can only access memory pointed to by it's pointer arguments. Rather than needing to consider all possible stores as aliasing (as we do for a readonly function), we can only consider the aliasing of the pointer arguments. Note that this change only addresses hoisting. I'm thinking about how to address speculation safety as well, but that will be a different change. FYI, argmemonly disallows accessing memory through non-pointer typed arguments. Differential Revision: http://reviews.llvm.org/D12771 llvm-svn: 248220
* Fix for pr24866Philip Reames2015-09-211-1/+8
| | | | | | Turns out that not every basic block is guaranteed to have a node within the DominatorTree. This is really hard to trigger, but the test case from the PR managed to do so. There's active discussion continuing about what documentation and/or invariants needed cleaned up. llvm-svn: 248216
* Fix UB: can't bind a reference to nullptr (NFC)Mehdi Amini2015-09-211-1/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 248213
* auto and range-for-ify some things to make changing container types a bit ↵David Blaikie2015-09-211-36/+25
| | | | | | easier in the (possibly near) future llvm-svn: 248212
* [DAGCombiner] Improve FMA support for interpolation patternsSimon Pilgrim2015-09-211-0/+89
| | | | | | | | | | This patch adds support for combining patterns such as (FMUL(FADD(1.0, x), y)) and (FMUL(FSUB(x, 1.0), y)) to their FMA equivalents. This is useful in particular for linear interpolation cases such as (FADD(FMUL(x, t), FMUL(y, FSUB(1.0, t)))) Differential Revision: http://reviews.llvm.org/D13003 llvm-svn: 248210
* [ARM] Do not scale vext with a factorJeroen Ketema2015-09-211-9/+1
| | | | | | | | | | | | | The vext pseudo-instruction takes the number of elements that need to be extracted, not the number of bytes. Hence, use the number of elements directly instead of scaling them with a factor. Reviewers: Silviu Baranga, James Molloy (not reflected in the differential revision) Differential Revision: http://reviews.llvm.org/D12974 llvm-svn: 248208
* [DAGCombiner] Tidy up FMA combine helpers. NFCI.Simon Pilgrim2015-09-211-25/+21
| | | | | | Based on feedback for D13003. llvm-svn: 248206
* [LoopUtils,LV] Propagate fast-math flags on generated FCmp instructionsJames Molloy2015-09-212-2/+11
| | | | | | | | | We're currently losing any fast-math flags when synthesizing fcmps for min/max reductions. In LV, make sure we copy over the scalar inst's flags. In LoopUtils, we know we only ever match patterns with hasUnsafeAlgebra, so apply that to any synthesized ops. llvm-svn: 248201
* Remove roundingMode argument in APFloat::modStephen Canon2015-09-214-7/+6
| | | | | | Because mod is always exact, this function should have never taken a rounding mode argument. The actual implementation still has issues, which I'll look at resolving in a subsequent patch. llvm-svn: 248195
* Fix accidentally committed debug printingMatt Arsenault2015-09-211-14/+1
| | | | llvm-svn: 248190
* [DivergenceAnalysis] Separated definition of class into header.Marcello Maggioni2015-09-211-54/+25
| | | | | | | | | | | | The definition of the DivergenceAnalysis pass was in a CPP file and wasn't accessible to users of the analysis to get it through "getAnalysis<>()". This patch extracts the definition into a separate header that can be used by users of the analysis to fetch the results. Patch by Volkan Keles (vkeles@apple.com) llvm-svn: 248186
* SelectionDAG: Use InsertNode for EntryNodeMatthias Braun2015-09-211-2/+2
| | | | | | This fixes problems where two nodes have persistent debug id 0 assigned. llvm-svn: 248182
* [FunctionAttrs] Extract a helper function for the core logic used toChandler Carruth2015-09-211-90/+117
| | | | | | | | evaluate whether 'readonly' or 'readnone' apply to a given function. This both reduces indentation and will make it easy to share the logic with a new pass manager implementation. llvm-svn: 248181
* [SystemZ] Fix expansion of ISD::FPOW and ISD::FSINCOSUlrich Weigand2015-09-211-0/+2
| | | | | | | | | | | | | The ISD::FPOW and ISD::FSINCOS opcodes default to Legal, but there is no legal instruction for those on SystemZ. This could cause LLVM internal errors. Fixed by setting the operation action to Expand for those opcodes. Also added test cases for all other LLVM IR intrinsics that should generate a library call. (Those already work correctly since the default operation action is fine.) llvm-svn: 248180
* Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def"James Molloy2015-09-212-5/+2
| | | | | | | | This was committed without the code review (http://reviews.llvm.org/D12937) being approved. This reverts commit r248152. llvm-svn: 248174
* AMDGPU: Move copy handling under switch like other instructionsMatt Arsenault2015-09-211-5/+10
| | | | llvm-svn: 248172
* add ShouldChangeType() variant that takes bitwidthsSanjay Patel2015-09-212-6/+16
| | | | | | This is more efficient for cases like D12965 where we already have widths. llvm-svn: 248170
* DAGCombiner: Replace store of FP constant after attemping store mergesMatt Arsenault2015-09-211-10/+10
| | | | | | | | | If storing multiple FP constants, some subset of the stores would be replaced with integers due to visit order, so MergeConsecutiveStores would only partially merge these. llvm-svn: 248169
* Factor replacement of stores of FP constants into new functionMatt Arsenault2015-09-211-72/+104
| | | | llvm-svn: 248168
* don't repeat function names in comments; NFCSanjay Patel2015-09-211-62/+57
| | | | llvm-svn: 248166
* [Machine Combiner] Refactor machine reassociation code to be target-independent.Chad Rosier2015-09-217-511/+237
| | | | | | | | | | No functional change intended. Patch by Haicheng Wu <haicheng@codeaurora.org>! http://reviews.llvm.org/D12887 PR24522 llvm-svn: 248164
* [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.defArtyom Skrobov2015-09-212-2/+5
| | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following review comments, also updating the description of FeatureDSPThumb2 in ARM.td. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248152
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