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* FastISel - fix uninitialized variable warnings in constructor. NFCI.Simon Pilgrim2019-11-021-1/+2
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* X86AsmPrinter - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-021-2/+2
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* Revert "NoFree argument attribute."Stefan Stipanovic2019-11-023-155/+16
| | | | This reverts commit c12efa2ed0547f7f9f8fba0ad7a76a4cb08bf53a.
* TargetMachine - fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-021-2/+2
| | | | TargetPassConfig::addCoreISelPasses() always initializes O0WantsFastISel but it appeases static analyzers that complain that O0WantsFastISel isn't initialized in the constructor.
* NoFree argument attribute.Stefan Stipanovic2019-11-023-16/+155
| | | | | | | | | | | | Summary: Deducing nofree atrribute for function arguments. Reviewers: jdoerfert Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67886
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-021-1/+1
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* [X86] Move computeZeroableShuffleElements before ↵Simon Pilgrim2019-11-021-87/+87
| | | | | | getTargetShuffleAndZeroables. NFCI. Prep work toward merging some of the functionality.
* Revert BCmp Loop Idiom recognition transform (PR43870)Roman Lebedev2019-11-021-877/+8
| | | | | | | | | | | | | | | | | As discussed in https://bugs.llvm.org/show_bug.cgi?id=43870, this transform is missing a crucial legality check: the old (non-countable) loop would early-return upon first mismatch, but there is no such guarantee for bcmp/memcmp. We'd need to ensure that [PtrA, PtrA+NBytes) and [PtrB, PtrB+NBytes) are fully dereferenceable memory regions. But that would limit the transform to constant loop trip counts and would further cripple it because dereferenceability analysis is *very* partial. Furthermore, even if all that is done, every single test would need to be rewritten from scratch. So let's just give up.
* [Attributor] Ignore BlockAddress users in call site traversalJohannes Doerfert2019-11-021-0/+4
| | | | | | | BlockAddress users will not "call" the function so they do not qualify as call sites in the first place. When we delete a function with BlockAddress users we need to first remove the body so they are properly discarded.
* [X86] Remove FeatureSSE3 from the implies list of HasFastHorizontalOps.Craig Topper2019-11-011-1/+1
| | | | HasFastHorizontalOps is a tuning flag. It shouldn't imply an ISA flag.
* [Attributor][FIX] Do not try to cast if a cast is not requiredJohannes Doerfert2019-11-021-2/+6
| | | | | | | | | When we replace constant returns at the call site we did issue a cast in the hopes it would be a no-op if the types are equal. Turns out that is not the case and we have to check it ourselves first. Reused an IPConstantProp test for coverage. No functional change to the test wrt. IPConstantProp.
* [Attributor][FIX] Transform invoke of nounwind to call + br %normal_destJohannes Doerfert2019-11-021-5/+22
| | | | | | | | | Even if the invoked function may-return, we can replace it with a call and branch if it is nounwind. We had almost everything in place to do this but did not which actually caused a crash when we removed the landingpad from the actually dead unwind block. Exposed by the IPConstantProp tests.
* [Attributor][FIX] Make "known" and "assumed" liveness explicitJohannes Doerfert2019-11-021-21/+43
| | | | | | | | We did merge "known" and "assumed" liveness information into a single set which caused various kinds of problems, especially because we did not properly record when something was actually known. With this patch we properly track the "known" bit and distinguish dead ends we know from the ones we still need to explore in future updates.
* [Attributor] `willreturn` + `noreturn` = UBJohannes Doerfert2019-11-021-4/+1
| | | | | | | | | | | We gave up on `noreturn` if `willreturn` was known for a while but we now again try to always derive `noreturn`. This is useful because a function that is `noreturn` + `willreturn` is basically dead as executing it would lead to undefined behavior (UB). This came up in the IPConstantProp cases where a function only contained a unreachable but was not marked `noreturn` which caused missed opportunities down the line.
* [Attributor][FIX] Make AAValueSimplifyArgument aware of thread-dependent ↵Johannes Doerfert2019-11-021-3/+13
| | | | | | | constants As in IPConstantProp, thread-dependent constants need not be propagated over callbacks. Took the comment and test from there, see also D56447.
* [Attributor][FIX] Handle the default case of a switchJohannes Doerfert2019-11-021-5/+5
| | | | | | In D69605 only the "cases" of a switch were handled but if none matched we did not make the default case life. This is fixed now and properly tested (with code from IPConstantProp/user-with-multiple-uses.ll).
* [Attributor][FIX] Make value simplification aware of "complicated" attributesJohannes Doerfert2019-11-021-0/+18
| | | | | | We cannot simply replace arguments that carry attributes like `nest`, `inalloca`, `sret`, and `byval`. Except for the last one, which we can replace if it is not written, we bail for now.
* [Attributor][NFCI] Avoid unnecessary work except for testingJohannes Doerfert2019-11-021-1/+12
| | | | | | | | Trying to deduce information for declarations and calls sites of declarations is not useful in practice but only for testing. Add a flag that disables this by default but also enable it in the tests. The misc.ll test will verify the flag "works" as expected.
* [Attributor][FIX] NoCapture is not a subsuming propertyJohannes Doerfert2019-11-021-5/+12
| | | | | | We cannot look at the subsuming positions and take their nocapture bit as shown with the two tests for which we derived nocapture on the call site argument and readonly on the argument of the second before.
* [Attributor][NFCI] Remove obsolete codeJohannes Doerfert2019-11-021-24/+0
| | | | | The code in question does not add anything as the class is a subclass of AACallSiteReturnedFromReturnedAndMustBeExecutedContext already.
* [X86] Model MXCSR for MMX FP instructionsPengfei Wang2019-11-011-5/+5
| | | | | | | | | | | | | | | | Summary: This patch models MXCSR and adds flag "mayRaiseFPException" for MMX FP instructions. Reviewers: craig.topper, andrew.w.kaylor, RKSimon, cameron.mcinally Reviewed By: craig.topper Subscribers: hiraditya, llvm-commits, LiuChen3 Tags: #llvm Differential Revision: https://reviews.llvm.org/D69702
* [X86] add mayRaiseFPException flag and FPCW registers for X87 instructionsPengfei Wang2019-11-012-25/+46
| | | | | | | | | | | | | | | | Summary: This patch adds flag "mayRaiseFPException" , FPCW and FPSW for X87 instructions which could raise float exception. Reviewers: pengfei, RKSimon, andrew.w.kaylor, uweigand, kpn, spatel, cameron.mcinally, craig.topper Reviewed By: craig.topper Subscribers: thakis, hiraditya, llvm-commits Patch by LiuChen. Differential Revision: https://reviews.llvm.org/D68854
* [NewPM] Add an SROA pass after loop unrollGuozhi Wei2019-11-011-0/+3
| | | | | | | | | | If there is a small local array accessed in a loop, SROA can't handle memory accesses with variant offset inside a loop, after the loop is fully unrolled, all memory accesses to the array are with fixed offset, so now they can be processed by SROA. But there is no more SROA passes after loop unroll. This patch add an SROA pass after loop unroll to handle this pattern. Differential Revision: https://reviews.llvm.org/D68593
* DebugInfo: Streamline debug_ranges/rnglists/rnglists.dwo emission codeDavid Blaikie2019-11-012-47/+23
| | | | | More code reuse, better basis for modelling debug_loc/loclists/loclists.dwo emission support.
* [TargetLowering] Move the setBooleanContents check on (xor (setcc), (setcc)) ↵Craig Topper2019-11-011-8/+13
| | | | | | | | | | | | | | | | | == / != 1 -> (setcc) != / == (setcc) to the right place We need to be checking the value types for the inner setccs not the outer setcc. We need to ensure those setccs produce a 0/1 value or that the xor is on the i1 type. I think at the time this code was originally written, getBooleanContents didn't take any arguments so this was probably correct. But now we can have a different boolean contents for integer and floating point. Not sure why the other combines below the xor were also checking the boolean contents. None of them involve any setccs other than the outer one and they only produce a new setcc. Differential Revision: https://reviews.llvm.org/D69480
* [MachineBasicBlock] Skip over debug instructions in computeRegisterLiveness ↵Craig Topper2019-11-011-0/+5
| | | | | | | | | | | | before checking for begin If there are debug instructions before the stopping point, we need to skip over them before checking for begin in order to avoid having the debug instructions effect behavior. Fixes PR43758. Differential Revision: https://reviews.llvm.org/D69606
* [amdgpu] Fix known bits compuation on `MUL_I24`/`MUL_U24`.Michael Liao2019-11-011-0/+3
| | | | | | | | | | Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl Tags: #llvm Differential Revision: https://reviews.llvm.org/D69735
* Recommit "[ThinLTO] Handle GUID collision in import global processing""Teresa Johnson2019-11-011-5/+16
| | | | | | | | This recommits cc0b9647b76178bc3869bbfff80535ad86366472 which was reverted in d39d1a2f87aca3cfabe58ecfa5146879baa70096. I added a fix for an issue found when testing via distributed ThinLTO, and added a test case for that failure.
* [WinCFG] Handle constant casts carefully in .gfids emissionReid Kleckner2019-11-011-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The general Function::hasAddressTaken has two issues that make it inappropriate for our purposes: 1. it is sensitive to dead constant users (PR43858 / crbug.com/1019970), leading to different codegen when debu info is enabled 2. it considers direct calls via a function cast to be address escapes The first is fixable, but the second is not, because IPO clients rely on this behavior. They assume this function means that all call sites are analyzable for IPO purposes. So, implement our own analysis, which gets closer to finding functions that may be indirect call targets. Reviewers: ajpaverd, efriedma, hans Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69676
* [X86] Change the behavior of canWidenShuffleElements used by ↵Craig Topper2019-11-011-19/+14
| | | | | | | | | | | lowerV2X128Shuffle to match the behavior in lowerVectorShuffle with regards to zeroable elements. Previously we marked zeroable elements in a way that prevented the widening check from recognizing that it could widen. Now we only mark them zeroable if V2 is an all zeros vector. This matches what we do for widening elements in lowerVectorShuffle. Fixes PR43866.
* [MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off ↵Fangrui Song2019-11-011-0/+1
| | | | builds after D69663
* [X86][AVX] Add support for and/or scalar bool reduction with AVX512 mask ↵Simon Pilgrim2019-11-011-0/+6
| | | | | | registers combineBitcastvxi1 only handles bitcast->MOVMSK combines, with mask registers we use BITCAST directly.
* [WebAssembly] Add experimental SIMD dot product instructionThomas Lively2019-11-011-0/+7
| | | | | | | | | | | | | | | | | | | Summary: This instruction is not merged to the spec proposal, but we need it to be implemented in the toolchain to experiment with it. It is available only on an opt-in basis through a clang builtin. Defined in https://github.com/WebAssembly/simd/pull/127. Depends on D69696. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69697
* Reland "[WebAssembly] Expand setcc of v2i64"Thomas Lively2019-11-012-0/+31
| | | | | | | | This reverts commit e5cae5692b5899631b5bfe5c23234deb5efda10c, which reverted 11850a6305c5778b180243eb06aefe86762dd4ce. The original revert was done because of breakage that was actually in a separate commit, 2ab1b8c1ec452fb743f6cc5051e75a01039cabfe, which was also reverted and has since been fixed and relanded.
* [Support] Use /proc/self/exe for GNU Hurdkristina2019-11-011-1/+1
| | | | | | | | | Use `/proc/self/exe` to get the current executable path on GNU Hurd. Patch by sthibaul (Samuel Thibault) Differential Revision: https://reviews.llvm.org/D69683
* [X86] isFNEG - use switch() instead of if-else tree. NFCI.Simon Pilgrim2019-11-011-33/+36
| | | | In a future patch this will avoid some checks which don't need to be done for some opcodes.
* Revert "[LLD][ThinLTO] Handle GUID collision in import global processing"Teresa Johnson2019-11-011-11/+5
| | | | | | | This reverts commit cc0b9647b76178bc3869bbfff80535ad86366472. The commit is causing a failure in internal testing. Will recommit with a fix later.
* Revert "[AArch64][MachineOutliner] Return address signing for outlined ↵Oliver Stannard2019-11-011-241/+7
| | | | | | | | | | functions" This is causing faults when an instruction which modifies SP is outlined, causing the PAC and AUT instructions to not match. This reverts commits 70caa1fc30c392974df3bccd9959765dae1779f6 and 55314d323738e4a8c1890b6a6e5064e7f4e0da1c.
* [LDV][RAGreedy] Inform LiveDebugVariables about new VRegs added by InlineSpillerBjorn Pettersson2019-11-012-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Make sure RAGreedy informs LiveDebugVariables about new VRegs that is introduced at spill by InlineSpiller. Consider this example LDV: !"var" [48r;128r):0 Loc0=%2 48B %2 = ... ... 128B %7 = ADD %2, ... If %2 is spilled the InlineSpiller will insert spill/reload instructions and introduces some new vregs. So we get 48B %4 = ... 56B spill %4 ... 120B reload %5 128B %3 = ADD %5, ... In the past we did not inform LDV about this, and when reintroducing DBG_VALUE instruction LDV still got information that "var" had the location of the spilled register %2 for the interval [48r;128r). The result was bad, since we mapped "var" to the spill slot even before the spill happened: %4 = ... DBG_VALUE %spill.0, !"var" spill %4 to %spill.0 ... reload %5 %3 = ADD %5, ... This patch will inform LDV about the interval split introduced due to spilling. So the location map in LDV will become !"var" [48r;56r):1 [56r;120r):0 [120r;128r):2 Loc0=%2 Loc1=%4 Loc2=%5 And when inserting DBG_VALUE instructions we get %4 = ... DBG_VALUE %4, !"var" spill %4 to %spill.0 DBG_VALUE %spill.0, !"var" ... reload %5 DBG_VALUE %5, !"var" %3 = ADD %5, ... Fixes: https://bugs.llvm.org/show_bug.cgi?id=38899 Reviewers: jmorse, vsk, aprantl Reviewed By: jmorse Subscribers: dstenb, wuzish, MatzeB, qcolombet, nemanjai, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69584
* [AArch64] Output the pseudo SPACE in asm and object filesMomchil Velikov2019-11-012-2/+12
| | | | | | | | | | | | | | | | Summary: It outputs nothing, but is useful for writing tests, checking asm output. Reviewers: t.p.northover, ostannard, tellenbach Reviewed By: tellenbach Subscribers: tellenbach, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69185 Change-Id: I6b58310e9e5632f0976d2000ce975ee28df90ebe
* [MIPS GlobalISel] Improve reg bank handling in MipsInstructionSelectorPetar Avramovic2019-11-011-58/+70
| | | | | | | | | | Introduce helper methods and refactor pieces of code related to register banks in MipsInstructionSelector. Add a few detailed asserts in order to get a better overview of LLT, register bank combinations that are supported at the moment and reduce need to look at other files. Differential Revision: https://reviews.llvm.org/D69663
* [LegacyPM] Fix pass structure dumpingevgeny2019-11-011-0/+5
| | | | | | | | If module pass uses on-demand function analyses then structure is being displayed incorrectly because FunctionPassManagerImpl can't dump contained FPPassManager instances. Differential revision: https://reviews.llvm.org/D69315
* [AArch64][SVE] Implement several floating-point arithmetic intrinsicsKerry McLaughlin2019-11-012-27/+56
| | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - fabd, fadd, fsub & fsubr - fmul, fmulx, fdiv & fdivr - fmax, fmaxnm, fmin & fminnm - fscale & ftsmul Reviewers: huntergr, sdesmalen, dancgr Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69657
* AMDGPU: Add default denormal mode to MachineFunctionInfoMatt Arsenault2019-11-013-6/+33
| | | | | | The default FP mode should really be a property of a specific function, and not a subtarget. Introduce the necessary fields to the SIMachineFunctionInfo to help move towards this goal.
* [X86] Reland: Enable YMM memcmp with AVX1David Zarzycki2019-11-011-3/+2
| | | | | | | | | | Update TargetTransformInfo to allow AVX1 to use YMM registers for memcmp. This is a follow up to D68632 which enabled XOR compares which made this possible. This also updates the memcmp-optsize.ll test unlike the first patch. https://reviews.llvm.org/D69658
* DAG: Add DAG argument to isFPExtFoldableMatt Arsenault2019-10-313-17/+32
| | | | | For AMDGPU this is dependent on the FP mode, which should eventually not be a property of the subtarget.
* [WebAssembly] SIMD integer min and max instructionsThomas Lively2019-10-311-0/+9
| | | | | | | | | | | | | | | | | | | | | | Summary: Introduces a clang builtins and LLVM intrinsics representing integer min/max instructions. These instructions have not been merged to the SIMD spec proposal yet, so they are currently opt-in only via builtins and not produced by general pattern matching. If these instructions are accepted into the spec proposal the builtins and intrinsics will be replaced with normal pattern matching. Defined in https://github.com/WebAssembly/simd/pull/27. Reviewers: aheejin Reviewed By: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69696
* Reland "[WebAssembly] Handle multiple loads of splatted loads"Thomas Lively2019-10-314-17/+27
| | | | | This reverts commit 92a25fbf11da51c8e3573b81a877d3b226990c07 and fixes the ambiguous method call that was causing build failures.
* Revert "[WebAssembly] Handle multiple loads of splatted loads"Vlad Tsyrklevich2019-10-314-27/+17
| | | | | | | This reverts commit 2ab1b8c1ec452fb743f6cc5051e75a01039cabfe, it is causing build failures on numerous bots, including sanitizer-x86_64-linux-bootstrap-ubsan. My previous revert was for the wrong commit.
* Revert "[WebAssembly] Expand setcc of v2i64"Vlad Tsyrklevich2019-10-312-31/+0
| | | | | | This reverts commit 11850a6305c5778b180243eb06aefe86762dd4ce, it was causing build failures on numerous bots, including sanitizer-x86_64-linux-bootstrap-ubsan.
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