summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-0819-183/+195
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Fix an assymmetry between ConvertScalar_ExtractValue and ↵Cameron Zwarich2011-06-081-3/+4
| | | | | | | | | | ConvertScalar_InsertValue. The former was using the size of the entire alloca, whereas the latter was correctly using the allocated size of the immediate type being converted (which may differ from the size of the alloca). This fixes PR10082. llvm-svn: 132759
* Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of theAkira Hatanaka2011-06-085-31/+64
| | | | | | dynamically allocated stack area was not set. llvm-svn: 132758
* Reorganize code in MipsTargetLowering::LowerCall to improve readability.Akira Hatanaka2011-06-081-38/+36
| | | | llvm-svn: 132756
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
| | | | llvm-svn: 132751
* Fix count.Rafael Espindola2011-06-081-1/+1
| | | | llvm-svn: 132749
* Count how many phis we are creating.Rafael Espindola2011-06-081-0/+2
| | | | llvm-svn: 132748
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-9/+16
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Fix a silly error I introduce in r131951.Rafael Espindola2011-06-071-4/+1
| | | | | | Fixes PR10095. llvm-svn: 132735
* Refactor MipsTargetLowering::EmitInstrWithCustomInserter.Akira Hatanaka2011-06-071-92/+90
| | | | llvm-svn: 132726
* Put back removed line.Akira Hatanaka2011-06-071-0/+1
| | | | llvm-svn: 132725
* Coding style fixes.Akira Hatanaka2011-06-073-44/+31
| | | | | | | | | - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. llvm-svn: 132724
* Use tabs to separate opcode and operand strings.Akira Hatanaka2011-06-071-21/+21
| | | | llvm-svn: 132718
* Add comments for wrapper node patterns in MipsInstrInfo.td.Akira Hatanaka2011-06-071-1/+10
| | | | llvm-svn: 132717
* Make EmitIntValue() work properly on big-endian targets.Roman Divacky2011-06-071-3/+6
| | | | llvm-svn: 132715
* Add test case for C++ exception handling and fix the following mistakes in ↵Akira Hatanaka2011-06-071-30/+60
| | | | | | | | | | | | | | | | | | MipsFrameLowering::emitPrologue: - cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. llvm-svn: 132703
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
| | | | | | | I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. llvm-svn: 132701
* Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.Andrew Trick2011-06-073-5/+5
| | | | | | rdar://problem/9556069 llvm-svn: 132699
* Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen2011-06-061-87/+57
| | | | | | | | | | | | | | | When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. llvm-svn: 132697
* Followup to 132458, omit unnecessary stack copy when x87 input is aStuart Hastings2011-06-062-7/+25
| | | | | | load. rdar://problem/6373334 llvm-svn: 132696
* Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen2011-06-062-23/+52
| | | | | | | | | | | | Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. llvm-svn: 132690
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-063-0/+192
| | | | | | legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. llvm-svn: 132689
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | llvm-svn: 132681
* Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen2011-06-061-11/+6
| | | | | | | | | | | | | | | The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. llvm-svn: 132680
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-061-1/+3
| | | | llvm-svn: 132676
* Use path API for path concatenation.Benjamin Kramer2011-06-051-5/+3
| | | | llvm-svn: 132668
* Basic support for macros with explicit arguments.Rafael Espindola2011-06-052-39/+105
| | | | | | | | | | | We still don't handle * default values * :req * :vararg * \() llvm-svn: 132656
* Produce an undefined reference to _GLOBAL_OFFSET_TABLE_ if we have aRafael Espindola2011-06-051-0/+2
| | | | | | | | | | VK_GOTOFF reloc. This matches as' behavior, but it is not clear why the linker might need this, so I added a FIXME. I could test this by duplicating test/MC/ELF/got.s, but it doesn't look worthwhile. llvm-svn: 132655
* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). llvm-svn: 132649
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
* Refactor parsing of variable names (ie., %foo and @foo) since they have the sameNick Lewycky2011-06-042-50/+46
| | | | | | | rules. Also refactor "read string until quote" into its own function. No functionality change! llvm-svn: 132645
* Add support for @GOTPTOFF in i386 mode.Nick Lewycky2011-06-041-0/+3
| | | | llvm-svn: 132643
* If the block that we're threading through is jumped to by an indirect branch,Bill Wendling2011-06-041-1/+3
| | | | | | | | | | | | then we don't want to set the destination in the indirect branch to the destination. This is because the indirect branch needs its destinations to have had their block addresses taken. This isn't so of the new critical edge that's split during this process. If it turns out that the destination block has only one predecessor, and that being a BB with an indirect branch, then it won't be marked as 'used' and may be removed. PR10072 llvm-svn: 132638
* Reapply r131781, now that the GVN bug with partially-aliasing loadsDan Gohman2011-06-041-1/+11
| | | | | | is disabled. llvm-svn: 132632
* Disable the main feature of 130180, the elimination of loads that areDan Gohman2011-06-041-0/+6
| | | | | | | | | | redundant with partially-aliasing loads. When computing what portion of a clobbering load value is needed, it doesn't consider phi-translation which may have occurred between the clobbing load and the redundant load. llvm-svn: 132631
* Revert r131781 again. Apparently there is more going on here.Dan Gohman2011-06-041-11/+1
| | | | llvm-svn: 132625
* Fold assert-only-used variable into the assert.Nick Lewycky2011-06-041-2/+1
| | | | llvm-svn: 132620
* Missing include of climits in the new BranchProbability pass.Andrew Trick2011-06-041-0/+1
| | | | llvm-svn: 132616
* New BranchProbabilityInfo analysis. Patch by Jakub Staszak!Andrew Trick2011-06-043-0/+350
| | | | | | | | | | | BranchProbabilityInfo provides an interface for IR passes to query the likelihood that control follows a CFG edge. This patch provides an initial implementation of static branch predication that will populate BranchProbabilityInfo for branches with no external profile information using very simple heuristics. It currently isn't hooked up to any external profile data, so static prediction does all the work. llvm-svn: 132613
* Reapply r131781 (revert r131809), now that some BasicAA shortcomingsDan Gohman2011-06-041-1/+11
| | | | | | it exposed are fixed. llvm-svn: 132611
* Fix BasicAA's recursion detection so that it doesn't pessimizeDan Gohman2011-06-041-37/+27
| | | | | | | | | queries in the case of a DAG, where a query reaches a node visited earlier, but it's not on a cycle. This avoids MayAlias results in cases where BasicAA is expected to return MustAlias or PartialAlias in order to protect TBAA. llvm-svn: 132609
* Reapply 132424 with fixes. This fixes PR10068.Stuart Hastings2011-06-035-6/+128
| | | | | | rdar://problem/5993888 llvm-svn: 132606
* Blackfin always uses a reserved call frame.Jakob Stoklund Olesen2011-06-033-2/+7
| | | | | | | Materializing the stack pointer update before a call requires a scratch register that may not be available. llvm-svn: 132601
* Another possible bug. Stopgap until we can autogenerate tables andEric Christopher2011-06-031-6/+3
| | | | | | | | constraint lengths. Part of rdar://9037836 and rdar://9119939 llvm-svn: 132598
* Fix an off by one error.Eric Christopher2011-06-031-2/+1
| | | | | | Part of rdar://9037836 and rdar://9119939 llvm-svn: 132590
* Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen2011-06-035-22/+18
| | | | | | | | | of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
* Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen2011-06-031-2/+14
| | | | | | | | Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. llvm-svn: 132580
* When merging MustAlias and PartialAlias, chose PartialAlias insteadDan Gohman2011-06-031-10/+21
| | | | | | of conservatively choosing MayAlias. llvm-svn: 132579
* Use IRBuilder, preserve line numbers.Devang Patel2011-06-031-4/+6
| | | | llvm-svn: 132578
* Make the Uv constraint a memory operand. This doesn't solve theEric Christopher2011-06-031-0/+3
| | | | | | | | addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 llvm-svn: 132561
OpenPOWER on IntegriCloud