summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm ↵Jakob Stoklund Olesen2009-07-161-8/+12
| | | | | | | | | | | operands. The inline asm operands must be parsed from the first flag, you cannot assume that an immediate operand preceeding a register use operand is the flag. PowerPC "m" operands are represented as (flag, imm, reg) triples. isRegTiedToDefOperand() would incorrectly interpret the imm as the flag. llvm-svn: 76101
* Changed my mind. We now allow remat of instructions whose defs have subreg ↵Evan Cheng2009-07-162-6/+8
| | | | | | indices. llvm-svn: 76100
* Privatize the ConstantFP table. I'm on a roll!Owen Anderson2009-07-166-75/+74
| | | | llvm-svn: 76097
* With recent MC changes, RIP base register is explicitly modeled. Make sure ↵Evan Cheng2009-07-161-7/+9
| | | | | | we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. llvm-svn: 76094
* Update CMake file.Ted Kremenek2009-07-161-0/+1
| | | | llvm-svn: 76093
* Move the ConstantInt uniquing table into LLVMContextImpl. This exposed a ↵Owen Anderson2009-07-1629-85/+165
| | | | | | | | number of issues in our current context-passing stuff, which is also fixed here llvm-svn: 76089
* Removed the SubsectionsViaSymbols MCStreamer API and replaced it with a genericKevin Enderby2009-07-161-3/+6
| | | | | | | EmitAssemblerFlag API which takes a value from the added AssemblerFlag enumerated constants. llvm-svn: 76087
* Fill in some holes in ScalarEvolution's loop iteration conditionDan Gohman2009-07-161-2/+27
| | | | | | | analysis. This allows indvars to emit a simpler loop trip count expression. llvm-svn: 76085
* Add an isLoopSimplifyForm() predicate, following the example ofDan Gohman2009-07-161-0/+24
| | | | | | | isLCSSAForm(), to test whether a loop is in the form guaranteed by the LoopSimplify pass. llvm-svn: 76077
* Use size_t.Dan Gohman2009-07-162-13/+13
| | | | llvm-svn: 76069
* UnbreakAnton Korobeynikov2009-07-1611-56/+122
| | | | llvm-svn: 76064
* Temporary disable 16 bit bswapAnton Korobeynikov2009-07-161-3/+4
| | | | llvm-svn: 76063
* Add instruction formats and few opcodesAnton Korobeynikov2009-07-162-983/+705
| | | | llvm-svn: 76062
* Add bswap patternsAnton Korobeynikov2009-07-161-0/+18
| | | | llvm-svn: 76061
* Provide crazy pseudos for regpairs spills / reloadsAnton Korobeynikov2009-07-162-2/+47
| | | | llvm-svn: 76060
* Handle long-disp stuff more consistentlyAnton Korobeynikov2009-07-163-7/+31
| | | | llvm-svn: 76059
* All FP instructions have 12 bit memory displacement fieldAnton Korobeynikov2009-07-161-34/+34
| | | | llvm-svn: 76058
* Another predicate routineAnton Korobeynikov2009-07-162-0/+31
| | | | llvm-svn: 76057
* More helpersAnton Korobeynikov2009-07-162-0/+66
| | | | llvm-svn: 76056
* Add bunch of branch folding stuffAnton Korobeynikov2009-07-163-1/+187
| | | | llvm-svn: 76055
* Add missed opcodes to short => long displacement conversionAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 76054
* CleanupAnton Korobeynikov2009-07-161-91/+29
| | | | llvm-svn: 76053
* Fix logic inversion for RI-mode address selectionAnton Korobeynikov2009-07-161-1/+1
| | | | llvm-svn: 76052
* Expand 32-bit bitconverts via memoryAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76050
* Fix incomin arg stack frame offset in case we need to generate stack frameAnton Korobeynikov2009-07-161-1/+1
| | | | llvm-svn: 76049
* Fix instruction mnemonics for some fp_to_sint operationsAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76048
* i32 values are passed extended also on stack. Handle this in generic wayAnton Korobeynikov2009-07-161-23/+24
| | | | llvm-svn: 76047
* We definitely have 1-0 boolsAnton Korobeynikov2009-07-161-0/+1
| | | | llvm-svn: 76046
* Revert the commit, it just hides the real bugAnton Korobeynikov2009-07-161-1/+2
| | | | llvm-svn: 76045
* Out GR128 regclass is not a 'real' i128 one.Anton Korobeynikov2009-07-163-5/+4
| | | | llvm-svn: 76044
* Add missed condbranch opcodesAnton Korobeynikov2009-07-161-5/+29
| | | | llvm-svn: 76043
* Handle bitconvertsAnton Korobeynikov2009-07-163-4/+16
| | | | llvm-svn: 76042
* Unbreak mvi and friends - emit only 'significant' part of the operandAnton Korobeynikov2009-07-162-6/+17
| | | | llvm-svn: 76041
* Expand fp_to_uint tooAnton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 76040
* We don't have FP truncstoresAnton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 76039
* Expand uint_to_fpAnton Korobeynikov2009-07-161-0/+2
| | | | llvm-svn: 76038
* Emit proper rounding mode for fp_to_sintAnton Korobeynikov2009-07-161-4/+4
| | | | llvm-svn: 76037
* f32/f64 regs are stored on stack if we're short in FP regsAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 76036
* Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension ↵Anton Korobeynikov2009-07-161-2/+1
| | | | | | side effects llvm-svn: 76035
* Make FP zero to be legal FP immediate via LOAD ZEROAnton Korobeynikov2009-07-162-0/+48
| | | | llvm-svn: 76034
* Loads are not two-address in any wayAnton Korobeynikov2009-07-161-8/+7
| | | | llvm-svn: 76033
* Add LOAD NEGATIVE instructionAnton Korobeynikov2009-07-161-1/+9
| | | | llvm-svn: 76032
* LOAD COMPLEMENT instruction is not really two-addrAnton Korobeynikov2009-07-161-4/+5
| | | | llvm-svn: 76031
* Add multiple add/sub instructionsAnton Korobeynikov2009-07-161-0/+40
| | | | llvm-svn: 76030
* Handle FP callee-saved regsAnton Korobeynikov2009-07-163-51/+102
| | | | llvm-svn: 76029
* Proper FP extloadsAnton Korobeynikov2009-07-162-7/+9
| | | | llvm-svn: 76028
* Add proper PWS impdef'sAnton Korobeynikov2009-07-162-21/+51
| | | | llvm-svn: 76027
* Propagate FP select_cc to dag insertersAnton Korobeynikov2009-07-162-2/+19
| | | | llvm-svn: 76026
* Implement fp_to_sintAnton Korobeynikov2009-07-161-1/+14
| | | | llvm-svn: 76025
* Implement FP regs spills / restoresAnton Korobeynikov2009-07-161-0/+14
| | | | llvm-svn: 76024
OpenPOWER on IntegriCloud