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* [PM/LCG] Follow-up fix to r308088 to handle deletion of libraryChandler Carruth2017-07-192-2/+7
| | | | | | | | | | | | | | | | | | | | | | | functions. In the prior commit, we provide ordering to the LCG between functions and library function definitions that they might begin to call through transformations. But we still would delete these library functions from the call graph if they became dead during inlining. While this immediately crashed, it also exposed a loss of information. We shouldn't remove definitions of library functions that can still usefully participate in the LCG-powered CGSCC optimization process. If new call edges are formed, we want to have definitions to be called. We can still remove these functions if truly dead using global-dce, etc, but removing them during the CGSCC walk is premature. This fixes a crash in the new PM when optimizing some unusual libraries that end up with "internal" lib functions such as the code in the "R" language's libraries. llvm-svn: 308417
* [SPARC] Add missing variable initialization after r308343.James Y Knight2017-07-191-0/+1
| | | | llvm-svn: 308415
* AMD znver1 Initial Scheduler modelCraig Topper2017-07-193-4/+226
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds the following 1. Adds a skeleton scheduler model for AMD Znver1. 2. Introduces the znver1 execution units and pipes. 3. Caters the instructions based on the generic scheduler classes. 4. Further additions to the scheduler model with instruction itineraries will be carried out incrementally based on a. Instructions types b. Registers used 5. Since itineraries are not added based on instructions, throughput information are bound to change when incremental changes are added. 6. Scheduler testcases are modified accordingly to suit the new model. Patch by Ganesh Gopalasubramanian. With minor formatting tweaks from me. Reviewers: craig.topper, RKSimon Subscribers: javed.absar, shivaram, ddibyend, vprasad Differential Revision: https://reviews.llvm.org/D35293 llvm-svn: 308411
* Object: preserve more information about DEF fileSaleem Abdulrasool2017-07-191-4/+8
| | | | | | | | | | | | Preserve the actual library name as provided by the user. This is required to properly replicate link's behaviour about the module import name handling. This requires an associated change to lld for updating the tests for the proper behaviour for the import library module name handling in various cases. Associated tests will be part of the lld change. llvm-svn: 308406
* Fix DebugLoc propagation for unreachable LoadInstWeiming Zhao2017-07-192-2/+4
| | | | | | | | | | | | | | Summary: Currently, when GVN creates a load and when InstCombine creates a new store for unreachable Load, the DebugLoc info gets lost. Reviewers: dberlin, davide, aprantl Reviewed By: aprantl Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D34639 llvm-svn: 308404
* Debug Info: Add a file: field to DIImportedEntity.Adrian Prantl2017-07-198-27/+45
| | | | | | | | | | | | | | | | | | | | | | | DIImportedEntity has a line number, but not a file field. To determine the decl_line/decl_file we combine the line number from the DIImportedEntity with the file from the DIImportedEntity's scope. This does not work correctly when the parent scope is a DINamespace or a DIModule, both of which do not have a source file. This patch adds a file field to DIImportedEntity to unambiguously identify the source location of the using/import declaration. Most testcase updates are mechanical, the interesting one is the removal of the FIXME in test/DebugInfo/Generic/namespace.ll. This fixes PR33822. See https://bugs.llvm.org/show_bug.cgi?id=33822 for more context. <rdar://problem/33357889> https://bugs.llvm.org/show_bug.cgi?id=33822 Differential Revision: https://reviews.llvm.org/D35583 llvm-svn: 308398
* [AArch64] Adjust the feature set for Exynos M2Evandro Menezes2017-07-181-0/+1
| | | | | | Add fusion of AES operations. llvm-svn: 308388
* [asan] Copy arguments passed by value into explicit allocas for ASanVitaly Buka2017-07-181-0/+38
| | | | | | | | | | | | | | | | | | | | | Summary: ASan determines the stack layout from alloca instructions. Since arguments marked as "byval" do not have an explicit alloca instruction, ASan does not produce red zones for them. This commit produces an explicit alloca instruction and copies the byval argument into the allocated memory so that red zones are produced. Submitted on behalf of @morehouse (Matt Morehouse) Reviewers: eugenis, vitalybuka Reviewed By: eugenis Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D34789 llvm-svn: 308387
* Object: rename parameter from DLLName to ImportNameSaleem Abdulrasool2017-07-181-16/+16
| | | | | | | | | | When I originally wrote this code, I neglected the fact that the import library may be created for executables. This name is not the name of the DLL, but rather the name for the imported module. It will be embedded into the IAT/ILT reference. Rename it to make it more obvious. NFC. llvm-svn: 308384
* Object: handle extensions properly in def filesSaleem Abdulrasool2017-07-181-3/+3
| | | | | | | | | | | | When given an extension as part of the `library` directive in a def file, the extension is preserved/honoured by link/lib. Behave similarly when parsing the def file. This requires checking if a native extension is provided as a keyword parameter. If no extension is present, append a standard `.dll` or `.exe` extension. This is best tested via lld, and I will add tests there as a follow up. llvm-svn: 308383
* llvm: add llvm-dlltool support to the archiverMartell Malone2017-07-1810-23/+341
| | | | | | | | | | | | | | | | A PE COFF spec compliant import library generator. Intended to be used with mingw-w64. Supports: PE COFF spec (section 8, Import Library Format) PE COFF spec (Aux Format 3: Weak Externals) Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D29892 This reapplies rL308329, which was reverted in rL308374 llvm-svn: 308379
* [RuntimeDyld][MachO/ARM] Don't add a redundant relocation entry.Lang Hames2017-07-181-1/+0
| | | | | | We only need to add this entry once for it to be fixed up. llvm-svn: 308375
* Revert r308329: llvm: add llvm-dlltool support to the archiverRui Ueyama2017-07-1810-341/+23
| | | | | | This reverts commit r308329 because it broke buildbots. llvm-svn: 308374
* llvm: fix -Wcast gcc warn error from rL308329Martell Malone2017-07-181-6/+3
| | | | llvm-svn: 308360
* [COFF, ARM64] Reserve X18 register by defaultMandeep Singh Grang2017-07-181-1/+2
| | | | | | | | | | | | Reviewers: compnerd, rnk, ruiu, mstorsjo Reviewed By: mstorsjo Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35531 llvm-svn: 308358
* [DAG] Improve Aliasing of operations to static allocaNirav Dave2017-07-181-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-recommiting after landing DAG extension-crash fix. Recommiting after adding check to avoid miscomputing alias information on addresses of the same base but different subindices. Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 308350
* [DAG] Reverse node replacement in extension operation. NFCI.Nirav Dave2017-07-181-12/+20
| | | | | | | | Reorder replacements to be user first in preparation for multi-level folding to premptively avoid inadvertantly deleting later nodes from sharing found from replacement. llvm-svn: 308348
* [Sparc] Added software multiplication/division featureJames Y Knight2017-07-184-1/+23
| | | | | | | | | | | Added a feature to the Sparc back-end that replaces the integer multiply and divide instructions with calls to .mul/.sdiv/.udiv. This is a step towards having full v7 support. Patch by: Eric Kedaigle Differential Revision: https://reviews.llvm.org/D35500 llvm-svn: 308343
* [libFuzzer] when adding a reduced input print REDUCED instead of NEWKostya Serebryany2017-07-183-5/+8
| | | | llvm-svn: 308336
* [DAG] Avoid deleting nodes before combining them.Nirav Dave2017-07-181-7/+26
| | | | | | | | | | | | | | | | | | When replacing a node and it's operand, replacing the operand node may cause the deletion of the original node leading to an assertion failure. Case around these replacements to avoid this without relying on inspecting the DELETED_NODE opcode in various extend dagcombiner cases. Fixes PR32515. Reviewers: dbabokin, RKSimon, davide, chandlerc Subscribers: chandlerc, llvm-commits Differential Revision: https://reviews.llvm.org/D34095 llvm-svn: 308330
* llvm: add llvm-dlltool support to the archiverMartell Malone2017-07-1810-23/+344
| | | | | | | | | | | | | | | A PE COFF spec compliant import library generator. Intended to be used with mingw-w64. Supports: PE COFF spec (section 8, Import Library Format) PE COFF spec (Aux Format 3: Weak Externals) Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D29892 llvm-svn: 308329
* AMDGPU: Annotate necessity of flat-scratch-initMatt Arsenault2017-07-183-11/+28
| | | | | | | | As an approximation of the existing handling to avoid regressions. Fixes using too many registers with calls on subtargets with the SGPR allocation bug. llvm-svn: 308326
* AMDGPU: Figure out private memory regs after loweringMatt Arsenault2017-07-187-33/+75
| | | | | | | | | | | | | | | | | | Introduce pseudo-registers for registers needed for stack access, which are replaced during finalizeLowering. Note these pseudo-registers are currently only used for the used register location, and not for determining their input argument register. This is better because it avoids the need to try to predict whether a call will be emitted from the IR, and also detects stack objects introduced by legalization. Test changes are from the HasStackObjects check being more accurate since stack objects introduced during legalization are now known. llvm-svn: 308325
* [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 2)Geoff Berry2017-07-183-2/+652
| | | | | | | | | | | | | | Summary: Avoid HW prefetcher instruction tag collisions in loops by inserting MOVs to change the base address register of strided loads. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D35366 llvm-svn: 308324
* [x86, CGP] increase memcmp() expansion up to 4 load pairsSimon Pilgrim2017-07-181-4/+5
| | | | | | | | | | | | | | | | | | | | | It should be a win to avoid going out to the system lib for all small memcmp() calls using scalar ops. For x86 32-bit, this means most everything up to 16 bytes. For 64-bit, that doubles because we can do 8-byte loads. Notes: Reduced from 4 to 2 loads for -Os behavior, which might not be optimal in all cases. It's effectively a question of how much do we trust the system implementation. Linux and macOS (and Windows I assume, but did not test) have optimized memcmp() code for x86, so it's probably not bad either way? PPC is using 8/4 for defaults on these. We do not expand at all for -Oz. There are still potential improvements to make for the CGP expansion IR and/or lowering such as avoiding select-of-constants (D34904) and not doing zexts to the max load type before doing a compare. We have special-case SSE/AVX codegen for (memcmp(x, y, 16/32) == 0) that will no longer be produced after this patch. I've shown the experimental justification for that change in PR33329: https://bugs.llvm.org/show_bug.cgi?id=33329#c12 TLDR: While the vector code is a likely winner, we can't guarantee that it's a winner in all cases on all CPUs, so I'm willing to sacrifice it for the greater good of expanding all small memcmp(). If we want to resurrect that codegen, it can be done by adjusting the CGP params or poking a hole to let those fall-through the CGP expansion. Committed on behalf of Sanjay Patel Differential Revision: https://reviews.llvm.org/D35067 llvm-svn: 308322
* [TRE] Simplify canTRE() a bit using all_of(). NFCI.Davide Italiano2017-07-181-10/+5
| | | | | | | This has a ~11 years old FIXME, which may not be true today. We might consider removing this code altogether. llvm-svn: 308319
* [Hexagon] Emit lookup tables in text section based on a flagSumanth Gundapaneni2017-07-182-0/+53
| | | | | | | | The flag "-hexagon-emit-lut-text" (defaulted to false) is added to decide on where to keep the switch generated lookup table. Differential Revision: https://reviews.llvm.org/D34818 llvm-svn: 308316
* AMDGPU: Fix crash when folding immediates into multiple usesNicolai Haehnle2017-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When an immediate is folded by constant folding, we re-scan the entire use list for two reasons: 1. The constant folding may have created a new use of the same reg. 2. The constant folding may have removed an additional use in the list we're currently traversing (e.g., constant folding an S_ADD_I32 c, c). However, this could previously lead to a crash when an unrelated use was added twice into the FoldList. Since we re-scan the whole list anyway, we might as well just clear the FoldList again before we do so. Using a MIR test to show this because real code seems to trigger the issue only in connection with some really subtle control flow structures. Fixes GL45-CTS.shading_language_420pack.binding_images on gfx9. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D35416 llvm-svn: 308314
* [DAG] Allow base element type of store merge type to also be a vector.Nirav Dave2017-07-181-1/+6
| | | | | | Correctly calculate merged vector size if MemVT is already a vector. llvm-svn: 308312
* [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if ↵Sam Kolton2017-07-186-17/+35
| | | | | | omod is supported for VOP3 instructions llvm-svn: 308310
* [globalisel][tablegen] Enable the import of rules involving fma.Daniel Sanders2017-07-181-1/+1
| | | | | | | | | | | | | | | | Summary: G_FMA was recently added to GlobalISel which enables the import of rules involving fma. Add the mapping to allow it. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35130 llvm-svn: 308308
* fix formatting issue; NFCHiroshi Inoue2017-07-181-4/+6
| | | | llvm-svn: 308305
* [AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8Dmitry Preobrazhensky2017-07-183-1/+9
| | | | | | | | | | See Bug 33639: https://bugs.llvm.org//show_bug.cgi?id=33639 Reviewers: vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D34892 llvm-svn: 308303
* [DAGCombine] Fix issue with out of bound constant rotation (PR33828)Simon Pilgrim2017-07-181-1/+10
| | | | | | Take the modulo of rotations by a constant greater than or equal to the bit-width llvm-svn: 308302
* [mips] Alter register classes for MSA pseudo f16 instructionsStefan Maksimovic2017-07-182-4/+32
| | | | | | | | | | | This change introduces additional machine instructions in functions dealing with the expansion of msa pseudo f16 instructions due to register classes being inappropriate when checked with machine verifier. Differential Revision: https://reviews.llvm.org/D34276 llvm-svn: 308301
* PSCEV] Create AddRec for Phis in cases of possible integer overflow,Dorit Nuzman2017-07-181-13/+372
| | | | | | | | | | | | | using runtime checks Extend the SCEVPredicateRewriter to work a bit harder when it encounters an UnknownSCEV for a Phi node; Try to build an AddRecurrence also for Phi nodes whose update chain involves casts that can be ignored under the proper runtime overflow test. This is one step towards addressing PR30654. Differential revision: http://reviews.llvm.org/D30041 llvm-svn: 308299
* [sancov] Fix PR33732Alexander Potapenko2017-07-181-0/+10
| | | | | | | | Coverage hooks that take less-than-64-bit-integers as parameters need the zeroext parameter attribute (http://llvm.org/docs/LangRef.html#paramattrs) to make sure they are properly extended by the x86_64 ABI. llvm-svn: 308296
* [AMDGPU][MC] Optimized IsRegIntersect functionDmitry Preobrazhensky2017-07-181-16/+2
| | | | | | | | | | | | Optimized IsRegIntersect by using MCRegAliasIterator See Bug 33800: https://bugs.llvm.org//show_bug.cgi?id=33800 Reviewers: arsenm, artem.tamazov Differential Revision: https://reviews.llvm.org/D35452 llvm-svn: 308294
* [libOption] - Replace std::pair with helper struct. NFC.George Rimar2017-07-181-12/+13
| | | | | | Splitted from D35476. llvm-svn: 308293
* [ARM|CodeGen] Improve the code in FastISelJaved Absar2017-07-181-23/+20
| | | | | | | | | | Cleaned up the code in FastISel a bit. Had to add make_range to MCInstrDesc as that was needed and seems missing. Reviewed by: @t.p.northover Differential Revision: https://reviews.llvm.org/D35494 llvm-svn: 308291
* [ARM] GlobalISel: Support G_(S|U)REM for s8 and s16Diana Picus2017-07-181-2/+4
| | | | | | | Widen to s32, and then do whatever Lowering/Custom/Libcall action the subtarget wants. llvm-svn: 308285
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A73.Florian Hahn2017-07-181-1/+3
| | | | | | | | | | | | | | | | Summary: Using 16 byte alignment is beneficial on Cortex-A73, similar to Cortex-A72 (added in D34961). Reviewers: mcrosier, t.p.northover, aadg, silviu.baranga Reviewed By: t.p.northover Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35493 llvm-svn: 308283
* [AMDGPU][MC] Added missing VOP3P opcodesDmitry Preobrazhensky2017-07-181-1/+9
| | | | | | | | | | | | | | | Added support of the following opcodes: v_pk_sub_u16 v_pk_mad_i16 v_pk_mad_u16 See Bug 33593: https://bugs.llvm.org//show_bug.cgi?id=33593 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D34890 llvm-svn: 308281
* [SystemZ, AsmParser] Enable the mnemonic spell corrector.Jonas Paulsson2017-07-181-2/+13
| | | | | | | | This enables the suggestions of other mnemonics when invalid ones are specified. Review: Ulrich Weigand llvm-svn: 308280
* GlobalISel: Support G_(S|U)REM widening in LegalizerHelperDiana Picus2017-07-181-0/+3
| | | | | | | | Treat widening G_SREM and G_UREM the same as G_SDIV and G_UDIV. This is going to be used in the ARM backend (and that's when the test will come too). llvm-svn: 308278
* Normalize constructor call syntax, NFCI.Serge Guelton2017-07-181-1/+1
| | | | llvm-svn: 308275
* Revert r308025 due to uncovering a crash in SelectionDAG. This is filedChandler Carruth2017-07-181-16/+6
| | | | | | | | | with a minimal test case in http://llvm.org/PR33833. Original commit message: Improve Aliasing of operations to static alloca llvm-svn: 308271
* Revert r308179 which causes tablegen to spam stderr on every build.Chandler Carruth2017-07-186-34/+17
| | | | | | | Original commit log: [AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions llvm-svn: 308270
* [X86] Prevent an assertion failure if a gather intrinsic is passed a ↵Craig Topper2017-07-181-4/+16
| | | | | | | | | | non-constant scale value. This isn't legal code, but we shouldn't crash on it. Now we just don't convert the gather intrinsic if the scale isn't constant and let it go through to isel where we'll report an isel failure. Fixes PR33772. llvm-svn: 308267
* [CGP] Cleanup - remove redundant code in OptimizeMemoryInst. NFCSerguei Katkov2017-07-181-35/+12
| | | | | | | | | | | | | | | | | | optimizeMemoryInst contains a vector AddrModeInsts. The only use of this vector is to check that all instructions are in the same block as memory instruction. This check is guarded by PhiSeen flag, so if we traversed through phi node then we do not need to keep information in AddrModeInsts. AddModeInsts is set first time we found some addressing mode and updated if we found new one later. We can find next addressing mode only if we traverse phi node so all code related to update of AddModeInsts can be safely removed. Reviewers: loladiro, spatel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35291 llvm-svn: 308265
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