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* [Power9] Add __float128 support in the backend for bitcast to a i128Stefan Pintilie2018-10-233-0/+68
| | | | | | | | | Add support to allow bit-casting from f128 to i128 and then extracting 64 bits from the result. Differential Revision: https://reviews.llvm.org/D49507 llvm-svn: 345053
* [IR] remove fake binop queries for not/negSanjay Patel2018-10-231-39/+0
| | | | | | | | | | | | | | | | | | | | | | | The initial motivation is that we want to remove the fneg API because that would silently fail if we add an actual fneg instruction to IR. The same would be true for the integer ops, so we might as well get rid of these too. We have a newer 'match' API that makes checking for these patterns simpler. It also works with vectors that may include undef elements in constants. If any out-of-tree users need updating, they can model their code changes on these commits: rL345050 rL345043 rL345042 rL345041 rL345036 rL345030 llvm-svn: 345052
* [InstCombine] use 'match' to simplify codeSanjay Patel2018-10-231-1/+1
| | | | | | | | | | | | There's probably some vector-with-undef-element pattern that shows an improvement, so this is probably not quite 'NFC'. This is the last step towards removing the fake binop queries for not/neg. Ie, there are no more uses of those functions in trunk. Fneg should follow. llvm-svn: 345050
* [TTI][X86] Treat SK_Transpose shuffles as SK_PermuteTwoSrc - there's no ↵Simon Pilgrim2018-10-231-0/+4
| | | | | | difference in lowering. llvm-svn: 345048
* [DebugInfo][GlobalOpt] Fix -debugify for globalopt shrinking globals to ↵Jordan Rupprecht2018-10-231-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | booleans. Summary: TryToShrinkGlobalToBoolean, when possible, will split store <value> + load <value> into store <bool> + select <bool ? value : 0>. This preserves DebugLoc during that pass. Fixes PR37959. The test case here is the simplified .ll for: ``` static int foo; int bar() { foo = 5; return foo; } ``` Reviewers: dblaikie, gbedwell, aprantl Reviewed By: dblaikie Subscribers: mehdi_amini, JDevlieghere, dexonsmith, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D53531 llvm-svn: 345046
* [WebAssembly] use 'match' to simplify code; NFCSanjay Patel2018-10-231-2/+6
| | | | | | | | Vector types are not possible here because this code explicitly checks for a scalar type, but this is another step towards completely removing the fake binop queries for not/neg/fneg. llvm-svn: 345043
* [Reassociate] replace fake binop queries with 'match' APISanjay Patel2018-10-231-18/+16
| | | | | | | | | | | | | | | | | We need to update this code before introducing an 'fneg' instruction in IR, so we might as well kill off the integer neg/not queries too. This is no-functional-change-intended for scalar code and most vector code. For vectors, we can see that the 'match' API allows for undef elements in constants, so we optimize those cases better. Ideally, there would be a test for each code diff, but I don't see evidence of that for the existing code, so I didn't try very hard to come up with new vector tests for each code change. Differential Revision: https://reviews.llvm.org/D53533 llvm-svn: 345042
* [SelectionDAG] use 'match' to simplify code; NFCSanjay Patel2018-10-231-8/+8
| | | | | | | | | Vector types are not possible here because this code only starts matching from the scalar bool value of a conditional branch, but this is another step towards completely removing the fake binop queries for not/neg/fneg. llvm-svn: 345041
* [LegalizeDAG] Remove unused variableBenjamin Kramer2018-10-231-2/+0
| | | | llvm-svn: 345040
* [LegalizeDAG] Share Vector/Scalar CTTZ ExpansionSimon Pilgrim2018-10-233-47/+64
| | | | | | | | | | As suggested on D53258, this patch demonstrates sharing common CTTZ expansion code between VectorLegalizer and SelectionDAGLegalize by putting it in TargetLowering. I intend to move CTLZ and (scalar) CTPOP over as well and then update D53258 accordingly. Differential Revision: https://reviews.llvm.org/D53474 llvm-svn: 345039
* [SLPVectorizer] Add basic support for mul/and/or/xor horizontal reductionsSimon Pilgrim2018-10-231-2/+5
| | | | | | | | | | | | Expand arithmetic reduction to include mul/and/or/xor instructions. This patch just fixes the SLPVectorizer - the effective reduction costs for AVX1+ are still poor (see rL344846) and will need to be improved before SLP sees this as a valid transform - but we can already see the effect on SSE2 tests. This partially helps PR37731, but doesn't fix it all as it still falls over on the extraction/reduction order for some reason. Differential Revision: https://reviews.llvm.org/D53473 llvm-svn: 345037
* [InstCombine] use 'match' to handle vectors and simplify codeSanjay Patel2018-10-231-2/+3
| | | | | | | This is another step towards completely removing the fake binop queries for not/neg/fneg. llvm-svn: 345036
* [InstCombine] swap select profile metadata when swapping select opsSanjay Patel2018-10-231-0/+1
| | | | llvm-svn: 345034
* Revert "[MachinePipeliner] Split MachinePipeliner code into header and cpp ↵Aleksandr Urakov2018-10-231-7/+598
| | | | | | | | | files" This reverts commit 40760b733d9eef841c897338af5e9d81b12551bf. It seems that the commit is a cuse of the build failure. llvm-svn: 345032
* [SLSR] use 'match' to simplify code; NFCSanjay Patel2018-10-231-4/+5
| | | | | | | | | This pass could probably be modified slightly to allow vector splat transforms for practically no cost, but it only works on scalars for now. So the use of the newer 'match' API should make no functional difference. llvm-svn: 345030
* Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << ↵Roman Lebedev2018-10-232-56/+74
| | | | | | | | | | | | | | | | (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
* Leftover bits from https://reviews.llvm.org/D53420 that were accidentally leftDorit Nuzman2018-10-231-2/+1
| | | | | | out of revision 344883 llvm-svn: 345021
* [X86][SSE] Update raw mask shuffle decoders to handle UNDEF mask eltsSimon Pilgrim2018-10-233-60/+59
| | | | | | | | Matches the approach taken in the constant pool shuffle decoders, and uses an UndefElts mask instead of uint64_t(-1) raw mask values, which doesn't work safely for i32/i64 shuffle mask sizes (as the -1 value is legal). This allows us to remove the constant pool shuffle decoders from most of the getTargetShuffleMask variable shuffle cases (X86ISD::VPERMV3 will be handled in a future commit). llvm-svn: 345018
* Revert "[X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 ↵Roman Lebedev2018-10-232-67/+50
| | | | | | | | | | | | | | | | | | | | - y) pattern" *Seems* to be breaking sanitizer-x86_64-linux-fast buildbot, the ELF/relocatable-versioned.s test: ==17758==MemorySanitizer CHECK failed: /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_allocator.cc:191 "((kBlockMagic)) == ((((u64*)addr)[0]))" (0x6a6cb03abcebc041, 0x0) #0 0x59716b in MsanCheckFailed(char const*, int, char const*, unsigned long long, unsigned long long) /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/msan/msan.cc:393 #1 0x586635 in __sanitizer::CheckFailed(char const*, int, char const*, unsigned long long, unsigned long long) /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_termination.cc:79 #2 0x57d5ff in __sanitizer::InternalFree(void*, __sanitizer::SizeClassAllocatorLocalCache<__sanitizer::SizeClassAllocator32<__sanitizer::AP32> >*) /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_allocator.cc:191 #3 0x7fc21b24193f (/lib/x86_64-linux-gnu/libc.so.6+0x3593f) #4 0x7fc21b241999 in exit (/lib/x86_64-linux-gnu/libc.so.6+0x35999) #5 0x7fc21b22c2e7 in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x202e7) #6 0x57c039 in _start (/b/sanitizer-x86_64-linux-fast/build/llvm_build_msan/bin/lld+0x57c039) This reverts commit r345014. llvm-svn: 345017
* [TTI] Add generic cost handling of SK_Reverse shufflesSimon Pilgrim2018-10-231-0/+2
| | | | | | | | These can be treated as a general permute. This required a fix for missing reverse patterns on ARM llvm-svn: 345015
* [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) patternRoman Lebedev2018-10-232-50/+67
| | | | | | | | | | | | | | | | | | Summary: Continuation of D52348. We also get the `c) x & (-1 >> (32 - y))` pattern here, because of the D48768. I will add extra-uses into those tests and follow-up with a patch to handle those patterns too. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345014
* Revert "Revert "[PDB] Extend IPDBSession's interface to retrieve frame data""Aleksandr Urakov2018-10-236-0/+118
| | | | | | This reverts commit 466ce67d6ec444962e5cc0136243c16a453190c0. llvm-svn: 345010
* [MachinePipeliner] Split MachinePipeliner code into header and cpp filesLama Saba2018-10-231-598/+7
| | | | | | | | Split MachinePipeliner code into header and cpp files to allow inheritance from SwingSchedulerDAG Differential Revision: https://reviews.llvm.org/D53477 llvm-svn: 345008
* Add support for GNU Hurd in Path.inc and other placesSylvestre Ledru2018-10-231-3/+8
| | | | | | | | | | | | | | Summary: Patch by Svante Signell & myself Reviewers: rnk, JDevlieghere, efriedma Reviewed By: efriedma Subscribers: efriedma, JDevlieghere, krytarowski, llvm-commits, kristina Differential Revision: https://reviews.llvm.org/D53409 llvm-svn: 345007
* [RuntimeDyld][COFF] Skip non-loaded sections when calculating ImageBase.Lang Hames2018-10-231-1/+7
| | | | | | | | | | | | | | | | | | Non-loaded sections (whose unused load-address defaults to zero) should not be taken into account when calculating ImageBase, or ImageBase will be incorrectly set to 0. Patch by Andrew Scheidecker. Thanks Andrew! https://reviews.llvm.org/D51343 + // The Sections list may contain sections that weren't loaded for + // whatever reason: they may be debug sections, and ProcessAllSections + // is false, or they may be sections that contain 0 bytes. If the + // section isn't loaded, the load address will be 0, and it should not + // be included in the ImageBase calculation. llvm-svn: 344995
* [ORC] Show JITDylib search order in JITDylib::dump.Lang Hames2018-10-231-0/+4
| | | | | | This can be helpful in debugging search-order related failures. llvm-svn: 344994
* [ORC] Dump flags for JITDylib symbol table entries.Lang Hames2018-10-231-2/+2
| | | | | | This can help when debugging flag-specific symbol table issues. llvm-svn: 344993
* [hwasan] add stack frame descriptions.Kostya Serebryany2018-10-231-1/+75
| | | | | | | | | | | | | | | | | | | Summary: At compile-time, create an array of {PC,HumanReadableStackFrameDescription} for every function that has an instrumented frame, and pass this array to the run-time at the module-init time. Similar to how we handle pc-table in SanitizerCoverage. The run-time is dummy, will add the actual logic in later commits. Reviewers: morehouse, eugenis Reviewed By: eugenis Subscribers: srhines, llvm-commits, kubamracek Differential Revision: https://reviews.llvm.org/D53227 llvm-svn: 344985
* [WebAssembly] Fix assembly printing of br_tableHeejin Ahn2018-10-231-2/+2
| | | | | | | | | | | | Summary: In `br_table's stack version asm string, \t was missing. Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53516 llvm-svn: 344981
* X86: fix a comment copy-paste issue (NFC)Saleem Abdulrasool2018-10-221-1/+1
| | | | | | The comment was copy-pasted but not updated. NFC. llvm-svn: 344973
* [X86] Remove unused entries from the X86ProcFamily enum. Add a note to ↵Craig Topper2018-10-222-28/+2
| | | | | | | | discourage creation of new enum entries. As we've learned multiple times, a coarse grained enum like this is not scalable and we should be migrating away from it. llvm-svn: 344972
* [Intrinsic] Unigned Saturation Addition IntrinsicLeonard Chan2018-10-2210-42/+70
| | | | | | | | | | | | Add an intrinsic that takes 2 integers and perform unsigned saturation addition on them. This is a part of implementing fixed point arithmetic in clang where some of the more complex operations will be implemented as intrinsics. Differential Revision: https://reviews.llvm.org/D53340 llvm-svn: 344971
* X86: Do not optimize branches with undef eflags inputsMatthias Braun2018-10-221-0/+5
| | | | | | | | | | | | analyzeBranch()/insertBranch() etc. do not properly deal with an undef flag on the eflags input and used to produce invalid MIR. I don't see this ever affecting real world inputs (I don't think it is possible to produce undef flags with llvm IR), so I simply changed the code to bail out in this case. rdar://42122367 llvm-svn: 344970
* [MC] Shrink MCAsmParser by grouping bools, add const, NFCReid Kleckner2018-10-221-1/+1
| | | | | | | | | | | | I was considering adding another boolean here. I standardized on bools since they allow default member initializers in the class definition. This makes ShowParsedOperands protected instead of private, but that's probably fine. Reduce the SmallVector size while we're at it, since the common case is that there is never a pending error. llvm-svn: 344967
* Recommit r344877 "[X86] Stop promoting integer loads to vXi64"Craig Topper2018-10-2210-522/+633
| | | | | | | | | | | | | | | | | | | | | | | | I've included a fix to DAGCombiner::ForwardStoreValueToDirectLoad that I believe will prevent the previous miscompile. Original commit message: Theoretically this was done to simplify the amount of isel patterns that were needed. But it also meant a substantial number of our isel patterns have to match an explicit bitcast. By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to change the load type to rem I had to add some additional plain load instruction patterns and a few other special cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like this promotion was hurting us more than helping. I still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems to relate to using getTargetConstantFromNode on a load that was shrunk due to an extract_subvector combine after the constant pool entry was created. So we end up decoding more mask elements than the lo I'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor promotion. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits, RKSimon Differential Revision: https://reviews.llvm.org/D53306 llvm-svn: 344965
* [WebAssembly][NFC] Remove WebAssemblyStackifier TableGen backendThomas Lively2018-10-225-32/+36
| | | | | | | | | | | | | | | | Summary: Replace its functionality with a TableGen InstrInfo relational instruction mapping. Although arguably more complex than the TableGen backend, the relational mapping is a smaller maintenance burden than a TableGen backend. Reviewers: aardappel, aheejin, dschuff Subscribers: mgorny, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53307 llvm-svn: 344962
* [DWARF] Use a function-local offset for AT_call_return_pcVedant Kumar2018-10-225-9/+38
| | | | | | | | | | | | | | | | | | | Logs provided by @stella.stamenova indicate that on Linux, lldb adds a spurious slide offset to the return PC it loads from AT_call_return_pc attributes (see the list thread: "[PATCH] D50478: Add support for artificial tail call frames"). This patch side-steps the issue by getting rid of the load address calculation in lldb's CallEdge::GetReturnPCAddress. The idea is to have the DWARF writer emit function-local offsets to the instruction after a call. I.e. return-pc = label-after-call-insn - function-entry. LLDB can simply add this offset to the base address of a function to get the return PC. Differential Revision: https://reviews.llvm.org/D53469 llvm-svn: 344960
* [Reassociate] add 'using namespace' to reduce bloat; NFCSanjay Patel2018-10-221-3/+4
| | | | llvm-svn: 344959
* [ORC] Guard access to the MemMgrs vector in RTDyldObjectLinkingLayer.Lang Hames2018-10-221-3/+10
| | | | | | | | | Otherwise we can end up with a data-race when linking concurrently. This should fix an intermittent failure in the multiple-compile-threads-basic.ll testcase. llvm-svn: 344956
* X86: add alias for pushfw/popfw in Intel modeTim Northover2018-10-221-0/+4
| | | | | | | | | A while ago we changed pushf and popf in Intel mode to generate pushfq and popfq. Unfortunately that left us with no way to get the 16-bit encoding in Intel mode so this patch adds pushfw and popfw as aliases there. llvm-svn: 344949
* Reapply "[MachineCopyPropagation] Reimplement CopyTracker in terms of ↵Justin Bogner2018-10-221-58/+69
| | | | | | | | | | | | | | | | | | | register units" Recommits r342942, which was reverted in r343189, with a fix for an issue where we would propagate unsafely if we defined only the upper part of a register. Original message: Change the copy tracker to keep a single map of register units instead of 3 maps of registers. This gives a very significant compile time performance improvement to the pass. I measured a 30-40% decrease in time spent in MCP on x86 and AArch64 and much more significant improvements on out of tree targets with more registers. llvm-svn: 344942
* [hot-cold-split] Add opt remark on successTeresa Johnson2018-10-221-0/+8
| | | | | | | | | | | | Summary: Emit optimization remark on successful hot cold split. Reviewers: sebpop, hiraditya Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53512 llvm-svn: 344938
* Revert rL344931 from llvm/trunk: [X86][SSE] getTargetShuffleMaskIndices - ↵Simon Pilgrim2018-10-221-9/+10
| | | | | | | | | | allow opt-in support for whole undef shuffle mask elements We can't safely assume that certain RawMask entries are UNDEF as most variable shuffles ignore non-index bits - PSHUFB only works on i8 elts so it'd be safe to use but I'm intending to come up with an alternative approach that works for all. ........ Enable this for PSHUFB constant mask decoding and remove the ConstantPool DecodePSHUFBMask llvm-svn: 344937
* Revert rL344933 from llvm/trunk: [X86][SSE] Tidyup DecodeVPERMILPMask ↵Simon Pilgrim2018-10-222-5/+5
| | | | | | | | | | shuffle mask decoding We can't safely assume that certain RawMask entries are UNDEF as most variable shuffles ignore non-index bits. ........ Add support for UNDEF raw mask elements and remove the ConstantPool DecodeVPERMILPMask usage in X86ISelLowering.cpp llvm-svn: 344936
* Revert r344930 as it broke some of the bots on Windows.Aaron Ballman2018-10-222-92/+79
| | | | | | http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/739 llvm-svn: 344935
* [X86][SSE] Tidyup DecodeVPERMILPMask shuffle mask decodingSimon Pilgrim2018-10-222-5/+5
| | | | | | Add support for UNDEF raw mask elements and remove the ConstantPool DecodeVPERMILPMask usage in X86ISelLowering.cpp llvm-svn: 344933
* [X86][SSE] getTargetShuffleMaskIndices - allow opt-in support for whole ↵Simon Pilgrim2018-10-221-10/+9
| | | | | | | | undef shuffle mask elements Enable this for PSHUFB constant mask decoding and remove the ConstantPool DecodePSHUFBMask llvm-svn: 344931
* [SourceMgr][FileCheck] Obey -color by extending WithColorJoel E. Denny2018-10-222-79/+92
| | | | | | | | | | | | | | | | | | | | | | While this change specifically targets FileCheck, it affects any tool using the same SourceMgr facilities. Previously, -color was documented in FileCheck's -help output, but -color had no effect. Now, -color obeys its documentation: it forces colors to be used in FileCheck diagnostics even when stderr is not a terminal. -color is especially helpful when combined with FileCheck's -v, which can produce a long series of diagnostics that you might wish to pipe to a pager, such as less -R. The WithColor extensions here will also help to clean up color usage in FileCheck's annotated dump of input, which is proposed in D52999. Reviewed By: JDevlieghere Differential Revision: https://reviews.llvm.org/D53419 llvm-svn: 344930
* [X86] getTargetConstantBitsFromNode - handle extraction from larger constant ↵Simon Pilgrim2018-10-221-2/+3
| | | | | | | | pool entries First step towards removing X86ShuffleDecodeConstantPool usage from X86ISelLowering.cpp llvm-svn: 344924
* Revert r344877 "[X86] Stop promoting integer loads to vXi64"Craig Topper2018-10-229-631/+521
| | | | | | Sam McCall reported miscompiles in some tensorflow code. Reverting while I try to figure out. llvm-svn: 344921
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