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* [x86 frame lowering] In 32-bit mode, use ESI as the base pointer.Chad Rosier2012-07-311-2/+4
| | | | | | | Previously, we were using EBX, but PIC requires the GOT to be in EBX before function calls via PLT GOT pointer. llvm-svn: 161066
* Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka2012-07-313-38/+17
| | | | | | | | | single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. llvm-svn: 161063
* MachineSink: Sort the successors before trying to find SuccToSinkTo.Manman Ren2012-07-311-2/+15
| | | | | | | | | | One motivating example is to sink an instruction from a basic block which has two successors: one outside the loop, the other inside the loop. We should try to sink the instruction outside the loop. rdar://11980766 llvm-svn: 161062
* Conform to LLVM coding style.Micah Villmow2012-07-311-2/+2
| | | | llvm-svn: 161061
* Don't generate ordered or unordered comparison operations if it is not legal ↵Micah Villmow2012-07-311-1/+2
| | | | | | to do so. llvm-svn: 161053
* Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove ↵Craig Topper2012-07-311-5/+4
| | | | | | trailing whitespace. llvm-svn: 161029
* Tidy up trailing whitespaceCraig Topper2012-07-311-33/+33
| | | | llvm-svn: 161027
* Tidy up trailing whitespaceCraig Topper2012-07-311-12/+12
| | | | llvm-svn: 161026
* Clear kill flags in removeCopyByCommutingDef().Jakob Stoklund Olesen2012-07-311-0/+2
| | | | | | | | | We are extending live ranges, so kill flags are not accurate. They aren't needed until they are recomputed after RA anyway. <rdar://problem/11950722> llvm-svn: 161023
* Reverse order of the two branches at end of a basic block if it is profitable.Manman Ren2012-07-311-1/+15
| | | | | | | | | | | | | | | We branch to the successor with higher edge weight first. Convert from je LBB4_8 --> to outer loop jmp LBB4_14 --> to inner loop to jne LBB4_14 jmp LBB4_8 PR12750 rdar: 11393714 llvm-svn: 161018
* Use the latest MachineRegisterInfo APIs. No functionality.Andrew Trick2012-07-301-1/+1
| | | | llvm-svn: 161010
* Inline MachineRegisterInfo::hasOneUseAndrew Trick2012-07-301-7/+0
| | | | llvm-svn: 161007
* Avoid looking at stale data in verifyAnalysis().Jakob Stoklund Olesen2012-07-301-1/+4
| | | | llvm-svn: 161004
* Allow traces to enter nested loops.Jakob Stoklund Olesen2012-07-301-14/+29
| | | | | | | | | | | This lets traces include the final iteration of a nested loop above the center block, and the first iteration of a nested loop below the center block. We still don't allow traces to contain backedges, and traces are truncated where they would leave a loop, as seen from the center block. llvm-svn: 161003
* Keep empty assembly macro argument values in the middle of the list.Jim Grosbach2012-07-301-2/+8
| | | | | | | | | | | | | | | | | | | Empty macro arguments at the end of the list should be as-if not specified at all, but those in the middle of the list need to be kept so as not to screw up the positional numbering. E.g.: .macro foo foo_-bash___: nop .endm foo 1, 2, 3, 4 foo 1, , 3, 4 Should create two labels, "foo_1_2_3_4" and "foo_1__3_4". rdar://11948769 llvm-svn: 161002
* Clarify invalidation strategy in comment.Jakob Stoklund Olesen2012-07-301-0/+6
| | | | llvm-svn: 160997
* Assert that all trace candidate blocks have been visited by the PO.Jakob Stoklund Olesen2012-07-301-11/+6
| | | | | | | | | | When computing a trace, all the candidates for pred/succ must have been visited. Filter out back-edges first, though. The PO traversal ignores them. Thanks to Andy for spotting this in review. llvm-svn: 160995
* Hook into PassManager's analysis verification.Jakob Stoklund Olesen2012-07-303-7/+4
| | | | | | | By overriding Pass::verifyAnalysis(), the pass contents will be verified by the pass manager. llvm-svn: 160994
* Consider address spaces for hashing and CSEing DAG nodes. Otherwise two ↵Pete Cooper2012-07-301-0/+22
| | | | | | loads from different x86 segments but the same address would get CSEd llvm-svn: 160987
* Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cppKevin Enderby2012-07-301-2/+9
| | | | | | | | | where the other_half of the movt and movw relocation entries needs to get set and only with the 16 bits of the other half. rdar://10038370 llvm-svn: 160978
* Add MachineInstr::isTransient().Jakob Stoklund Olesen2012-07-301-23/+1
| | | | | | | | | | | This is a cleaned up version of the isFree() function in MachineTraceMetrics.cpp. Transient instructions are very unlikely to produce any code in the final output. Either because they get eliminated by RegisterCoalescing, or because they are pseudo-instructions like labels and debug values. llvm-svn: 160977
* Add MachineTraceMetrics::verify().Jakob Stoklund Olesen2012-07-303-11/+55
| | | | | | | This function verifies the consistency of cached data in the MachineTraceMetrics analysis. llvm-svn: 160976
* Verify that the CFG hasn't changed during invalidate().Jakob Stoklund Olesen2012-07-301-2/+12
| | | | | | | The MachineTraceMetrics analysis must be invalidated before modifying the CFG. This will catch some of the violations of that rule. llvm-svn: 160969
* Add MachineBasicBlock::isPredecessor().Jakob Stoklund Olesen2012-07-301-2/+5
| | | | | | | | A->isPredecessor(B) is the same as B->isSuccessor(A), but it can tolerate a B that is null or dangling. This shouldn't happen normally, but it it useful for verification code. llvm-svn: 160968
* When constant folding GEP expressions, keep the address space information of ↵Nadav Rotem2012-07-301-3/+19
| | | | | | | | pointers. Together with Ran Chachick <ran.chachick@intel.com> llvm-svn: 160954
* Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoadCraig Topper2012-07-301-0/+6
| | | | llvm-svn: 160953
* Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The ↵Craig Topper2012-07-301-0/+2
| | | | | | isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. llvm-svn: 160951
* Give VCVTTPD2DQ priority over CVTTPD2DQ.Craig Topper2012-07-301-10/+10
| | | | llvm-svn: 160942
* Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.Craig Topper2012-07-303-43/+46
| | | | llvm-svn: 160941
* Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. ↵Craig Topper2012-07-301-9/+10
| | | | | | Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern. llvm-svn: 160939
* Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert ↵Craig Topper2012-07-291-26/+41
| | | | | | instruction patterns. llvm-svn: 160938
* Move more SSE/AVX convert instruction patterns into their definitions.Craig Topper2012-07-291-70/+50
| | | | llvm-svn: 160937
* Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren2012-07-293-99/+0
| | | | llvm-svn: 160927
* Fold patterns for some of the SSE/AVX convert instructions into their ↵Craig Topper2012-07-281-49/+34
| | | | | | instruction definitions. llvm-svn: 160922
* Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects.Craig Topper2012-07-281-22/+23
| | | | llvm-svn: 160921
* X86 Peephole: fold loads to the source register operand if possible.Manman Ren2012-07-283-0/+99
| | | | | | | | | Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 llvm-svn: 160919
* Make CVTSS2SI instruction definition consistent with CVTSD2SI.Craig Topper2012-07-281-34/+14
| | | | llvm-svn: 160914
* Fix up memory load types for SSE scalar convert intrinsic patterns.Craig Topper2012-07-281-27/+26
| | | | llvm-svn: 160913
* X86 Peephole: fix PR13475 in optimizeCompare.Manman Ren2012-07-281-3/+7
| | | | | | | | It is possible that an instruction can use and update EFLAGS. When checking the safety, we should check the usage of EFLAGS first before declaring it is safe to optimize due to the update. llvm-svn: 160912
* Reenable a basic SSA DAG builder optimization.Andrew Trick2012-07-281-5/+4
| | | | | | Jakob fixed ProcessImplicifDefs in r159149. llvm-svn: 160910
* Add more debug output to MachineTraceMetrics.Jakob Stoklund Olesen2012-07-273-3/+48
| | | | llvm-svn: 160905
* Keep track of the head and tail of the trace through each block.Jakob Stoklund Olesen2012-07-272-4/+18
| | | | | | | This makes it possible to quickly detect blocks that are outside the trace. llvm-svn: 160904
* Add a DW_AT_high_pc for CUs that are a single address range. UpdateEric Christopher2012-07-272-6/+24
| | | | | | | | | | all tests accordingly. Fixes PR13351. Patch by shinichiro hamaji! llvm-svn: 160899
* Also compute register mask lists under -new-live-intervals.Jakob Stoklund Olesen2012-07-271-8/+34
| | | | llvm-svn: 160898
* Typos.Chad Rosier2012-07-271-1/+1
| | | | llvm-svn: 160897
* Teach CodeGenPrep to look past bitcast when it's duplicating return instructionEvan Cheng2012-07-272-7/+34
| | | | | | | | into predecessor blocks to enable tail call optimization. rdar://11958338 llvm-svn: 160894
* Eliminate the IS_PHI_DEF flag and VNInfo::setIsPHIDef().Jakob Stoklund Olesen2012-07-274-8/+2
| | | | | | | | A value number is a PHI def if and only if it begins at a block boundary. This can be derived from the def slot, a separate flag is not necessary. llvm-svn: 160893
* Add a -new-live-intervals experimental option.Jakob Stoklund Olesen2012-07-271-1/+36
| | | | | | | | | This option replaces the existing live interval computation with one based on LiveRangeCalc.cpp. The new algorithm does not depend on LiveVariables, and it can be run at any time, before or after leaving SSA form. llvm-svn: 160892
* Fixing problems with X86_64_32 relocations and making the assertions more ↵Andrew Kaylor2012-07-271-5/+4
| | | | | | readable. llvm-svn: 160889
* Add <imp-def> of super-register when lowering SUBREG_TO_REG.Jakob Stoklund Olesen2012-07-271-4/+7
| | | | | | Patch by Tyler Nowicki! llvm-svn: 160888
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