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* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-194-17/+25
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* Remove isSubroutineType test for isCompositeType, getTag() is enough.Yaron Keren2014-12-191-1/+1
| | | | llvm-svn: 224621
* Add printing the LC_SUB_CLIENT load command with llvm-objdump’s ↵Kevin Enderby2014-12-191-0/+5
| | | | | | -private-headers. llvm-svn: 224616
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-196-161/+13
| | | | llvm-svn: 224612
* merge consecutive stores of extracted vector elementsSanjay Patel2014-12-191-4/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a path to DAGCombiner::MergeConsecutiveStores() to combine multiple scalar stores when the store operands are extracted vector elements. This is a partial fix for PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 ). For the new test case, codegen improves from: vmovss %xmm0, (%rdi) vextractps $1, %xmm0, 4(%rdi) vextractps $2, %xmm0, 8(%rdi) vextractps $3, %xmm0, 12(%rdi) vextractf128 $1, %ymm0, %xmm0 vmovss %xmm0, 16(%rdi) vextractps $1, %xmm0, 20(%rdi) vextractps $2, %xmm0, 24(%rdi) vextractps $3, %xmm0, 28(%rdi) vzeroupper retq To: vmovups %ymm0, (%rdi) vzeroupper retq Patch reviewed by Nadav Rotem. Differential Revision: http://reviews.llvm.org/D6698 llvm-svn: 224611
* [Hexagon] Adding bit extraction and table indexing instructions.Colin LeMahieu2014-12-191-0/+101
| | | | llvm-svn: 224610
* [Hexagon] Adding bit insertion instructions.Colin LeMahieu2014-12-191-0/+65
| | | | llvm-svn: 224609
* [Hexagon] Adding more xtype shift instructions.Colin LeMahieu2014-12-191-0/+107
| | | | llvm-svn: 224608
* Add printing the LC_SUB_LIBRARY load command with llvm-objdump’s ↵Kevin Enderby2014-12-191-0/+5
| | | | | | -private-headers. llvm-svn: 224607
* [Hexagon] Adding xtype shift instructions.Colin LeMahieu2014-12-191-0/+198
| | | | llvm-svn: 224604
* [Hexagon] Adding transfers to and from control registers.Colin LeMahieu2014-12-192-0/+65
| | | | llvm-svn: 224599
* [Hexagon] Adding doubleregs for control registers. Renaming control ↵Colin LeMahieu2014-12-194-22/+66
| | | | | | register class. llvm-svn: 224598
* [DebugInfo] Move all DWARF headers to the public include directory.Frederic Riss2014-12-1932-1608/+26
| | | | | | | | | | dsymutil needs access to DWARF specific inforamtion, the small DIContext wrapper isn't sufficient. Other DWARF consumers might want to use it too (I'm looking at you lldb). Differential Revision: http://reviews.llvm.org/D6694 llvm-svn: 224594
* [BBVectorize] Remove two more redundant assignments.Tilmann Scheller2014-12-191-2/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224590
* [BBVectorize] Remove redundant assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224589
* Reapply: [InstCombine] Fix visitSwitchInst to use right operand types for ↵Bruno Cardoso Lopes2014-12-191-3/+10
| | | | | | | | | | | | | | | | | | sub cstexpr The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. Also, fix code to also return the modified switch when only the truncation is performed. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224588
* [LoopVectorize] Remove redundant assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224587
* [ARM] Remove dead assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224586
* use -0.0 when creating an fneg instructionSanjay Patel2014-12-191-1/+1
| | | | | | | | | | | | | | | | | | | Backends recognize (-0.0 - X) as the canonical form for fneg and produce better code. Eg, ppc64 with 0.0: lis r2, ha16(LCPI0_0) lfs f0, lo16(LCPI0_0)(r2) fsubs f1, f0, f1 blr vs. -0.0: fneg f1, f1 blr Differential Revision: http://reviews.llvm.org/D6723 llvm-svn: 224583
* Revert "[InstCombine] Fix visitSwitchInst to use right operand types for sub ↵Bruno Cardoso Lopes2014-12-191-4/+2
| | | | | | | | | | | | | cstexpr" Reverts commit r224574 to appease buildbots: The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. llvm-svn: 224576
* [InstCombine] Fix visitSwitchInst to use right operand types for sub cstexprBruno Cardoso Lopes2014-12-191-2/+4
| | | | | | | | | | | | | The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224574
* Remove redundant assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found with the Clang static analyzer. llvm-svn: 224570
* Rename MapValue(Metadata*) to MapMetadata()Duncan P. N. Exon Smith2014-12-194-21/+21
| | | | | | | | Instead of reusing the name `MapValue()` when mapping `Metadata`, use `MapMetadata()`. The old name doesn't make much sense after the `Metadata`/`Value` split. llvm-svn: 224566
* [Object] Don't crash on empty export lists.Juergen Ributzka2014-12-191-1/+4
| | | | | | | | | | | | Summary: This fixes the exports iterator if the export list is empty. Reviewers: Bigcheese, kledzik Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6732 llvm-svn: 224563
* RegisterCoalescer: rewrite eliminateUndefCopy().Matthias Braun2014-12-191-29/+64
| | | | | | | | This also fixes problems with undef copies of subregisters. I can't attach a testcase for that as none of the targets in trunk has subregister liveness tracking enabled. llvm-svn: 224560
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-196-37/+138
| | | | llvm-svn: 224556
* Explain why LLVM is emitting a DW_AT_containing_type inside of a class.Adrian Prantl2014-12-191-0/+2
| | | | llvm-svn: 224555
* ConstantFold: Shifting undef by zero results in undefDavid Majnemer2014-12-181-0/+9
| | | | llvm-svn: 224553
* Reverting 224550, was not ready for commit.Colin LeMahieu2014-12-186-134/+33
| | | | llvm-svn: 224552
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-186-33/+134
| | | | llvm-svn: 224550
* Add printing the LC_SUB_UMBRELLA load command with llvm-objdump’s ↵Kevin Enderby2014-12-181-0/+5
| | | | | | -private-headers. llvm-svn: 224548
* Instead of explicitely comparing both lowercase and uppercase variants.Roman Divacky2014-12-181-81/+1
| | | | | | | | | | .lower() the Name and compare only the lowecase. Removing 81 compares/lines of code. This changes the accepted string to be mixed lower/upper case but it should be ok. Discussed with Jim Grosbach. llvm-svn: 224547
* fix formatting; NFCSanjay Patel2014-12-181-8/+4
| | | | llvm-svn: 224542
* LiveIntervalAnalysis: Cleanup computeDeadValuesMatthias Braun2014-12-181-24/+33
| | | | | | | | | - This also fixes a bug introduced in r223880 where values were not correctly marked as Dead anymore. - Cleanup computeDeadValues(): split up SubRange code variant, simplify arguments. llvm-svn: 224538
* Add printing the LC_SUB_FRAMEWORK load command with llvm-objdump’s ↵Kevin Enderby2014-12-181-0/+4
| | | | | | -private-headers. llvm-svn: 224534
* Add missing implementation of 'sys::path::is_other' to the support library.Juergen Ributzka2014-12-181-0/+8
| | | | | | | The header claims that this function exists, but the linker wasn't too happy about it not being in the library. llvm-svn: 224527
* [mips][microMIPS] Fix bugs related to atomic SC/LL instructionsJozef Kolek2014-12-181-4/+8
| | | | | | | | | Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic operations the mips32r2 encoding was emitted instead of microMIPS. Differential Revision: http://reviews.llvm.org/D6659 llvm-svn: 224524
* ARM: fix an off-by-one in the register list accessSaleem Abdulrasool2014-12-181-2/+2
| | | | | | | | | Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
* [AVX512] Enable FP arithmetic lowering for AVX512VL subsets.Robert Khasanov2014-12-184-2/+105
| | | | | | | Added RegOp2MemOpTable4 to transform 4th operand from register to memory in merge-masked versions of instructions. Added lowering tests. llvm-svn: 224516
* [Msan] Generalize instrumentation code to support FreeBSD mappingViktor Kutuzov2014-12-181-27/+106
| | | | | | Differential Revision: http://reviews.llvm.org/D6666 llvm-svn: 224514
* Fix Visual C++ error "'llvm::make_unique' : ambiguous call to overloaded ↵Yaron Keren2014-12-181-2/+2
| | | | | | function". llvm-svn: 224506
* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-181-15/+76
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* [SROA] Cleanup - remove the use of std::mem_fun_ref nonsense and useChandler Carruth2014-12-181-1/+3
| | | | | | a lambda now that we have them. llvm-svn: 224500
* Modernize the getStreamedBitcodeModule interface a bit. NFC.Rafael Espindola2014-12-181-18/+14
| | | | llvm-svn: 224499
* [PowerPC] Use MCPhysReg for tables of registers. Const-correct the tables. ↵Craig Topper2014-12-181-12/+12
| | | | | | Only put the anonymous namespace around classes. NFC. llvm-svn: 224498
* [X86] Use correct opsize on indirect call and jump aliases.Craig Topper2014-12-181-4/+4
| | | | llvm-svn: 224497
* [X86] Don't use PS prefix on LDMXCSR/STMXCSR.Craig Topper2014-12-181-6/+8
| | | | | | Near as I can tell prefixes are ignored on these instructions except for a comment in the Intel docs about 0xf3. Binutils disassembler seems to ignore prefixes on these instructions. Our disassembler still doesn't distinguish PS and "no prefix" well enough for this to make a functional change, but it helps with experiments I'm doing on a potential new disassembler table builder. llvm-svn: 224496
* [X86] Remove unnecessary 'In64BitMode' predicate for instructions that ↵Craig Topper2014-12-181-14/+11
| | | | | | already indicate use of REX.W. llvm-svn: 224495
* Add a corresponding '@LOCAL' parse to match r224415.Justin Hibbits2014-12-181-0/+1
| | | | | | Pointed out by Jim Grosbach. llvm-svn: 224494
* Add a new string member to the TargetOptions struct for the nameEric Christopher2014-12-186-61/+84
| | | | | | | | | | | | | of the abi we should be using. For targets that don't use the option there's no change, otherwise this allows external users to set the ABI via string and avoid some of the -backend-option pain in clang. Use this option to move the ABI for the ARM port from the Subtarget to the TargetMachine and update the testcases accordingly since it's no longer valid to set via -mattr. llvm-svn: 224492
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