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* While inlining, clone llvm.dbg.func.start intrinsic and adjust Devang Patel2009-04-152-3/+52
| | | | | | llvm.dbg.region.end instrinsic. This nested llvm.dbg.func.start/llvm.dbg.region.end pair now enables DW_TAG_inlined_subroutine support in code generator. llvm-svn: 69118
* Construct and emit DW_TAG_inlined_subroutine DIEs for inlined subroutine ↵Devang Patel2009-04-153-91/+217
| | | | | | scopes (only in FastISel mode). llvm-svn: 69116
* Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble withDan Gohman2009-04-151-0/+35
| | | | | | the local register allocator. llvm-svn: 69115
* Add a method to check that the subprogram holds debug info for the given ↵Devang Patel2009-04-151-0/+13
| | | | | | Function or not. llvm-svn: 69113
* Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it whenDan Gohman2009-04-152-5/+20
| | | | | | | | either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. llvm-svn: 69111
* GR8_NOREX can contain the H registers, since they don't requireDan Gohman2009-04-151-2/+3
| | | | | | REX prefixes. llvm-svn: 69108
* Optimize conditional branch on i1 phis with non-constant inputs.Evan Cheng2009-04-141-14/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This turns: eq: %3 = icmp eq i32 %1, %2 br label %join ne: %4 = icmp ne i32 %1, %2 br label %join join: %5 = phi i1 [%3, %eq], [%4, %ne] br i1 %5, label %yes, label %no => eq: %3 = icmp eq i32 %1, %2 br i1 %3, label %yes, label %no ne: %4 = icmp ne i32 %1, %2 br i1 %4, label %yes, label %no llvm-svn: 69102
* For the h-register addressing-mode trick, use the correct value forDan Gohman2009-04-141-1/+14
| | | | | | any non-address uses of the address value. This fixes 186.crafty. llvm-svn: 69094
* Mac OS X 10.6 and above do not use key manager to register EH frames.Evan Cheng2009-04-141-2/+8
| | | | llvm-svn: 69090
* When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REGDan Gohman2009-04-141-20/+19
| | | | | | | | | | | | operator is used by a CopyToReg to export the value to a different block, don't reuse the CopyToReg's register for the subreg operation result if the register isn't precisely the right class for the subreg operation. Also, rename the h-registers.ll test, now that there are more than one. llvm-svn: 69087
* Call CreateProcess with bInheritHandles = TRUE.Mikhail Glushenkov2009-04-141-1/+1
| | | | | | | | Makes llvmc show error messages printed by child processes when run from the Cygwin/MSYS shell. Since ExecuteAndWait does not return until the child program has finished execution, this change should be harmless. llvm-svn: 69082
* Delete trailing whitespace.Mikhail Glushenkov2009-04-141-13/+13
| | | | llvm-svn: 69081
* Some of GR8_NOREX registers are only available in 64-bit mode.Evan Cheng2009-04-141-0/+48
| | | | llvm-svn: 69049
* Handle aggregate type arguments to direct and indirect calls.Sanjiv Gupta2009-04-144-35/+101
| | | | llvm-svn: 69022
* LoopIndexSplit needs to inform the loop pass manager of the instructions it isOwen Anderson2009-04-141-0/+1
| | | | | | deleting, not just the basic block. llvm-svn: 69011
* Do not force asm's to be chained if they don't touchDale Johannesen2009-04-141-0/+3
| | | | | | | memory and aren't volatile. This was interfering with good scheduling. llvm-svn: 69008
* Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and ↵Evan Cheng2009-04-141-9/+13
| | | | | | IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side. llvm-svn: 69006
* Make these errors more noticable in build logs.Daniel Dunbar2009-04-131-5/+5
| | | | llvm-svn: 68998
* Change SelectionDAG type legalization to allow BUILD_VECTOR operands to beBob Wilson2009-04-135-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | promoted to legal types without changing the type of the vector. This is following a suggestion from Duncan (http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/019923.html). The transformation that used to be done during type legalization is now postponed to DAG legalization. This allows the BUILD_VECTORs to be optimized and potentially handled specially by target-specific code. It turns out that this is also consistent with an optimization done by the DAG combiner: a BUILD_VECTOR and INSERT_VECTOR_ELT may be combined by replacing one of the BUILD_VECTOR operands with the newly inserted element; but INSERT_VECTOR_ELT allows its scalar operand to be larger than the element type, with any extra high bits being implicitly truncated. The result is a BUILD_VECTOR where one of the operands has a type larger the the vector element type. Any code that operates on BUILD_VECTORs may now need to be aware of the potential type discrepancy between the vector element type and the BUILD_VECTOR operands. This patch updates all of the places that I could find to handle that case. llvm-svn: 68996
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-134-30/+29
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
* Refactor some code in SelectionDAGLegalize::ExpandBUILD_VECTOR.Bob Wilson2009-04-131-24/+19
| | | | llvm-svn: 68981
* PR3934: Fix a bogus two-address pass assertion.Evan Cheng2009-04-131-8/+10
| | | | llvm-svn: 68979
* Right now, Debugging information to encode scopes (DW_TAG_lexical_block) ↵Devang Patel2009-04-133-21/+24
| | | | | | | | relies on DBG_LABEL. Unfortunately this intefers with the quality of optimized code. This patch updates dwarf writer to encode scoping information in DWARF only in FastISel mode. llvm-svn: 68973
* Reapply 68847.Devang Patel2009-04-135-6/+168
| | | | | | Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default. llvm-svn: 68964
* Implement x86 h-register extract support.Dan Gohman2009-04-137-98/+359
| | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. llvm-svn: 68962
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-132-75/+170
| | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. llvm-svn: 68961
* Remove x86's special-case handling for ISD::TRUNCATE andDan Gohman2009-04-131-85/+0
| | | | | | | | ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle these cases, and the scheduling issues observed earlier appear to be resolved now. llvm-svn: 68959
* Fix copy+pastos in comments.Dan Gohman2009-04-131-2/+2
| | | | llvm-svn: 68958
* Don't abort on an aliasing physical register that does not haveDan Gohman2009-04-131-1/+1
| | | | | | a live interval. This is needed for some upcoming subreg changes. llvm-svn: 68956
* When assigning a physical register to a MachineOperand, setDan Gohman2009-04-131-1/+10
| | | | | | | | | the subreg field to 0, since the subreg field is only used for virtual register subregs. This doesn't change current functionality; it just eliminates bogus noise from debug output. llvm-svn: 68955
* List the l registers before h registers, for consistency.Dan Gohman2009-04-131-4/+4
| | | | llvm-svn: 68954
* Add an assertion to verify that a copy was actually emitted.Dan Gohman2009-04-131-1/+2
| | | | llvm-svn: 68953
* Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.Dan Gohman2009-04-131-3/+3
| | | | llvm-svn: 68951
* Add a comment about MOVSX64rr8.Dan Gohman2009-04-131-0/+4
| | | | llvm-svn: 68950
* Fix another hard-coded constant to use X86AddrNumOperands.Dan Gohman2009-04-131-1/+1
| | | | | | This unbreaks the JIT on x86-64. llvm-svn: 68948
* X86-64 TLS support for local exec and initial exec.Rafael Espindola2009-04-133-10/+23
| | | | llvm-svn: 68947
* While passing arg of types larger than char only one byte at lower end was ↵Sanjiv Gupta2009-04-131-1/+1
| | | | | | getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256. llvm-svn: 68946
* Fix warning in .ll parser, detect and reject available_externally on functionNick Lewycky2009-04-131-0/+1
| | | | | | declarations. llvm-svn: 68944
* Add a new "available_externally" linkage type. This is intendedChris Lattner2009-04-1311-7/+30
| | | | | | | | to support C99 inline, GNU extern inline, etc. Related bugzilla's include PR3517, PR3100, & PR2933. Nothing uses this yet, but it appears to work. llvm-svn: 68940
* eliminate unneeded parens.Chris Lattner2009-04-131-2/+2
| | | | llvm-svn: 68939
* Link against libffi if available, fall back to "no external calls fromNick Lewycky2009-04-131-8/+8
| | | | | | interpreter mode" when it's not. llvm-svn: 68937
* fix PR3965:SIGINT handler not restored after calling ParseAST(),Chris Lattner2009-04-121-1/+2
| | | | | | patch by Alexei Svitkine! llvm-svn: 68929
* In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matchingRafael Espindola2009-04-121-3/+8
| | | | | | only if symbolic addresses are RIP relatives. llvm-svn: 68924
* refactor some code into X86DAGToDAGISel::MatchWrapperRafael Espindola2009-04-121-44/+51
| | | | llvm-svn: 68915
* "There was a typo in my previous patch which leads to miscompilation ofChris Lattner2009-04-121-1/+1
| | | | | | | | | | | | | | strncat :( strncat(foo, "bar", 99) would be optimized to memcpy(foo+strlen(foo), "bar", 100, 1) instead of memcpy(foo+strlen(foo), "bar", 4, 1)" Patch by Benjamin Kramer! llvm-svn: 68905
* fix a cross-block fastisel crash handling overflow intrinsics.Chris Lattner2009-04-121-5/+16
| | | | | | See comment for details. This fixes rdar://6772169 llvm-svn: 68890
* make UpdateValueMap handle the possiblity that we could beChris Lattner2009-04-121-1/+1
| | | | | | copying into the right register, avoiding a copy. llvm-svn: 68889
* optimize FastISel::UpdateValueMap to avoid duplicate map lookups,Chris Lattner2009-04-121-7/+12
| | | | | | and make it return the assigned register. llvm-svn: 68888
* simplify code by using IntrinsicInst.Chris Lattner2009-04-121-69/+54
| | | | llvm-svn: 68887
* Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner2009-04-121-15/+3
| | | | | | | hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. llvm-svn: 68886
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