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* X86: loosen an overly aggressive MachO assertionSaleem Abdulrasool2016-09-201-2/+6
| | | | | | | | | | | | | We would assert that the FP setup CFI used esp/rsp always. This held up in practice when the code was generated from IR. However, with the integrated assembler, it is possible to have the input be user specified assembly. In such a case, we cannot assume that the function implementation has a compact unwind representation. Loosen the assertion into a check and bail if we cannot represent the frame pointer in the compact unwinding. Addresses PR30453! llvm-svn: 281986
* Remove more guts of TargetMachine::getNameWithPrefix and migrate one check ↵Eric Christopher2016-09-202-8/+8
| | | | | | | | to the TLOF mach-o version. NFC intended. llvm-svn: 281983
* Remove a use of subtarget initialization in the X86 backend so we can get ↵Eric Christopher2016-09-201-1/+4
| | | | | | | | rid of the default subtarget. NFC intended. llvm-svn: 281982
* Remove extra argument used once on TargetMachine::getNameWithPrefix and ↵Eric Christopher2016-09-202-4/+3
| | | | | | inline the result into the singular caller. llvm-svn: 281981
* Improve the -debug output for Debug Range Extension (NFC)Keith Walker2016-09-201-1/+2
| | | | | | Include header messages and remove unnecessary blank lines. llvm-svn: 281980
* GlobalISel: split aggregates for PCS loweringTim Northover2016-09-206-47/+143
| | | | | | | | | | | This should match the existing behaviour for passing complicated struct and array types, in particular HFAs come through like that from Clang. For C & C++ we still need to somehow support all the weird ABI flags, or at least those that are present in the IR (signext, byval, ...), and stack-based parameter passing. llvm-svn: 281977
* move variables closer to their uses; add FIXMEs; NFCSanjay Patel2016-09-201-10/+10
| | | | llvm-svn: 281972
* AVX-512: Fixed a bug in lowering saturated operations on KNL.Elena Demikhovsky2016-09-201-2/+8
| | | | | | | | The generated code is still not optimal. Differential Revision: https://reviews.llvm.org/D24723 llvm-svn: 281966
* [AMDGPU] Refactor VOP3 instruction TD definitionsValery Pykhtin2016-09-206-373/+448
| | | | | | Differential revision: https://reviews.llvm.org/D24664 llvm-svn: 281965
* Make llvm::ConvertDebugDeclareToDebugValue() be a void function (NFC)Keith Walker2016-09-201-8/+5
| | | | | | | | | | The routines llvm::ConvertDebugDeclareToDebugValue() always returned a true value which was never checked at the call site; change the function return type to void. This NFC cleanup was approved in the review https://reviews.llvm.org/D23715 llvm-svn: 281964
* Reverting revision 281960 due to test failures.Dorit Nuzman2016-09-201-10/+2
| | | | llvm-svn: 281961
* [SROA] Preserve llvm.mem.parallel_loop_access metadata.Dorit Nuzman2016-09-201-2/+10
| | | | | | | | | | | | SROA doesn't preserve the llvm.mem.parallel_loop_access metadata when it transforms loads/stores. This patch fixes a couple occurences of this issue. (Partially addresses PR28981). Differential Revision: https://reviews.llvm.org/D23549 llvm-svn: 281960
* [AVX-512] Teach X86InstrInfo::copyPhysReg to use a 512-bit move if ↵Craig Topper2016-09-203-5/+38
| | | | | | | | XMM16-XMM31 or YMM16-YMM31 are the source or dest of the copy and VLX is not supported. This can happen with SUBREG_TO_REG of ZMM16-ZMM31. Fixes PR30430. llvm-svn: 281959
* [AVX-512] Use 512-bit vcvtps2ph/vcvtph2ps to implement fp_to_f16/f16_to_fp ↵Craig Topper2016-09-203-2/+32
| | | | | | | | when F16C and VLX are not supported. Fixes PR23941. llvm-svn: 281958
* BranchFolder: Fix invalid undef flags after merge.Matthias Braun2016-09-201-5/+14
| | | | | | | | | | It is legal to merge instructions with different undef flags; However we must drop the undef flag from the merged instruction if it isn't present everywhere. This fixes http://llvm.org/PR30199 llvm-svn: 281957
* [x86] fix variable names; NFCSanjay Patel2016-09-201-22/+23
| | | | llvm-svn: 281953
* [sanitizer-coverage] add comdat to coverage guards if neededKostya Serebryany2016-09-201-0/+2
| | | | llvm-svn: 281952
* [LCSSA] Cache LoopExits to avoid wasted workPhilip Reames2016-09-191-3/+9
| | | | | | | | | | When looking at the scribus_1.3 example from https://llvm.org/bugs/show_bug.cgi?id=10584, I noticed that we were spending a large amount of time computing loop exits in LCSSA. This code appears to be written with the assumption that LoopExits are stored in the Loop and thus cheap to query. This is not true, so we should cache the result across the potentially long running loop which tends to visit a small handful of Loops. On the particular example from 10584, this change drops the time spent in LCSSA computation by about 80%. Differential Revision: https://reviews.llvm.org/D24509 llvm-svn: 281949
* [RegisterBankInfo] Adapt call to std::fill due to use of SmallVector.Quentin Colombet2016-09-191-1/+1
| | | | | | This was meant to be commited with my previous commit. llvm-svn: 281948
* Merge branch 'ADCE5'David Callahan2016-09-191-2/+39
| | | | llvm-svn: 281947
* [x86] use getSignBit() to simplify code; NFCISanjay Patel2016-09-191-4/+3
| | | | llvm-svn: 281944
* BitcodeWriter: fix emission of invoke when calling a var-arg function with ↵Mehdi Amini2016-09-191-1/+1
| | | | | | operand bundles llvm-svn: 281940
* [libFuzzer] use sleep() instead of std::this_thread::sleep_for to avoid ↵Kostya Serebryany2016-09-191-1/+1
| | | | | | coverage from instrumented libc++ llvm-svn: 281933
* Handle early inline for hot callsites that reside in the same basic block.Dehao Chen2016-09-191-2/+7
| | | | | | | | | | | | Summary: Callsites in the same basic block should share the same hotness. This patch checks for the hottest callsite in the same basic block, and use the hotness for all callsites in that basic block for early inline decisions. It also fixes the test to add "-S" so theat the "CHECK-NOT" is actually checking the content. Reviewers: dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24734 llvm-svn: 281927
* [RegisterBankInfo] Avoid heap allocation in most cases.Quentin Colombet2016-09-191-1/+1
| | | | | | | | | | | The OperandsMapper class is used heavy in RegBankSelect and each instantiation triggered a heap allocation for the array of operands. Instead, use a SmallVector with a big enough size such that most of the cases do not have to use dynamically allocated memory. This improves the compile time of the RegBankSelect pass. llvm-svn: 281916
* LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculationMatthias Braun2016-09-191-3/+3
| | | | | | | | | | | | | Machine programs need a definition of each vreg before reaching a use (the definition may come from an IMPLICIT_DEF instruction). This class of errors is not detected by the MachineVerifier because of efficiency concerns. LiveRangeCalc used to report these problems, make it do that again (followup to r279625). Also use report_fatal_error() instead of llvm_unreachable() as the error reporting is only present in asserts build anyway. llvm-svn: 281914
* Only set branch weight during sample pgo annotation when max_weight of the ↵Dehao Chen2016-09-191-11/+15
| | | | | | | | | | | | | | branch is non-zero. Otherwise use default static profile to set branch probability. Summary: It does not make sense to set equal weights for all unkown branches as we have static branch prediction available. Reviewers: dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24732 llvm-svn: 281912
* Use call target count to derive the call instruction weightDehao Chen2016-09-191-3/+5
| | | | | | | | | | | | Summary: The call target count profile is directly derived from LBR branch->target data. This is more reliable than instruction frequency profiles that could be moved across basic block boundaries. This patches uses call target count profile to annotate call instructions. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24410 llvm-svn: 281911
* [asan] Support dynamic shadow address instrumentationEtienne Bergeron2016-09-191-7/+46
| | | | | | | | | | | | | | | | | | | Summary: This patch is adding the support for a shadow memory with dynamically allocated address range. The compiler-rt needs to export a symbol containing the shadow memory range. This is required to support ASAN on windows 64-bits. Reviewers: kcc, rnk, vitalybuka Subscribers: kubabrecka, dberris, llvm-commits, chrisha Differential Revision: https://reviews.llvm.org/D23354 llvm-svn: 281908
* [AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin2016-09-196-648/+1118
| | | | | | Differential Revision: https://reviews.llvm.org/D24546 llvm-svn: 281903
* [AArch64] Fix encoding for lsl #12 in add/sub immediatesDiana Picus2016-09-191-2/+2
| | | | | | | | | | | Whenever an add/sub immediate needs a fixup, we set that immediate field to zero, which is correct, but we also set the shift bits to zero, which is not true for instructions that use lsl #12. This patch makes sure that if lsl #12 was used, it will appear in the encoding of the instruction. Differential Revision: https://reviews.llvm.org/D23930 llvm-svn: 281898
* [AMDGPU] Fix s_branch with -1 offsetSam Kolton2016-09-191-5/+2
| | | | | | | | | | | | | | | | | | | Summary: In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0. ''' label: s_branch label // should emit [0xff,0xff,0x82,0xbf] ''' Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl Differential Revision: https://reviews.llvm.org/D24671 llvm-svn: 281896
* Add @llvm.dbg.value entries for the phi node created by -mem2regKeith Walker2016-09-192-0/+47
| | | | | | | | | | | | | | | | | | | | | | | When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare entries are converted to @llvm.dbg.value entries at the place where the store instructions existed. However no entry is created to describe the resulting value of the phi node. The effect of this is especially noticeable in for loops which have a constant for the intial value; the loop control variable's location would be described as the intial constant value in the loop body once the -mem2reg optimization phase was run. This change adds the creation of the @llvm.dbg.value entries to describe variables whose location is the result of a phi node created in -mem2reg. Also when the phi node is finally lowered to a machine instruction it is important that the lowered "load" instruction is placed before the associated DEBUG_VALUE entry describing the value loaded. Differential Revision: https://reviews.llvm.org/D23715 llvm-svn: 281895
* [Thumb] Set correct initial mapping symbol for big-endian thumbOliver Stannard2016-09-191-1/+2
| | | | | | | | | | The initial mapping symbol state is set from the triple, but we only checked for the little-endian thumb triple, so could end up with an ARM mapping symbol for big-endian thumb. Differential Revision: https://reviews.llvm.org/D24553 llvm-svn: 281894
* ARM: check alignment before transforming ldr -> ldm (or similar).Tim Northover2016-09-192-8/+28
| | | | | | | | | ldm and stm instructions always require 4-byte alignment on the pointer, but we weren't checking this before trying to reduce code-size by replacing a post-indexed load/store with them. Unfortunately, we were also dropping this incormation in DAG ISel too, but that's easy enough to fix. llvm-svn: 281893
* [SimplifyCFG] Update (AND) IR flags when CSE'ing instructionsJames Molloy2016-09-191-2/+4
| | | | | | | | We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to. Fixes PR30373. llvm-svn: 281889
* [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is ↵Craig Topper2016-09-192-32/+44
| | | | | | | | not the output of an instruction. SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from. llvm-svn: 281885
* [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is ↵Craig Topper2016-09-193-2/+23
| | | | | | | | supported regardless of whether F16C is also supported. Still need to add support for lowering using AVX512F when neither VLX or F16C is supported. llvm-svn: 281884
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-1911-62/+224
| | | | | | | | | | | | This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter. This is one of 3 commits to different repositories of XRay ARM port. The other 2 are: https://reviews.llvm.org/D23932 (Clang test) https://reviews.llvm.org/D23933 (compiler-rt) Differential Revision: https://reviews.llvm.org/D23931 llvm-svn: 281878
* Handle Invoke during sample profiler annotation: make it inlinable.Dehao Chen2016-09-181-23/+32
| | | | | | | | | | | | Summary: Previously we reline on inst-combine to remove inlinable invoke instructions. This causes trouble because a few extra optimizations are schedule early that could introduce too much CFG change (e.g. simplifycfg removes too much control flow). This patch handles invoke instruction in-place during sample profile annotation, so that we do not rely on instcombine to remove those invoke instructions. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24409 llvm-svn: 281870
* [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 ↵Craig Topper2016-09-183-4/+30
| | | | | | | | rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision. Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future. llvm-svn: 281868
* [AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a ↵Craig Topper2016-09-181-2/+2
| | | | | | second operand containing an X86 specific rounding mode encoding that doesn't belong. llvm-svn: 281867
* [libFuzzer] add -print_coverage=1 flag to print coverage directly from ↵Kostya Serebryany2016-09-188-10/+45
| | | | | | libFuzzer llvm-svn: 281866
* Fix covered-switch-default warningSimon Pilgrim2016-09-181-5/+4
| | | | llvm-svn: 281865
* [X86] Fix typo in comment. NFCCraig Topper2016-09-181-1/+1
| | | | llvm-svn: 281862
* [AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer ↵Craig Topper2016-09-181-1/+16
| | | | | | conversion intrinsics to be consistent across all intruction sets. llvm-svn: 281861
* [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the ↵Craig Topper2016-09-181-8/+8
| | | | | | correct register class. llvm-svn: 281860
* Fix built bot failureXinliang David Li2016-09-181-1/+1
| | | | llvm-svn: 281859
* [Profile] Implement select instruction instrumentation in IR PGOXinliang David Li2016-09-182-11/+151
| | | | | | Differential Revision: http://reviews.llvm.org/D23727 llvm-svn: 281858
* [Loop Vectorizer] Consecutive memory access - fixed and simplifiedElena Demikhovsky2016-09-182-85/+9
| | | | | | | | | Amended consecutive memory access detection in Loop Vectorizer. Load/Store were not handled properly without preceding GEP instruction. Differential Revision: https://reviews.llvm.org/D20789 llvm-svn: 281853
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