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* LSR: Fold redundant bitcasts on-the-fly.Andrew Trick2011-12-141-3/+8
| | | | llvm-svn: 146597
* ARM NEON fix alignment encoding for VST2 w/ writeback.Jim Grosbach2011-12-141-4/+4
| | | | | | Add tests for w/ writeback instruction parsing and encoding. llvm-svn: 146594
* Add the .incbin directive which takes the binary data from a file and emitsKevin Enderby2011-12-141-0/+49
| | | | | | it to the streamer. rdar://10383898 llvm-svn: 146592
* Nuke old code. Missed in last commit.Jim Grosbach2011-12-141-14/+0
| | | | llvm-svn: 146590
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-144-54/+130
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM NEON improve factoring a bit. No functional change.Jim Grosbach2011-12-141-18/+12
| | | | llvm-svn: 146585
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-143-16/+47
| | | | | | | | | | | r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-145-76/+52
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* Fix for bug #11429: Wrong behaviour for switches. Small improvement for code ↵Stepan Dyatkovskiy2011-12-141-11/+82
| | | | | | size heuristics. llvm-svn: 146578
* It turns out that clang does use pointer-to-function types toDan Gohman2011-12-141-2/+6
| | | | | | point to ARC-managed pointers sometimes. This fixes rdar://10551239. llvm-svn: 146577
* Fix speling and 80-col.Jakob Stoklund Olesen2011-12-141-4/+3
| | | | llvm-svn: 146575
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-144-6/+32
| | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
* Fix copy/pasto that skipped the 'modify' step.Jim Grosbach2011-12-141-4/+4
| | | | llvm-svn: 146571
* ARM/Thumb2 mov vs. mvn alias goes both ways.Jim Grosbach2011-12-142-0/+4
| | | | llvm-svn: 146570
* VFP2 is required for FP loads. Noticed by inspection.Chad Rosier2011-12-141-0/+2
| | | | llvm-svn: 146569
* Tidy up.Chad Rosier2011-12-141-1/+2
| | | | llvm-svn: 146568
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-142-1/+11
| | | | | | | | | | When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 llvm-svn: 146567
* Fix 80-column violation and extraneous brackets.Chad Rosier2011-12-141-8/+9
| | | | llvm-svn: 146566
* llvm/lib/CodeGen: Fix cmake build since r146542.NAKAMURA Takumi2011-12-141-0/+1
| | | | llvm-svn: 146550
* Fix a stupid typo in MemDepPrinter.Eli Friedman2011-12-141-1/+1
| | | | llvm-svn: 146549
* Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.Eli Friedman2011-12-141-0/+5
| | | | llvm-svn: 146548
* Allow target to specify register output dependency. Still default to one.Evan Cheng2011-12-141-1/+7
| | | | llvm-svn: 146547
* Revert r146481 to review possible miscompilations.Bill Wendling2011-12-141-33/+6
| | | | llvm-svn: 146546
* Disable to review some failures.Bill Wendling2011-12-141-1/+2
| | | | llvm-svn: 146545
* ARM assembler support for the target-specific .req directive.Jim Grosbach2011-12-141-1/+67
| | | | | | rdar://10549683 llvm-svn: 146543
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-1418-109/+476
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* DW_AT_virtuality is also defined to be constant, not flag.Nick Lewycky2011-12-141-2/+2
| | | | llvm-svn: 146534
* Per discussion on the list, remove BitcodeVerify pass to reimplement as a ↵Chad Rosier2011-12-142-55/+0
| | | | | | free function. llvm-svn: 146531
* [asan] remove .preinit_array from the compiler module (it breaks .so ↵Kostya Serebryany2011-12-141-16/+0
| | | | | | builds). This should be done in the run-time. llvm-svn: 146527
* Support/FileSystem: Add file_magic and move a vew clients over to it.Michael J. Spencer2011-12-133-17/+129
| | | | llvm-svn: 146523
* Support/Program: Make Change<stream>ToBinary return error_code.Michael J. Spencer2011-12-134-12/+20
| | | | llvm-svn: 146522
* Cleanup whitespace.Michael J. Spencer2011-12-132-4/+4
| | | | llvm-svn: 146521
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-132-1/+45
| | | | | | rdar://10549767 llvm-svn: 146520
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-132-11/+39
| | | | | | rdar://10550269 llvm-svn: 146519
* Thumb2 pre/post indexed stores can be from any non-PC GPR.Jim Grosbach2011-12-131-3/+3
| | | | | | rdar://10549786 llvm-svn: 146518
* Thumb2 tweak for ccout handling in RSB parsing.Jim Grosbach2011-12-131-1/+4
| | | | llvm-svn: 146516
* ARM thumb2 parsing of "rsb rd, rn, #0".Jim Grosbach2011-12-131-2/+8
| | | | | | rdar://10549741 llvm-svn: 146515
* ARM NEON two-operand aliases for VQDMULH.Jim Grosbach2011-12-132-0/+13
| | | | llvm-svn: 146514
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-133-3/+13
| | | | llvm-svn: 146511
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-132-0/+3
| | | | llvm-svn: 146508
* ARM add more 'gas' compatibility aliases for NEON instructions.Jim Grosbach2011-12-133-3/+37
| | | | llvm-svn: 146507
* [asan] report an error if blacklist file contains a malformed regex. fixes ↵Kostya Serebryany2011-12-131-5/+13
| | | | | | asan issue 17 llvm-svn: 146503
* [fast-isel] Unaligned loads of floats are not supported. Therefore, convert ↵Chad Rosier2011-12-131-7/+32
| | | | | | | | to a regular load and then move the result from a GPR to a FPR. llvm-svn: 146502
* [fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle Chad Rosier2011-12-131-103/+0
| | | | | | instructions that define aggregate types. llvm-svn: 146492
* Avoid using the 'insertvalue' instruction here.Bill Wendling2011-12-131-6/+33
| | | | | | | | | Fast ISel isn't able to handle 'insertvalue' and it causes a large slowdown during -O0 compilation. We don't necessarily need to generate an aggregate of the values here if they're just going to be extracted directly afterwards. <rdar://problem/10530851> llvm-svn: 146481
* DW_AT_accessibility is "constant" class, not form class, so it may not useNick Lewycky2011-12-131-6/+6
| | | | | | DW_FORM_flag. Use DW_FORM_data1 for one byte. llvm-svn: 146475
* Expand .cprestore directive to multiple instructions if the offset does not fit Akira Hatanaka2011-12-133-16/+35
| | | | | | in a 16-bit field. llvm-svn: 146469
* Relocation against a symbol, instead of against section. We had some extremeAkira Hatanaka2011-12-131-2/+2
| | | | | | | | | | | test cases where there were a lot of relocations applied relative to a large rodata section. Gas would create a symbol for each of these whereas we would be relative to the beginning of the rodata section. This change mimics what gas does. Patch by Jack Carter. llvm-svn: 146468
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-1317-23/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Cleanup. Clarify LSRInstance public methods.Andrew Trick2011-12-131-1/+1
| | | | llvm-svn: 146459
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