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* [APInt] Add early outs for a division by 1 to udiv/urem/udivremCraig Topper2017-05-121-4/+18
| | | | | | | | We already counted the number of bits in the RHS so its pretty cheap to just check if the RHS is 1. Differential Revision: https://reviews.llvm.org/D33154 llvm-svn: 302953
* [APInt] In udivrem, remember the bit width in a local variable so we don't ↵Craig Topper2017-05-121-4/+5
| | | | | | | | reread it from the LHS which might be aliased with Quotient or Remainder. This helped the compiler generate better code for the single word case. It was able to remember that the bit width was still a single word when it created the Remainder APInt and not create code for it possibly being multiword. llvm-svn: 302952
* LTO: Don't verify modules twice in verifyMergedModuleOnceAdrian Prantl2017-05-121-10/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D33140 llvm-svn: 302951
* AMDGPU/SI: Don't promote to vector if the load/store is volatile.Changpeng Fang2017-05-121-2/+5
| | | | | | | | | | | | | Summary: We should not change volatile loads/stores in promoting alloca to vector. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D33107 llvm-svn: 302943
* [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)Simon Pilgrim2017-05-121-1/+3
| | | | | | | | This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146. Differential Revision: https://reviews.llvm.org/D33147 llvm-svn: 302942
* Remove ignore-empty-index-file optionTeresa Johnson2017-05-121-8/+2
| | | | | | | | | | | | | | | Summary: As discussed in the D32195 review thread and on IRC, remove this option and replace with parameter, which will be set to true when invoked from clang in the context of a ThinLTO distributed backend. Reviewers: pcc Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D33133 llvm-svn: 302939
* Add LiveRangeShrink pass to shrink live range within BB.Dehao Chen2017-05-124-0/+216
| | | | | | | | | | | | | | Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB. Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb Reviewed By: MatzeB, andreadb Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D32563 llvm-svn: 302938
* [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the ↵Tim Shen2017-05-124-50/+108
| | | | | | | | | | | | | | | | | | | | | | backend. NFC. Summary: Eli pointed out that it's unsafe to combine the shifts to ISD::SHL etc., because those are not defined for b > sizeof(a) * 8, even after some of the combiners run. However, PPCISD::SHL defines that behavior (as the instructions themselves). Move the combination to the backend. The tests in shift_mask.ll still pass. Reviewers: echristo, hfinkel, efriedma, iteratee Subscribers: nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D33076 llvm-svn: 302937
* [CodeView] Add a random access type visitor.Zachary Turner2017-05-127-89/+160
| | | | | | | | | | | | This adds a visitor that is capable of accessing type records randomly and caching intermediate results that it learns about during partial linear scans. This yields amortized O(1) access to a type stream even though type streams cannot normally be indexed. Differential Revision: https://reviews.llvm.org/D33009 llvm-svn: 302936
* [AArch64][Falkor] Refine modeling of multiply accumulate forwarding.Geoff Berry2017-05-122-44/+61
| | | | llvm-svn: 302933
* [APInt] Add an assert to check for divide by zero in udivrem. NFCCraig Topper2017-05-121-0/+1
| | | | | | udiv and urem already had the same assert. llvm-svn: 302931
* [APInt] Remove unnecessary checks of rhsWords==1 with lhsWords==1 from udiv ↵Craig Topper2017-05-121-2/+2
| | | | | | | | and udivrem. NFC At this point in the code rhsWords is guaranteed to be non-zero and less than or equal to lhsWords. So if lhsWords is 1, rhsWords must also be 1. urem alread had the check removed so this makes all 3 consistent. llvm-svn: 302930
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-05-121-7/+7
| | | | llvm-svn: 302927
* [KnownBits] Add bit counting methods to KnownBits struct and use them where ↵Craig Topper2017-05-1216-89/+76
| | | | | | | | | | | | possible This patch adds min/max population count, leading/trailing zero/one bit counting methods. The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give. Differential Revision: https://reviews.llvm.org/D32931 llvm-svn: 302925
* [codeview] Fix assertion failure introduced in r295354 refactoringReid Kleckner2017-05-121-2/+1
| | | | | | | | CodeViewDebug sets Asm to nullptr to disable debug info generation. You can get a .ll file like no-cus.ll from 'clang -gcodeview -g0', which happens in the ubsan test suite. llvm-svn: 302923
* AMDGPU/GlobalISel: Mark 32-bit integer constants as legalTom Stellard2017-05-121-0/+1
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33115 llvm-svn: 302919
* [SPARC] Support 'f' and 'e' inline asm constraints.James Y Knight2017-05-122-3/+26
| | | | | | | | Based on patch by Patrick Boettcher and Chris Dewhurst. Differential Revision: https://reviews.llvm.org/D29116 llvm-svn: 302911
* [NewGVN] Improve debug output a bit. NFCI.Davide Italiano2017-05-121-1/+1
| | | | | | | While debugging a predicate info problem, I noticed this was missing a newline, making the debug output slightly less readable. llvm-svn: 302908
* [DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.Simon Pilgrim2017-05-121-8/+2
| | | | llvm-svn: 302907
* [NewGVN] Format an assertion and fix a typo. NFCI.Davide Italiano2017-05-121-3/+2
| | | | llvm-svn: 302906
* [NewGVN] Don't incorrectly reset the memory leader.Davide Italiano2017-05-121-1/+1
| | | | | | | | | | This code was missing a check for stores, so we were thinking the congruency class didn't have any memory members, and reset the memory leader. Differential Revision: https://reviews.llvm.org/D33056 llvm-svn: 302905
* [DAGCombine] Use SelectionDAG::getZExtOrTrunc helper. NFCI.Simon Pilgrim2017-05-121-8/+2
| | | | llvm-svn: 302897
* Use SDValue::getOperand() helper. NFCI.Simon Pilgrim2017-05-122-22/+19
| | | | llvm-svn: 302896
* Use SDValue::getOperand() helper. NFCI.Simon Pilgrim2017-05-121-22/+19
| | | | llvm-svn: 302894
* [AVR] Migrate to new StructType::get owing to Supress all uses of ↵Leslie Zhai2017-05-121-1/+1
| | | | | | | | | | | | LLVM_END_WITH_NULL Reviewers: dylanmckay, jroelofs, RKSimon, serge-sans-paille Reviewed By: serge-sans-paille Differential Revision: https://reviews.llvm.org/D33119 llvm-svn: 302885
* [BPI] Ignore remainder while distributing the remaining probability from ↵Serguei Katkov2017-05-121-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | unreachanble This is a follow up patch for https://reviews.llvm.org/rL300440 to address a comment. To make implementation to be consistent with other cases we just ignore the remainder after distribution of remaining probability between reachable edges. If we reduced the probability of some edges coming to unreachable blocks we should distribute the remaining part across other edges coming to reachable blocks to satisfy the condition that sum of all probabilities should be equal to one. If this remaining part is not divided by number of "reachable" edges then we get this remainder. This remainder probability should be pretty small. Other cases just ignore if the sum of probabilities is not equal to one so we do the same. Reviewers: chandlerc, sanjoy, vsk, junbuml, reames Reviewed By: reames Subscribers: reames, llvm-commits Differential Revision: https://reviews.llvm.org/D32124 llvm-svn: 302883
* [APInt] Fix a case where udivrem might delete and create a new allocation ↵Craig Topper2017-05-121-2/+5
| | | | | | instead of reusing the original. llvm-svn: 302882
* Handle a COPY with undef source operand in LowerCopy()Jonas Paulsson2017-05-121-2/+3
| | | | | | | | | | | | | Llvm-stress discovered that a COPY may end up in ExpandPostRA::LowerCopy() with an undef source operand. It is not possible for the target to handle this, as this flag is not passed to TII->copyPhysReg(). This patch solves this by treating such a COPY as an identity COPY. Review: Matthias Braun https://reviews.llvm.org/D32892 llvm-svn: 302877
* [IfConversion] Keep the CFG updated incrementally in IfConvertTriangleMikael Holmen2017-05-121-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Instead of using RemoveExtraEdges (which uses analyzeBranch, which cannot always be trusted) at the end to fixup the CFG we keep the CFG updated as we go along and remove or add branches and merge blocks. This way we won't have any problems if the involved MBBs contain unanalyzable instructions. This fixes PR32721. In that case we had a triangle EBB | \ | | | TBB | / FBB where FBB didn't have any successors at all since it ended with an unconditional return. Then TBB and FBB were be merged into EBB, but EBB would still keep its successors, and the use of analyzeBranch and CorrectExtraCFGEdges wouldn't help to remove them since the return instruction is not analyzable (at least not on ARM). Reviewers: kparzysz, iteratee, MatzeB Reviewed By: iteratee Subscribers: aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33037 llvm-svn: 302876
* [PM/Unswitch] Teach the new simple loop unswitch to handle loopChandler Carruth2017-05-121-23/+138
| | | | | | | | | | | | | | | | | | | | | | | | invariant PHI inputs and to rewrite PHI nodes during the actual unswitching. The checking is quite easy, but rewriting the PHI nodes is somewhat surprisingly challenging. This should handle both branches and switches. I think this is now a full featured trivial unswitcher, and more full featured than the trivial cases in the old pass while still being (IMO) somewhat simpler in how it works. Next up is to verify its correctness in more widespread testing, and then to add non-trivial unswitching. Thanks to Davide and Sanjoy for the excellent review. There is one remaining question that I may address in a follow-up patch (see the review thread for details) but it isn't related to the functionality specifically. Differential Revision: https://reviews.llvm.org/D32699 llvm-svn: 302867
* [APInt] Add a utility method to change the bit width and storage size of an ↵Craig Topper2017-05-121-42/+31
| | | | | | | | | | | | | | | | | | | APInt. Summary: This adds a resize method to APInt that manages deleting/allocating storage for an APInt and changes its bit width. Use this to simplify code in copy assignment and divide. The assignment code in particular was overly complicated. Treating every possible case as a separate implementation. I'm also pretty sure the clearUnusedBits code at the end was unnecessary. Since we always copying whole words from the source APInt. All unused bits should be clear in the source. Reviewers: hans, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33073 llvm-svn: 302863
* DWARF: Avoid cross-CU references under FissionDavid Blaikie2017-05-127-70/+116
| | | | | | | | | | | | | | | | | | Turns out that the Fission/Split DWARF package format (DWP) is currently insufficient to handle cross-CU (ref_addr) references. So for now, duplicate any debug info needed in these situations: * inlined_subroutine's abstract_origin * inlined variable's abstract_origin * types Keep the ref_addr behavior in general, including in the split DWARF inline debug info that can be emitted into the object files for online symbolication. Keep a flag to use the old (ref_addr) behavior for testing ways of addressing this limitation in the DWP tool (& for those not using DWP packaging). llvm-svn: 302858
* [XRay][lib] Support and temporarily skip over CustomEvent recordsDean Michael Berris2017-05-121-2/+32
| | | | | | | | | | | | | | | | Summary: In D30630 we will start writing custom event records. To avoid breaking the tools that read the FDR mode records, we skip over these records. To support these custom event records more effectively, we will have to expose them in the trace loading API. Those changes will be forthcoming. Reviewers: kpw, pelikan Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33032 llvm-svn: 302856
* CallGraph: Remove almost-unused field 'Root'.Peter Collingbourne2017-05-111-29/+5
| | | | llvm-svn: 302852
* Change sample profile writer to make it deterministic.Dehao Chen2017-05-111-4/+38
| | | | | | | | | | | | | | Summary: This patch changes the function profile output order to be deterministic. In order to make it easier to understand, hottest functions (with most total samples) is ordered first. Reviewers: dnovillo, davidxl Reviewed By: dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33111 llvm-svn: 302851
* Restrict call metadata based hotness detection to Sample PGO modeTeresa Johnson2017-05-111-5/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: Don't use the metadata on call instructions for determining hotness unless we are in sample PGO mode, where it is needed because profile counts are not accurate. In instrumentation mode this is not necessary and does more harm than good when calls have VP metadata that hasn't been properly scaled after transformations or dropped after constant prop based devirtualization (both should be fixed, but we don't need to do this in the first place for instrumentation PGO). This required adjusting a number of tests to distinguish between sample and instrumentation PGO handling, and to add in profile summary metadata so that getProfileCount can get the summary. Reviewers: davidxl, danielcdh Subscribers: aemerson, rengolin, mehdi_amini, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D32877 llvm-svn: 302844
* Issue diagnostics when returning FP values on x86_64 without SSE1/2Reid Kleckner2017-05-111-9/+24
| | | | | | | | | | | | | Avoid using report_fatal_error, because it will ask the user to file a bug. If the user attempts to disable SSE on x86_64 and them use floating point, that's a bug in their code, not a bug in the compiler. This is just a start. There are other ways to crash the backend in this configuration, but they should be updated to follow this pattern. Differential Revision: https://reviews.llvm.org/D27522 llvm-svn: 302835
* [PPC] Change the register constraint of the first source operand of ↵Guozhi Wei2017-05-112-1/+18
| | | | | | | | | | | | instruction mtvsrdd to g8rc_nox0 According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834
* [GISel]: Remove unused lambda captures. NFCAditya Nandakumar2017-05-111-4/+4
| | | | | | https://reviews.llvm.org/D33085 llvm-svn: 302831
* Decrease inlinecold-threshold to 45Easwaran Raman2017-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | I ran the test-suite (including SPEC 2006) in PGO mode comparing cold thresholds of 225 and 45. Here are some stats on the text size: Out of 904 tests that ran, 197 see a change in text size. The average text size reduction (of all the 904 binaries) is 1.07%. Of the 197 binaries, 19 see a text size increase, as high as 18%, but most of them are small single source benchmarks. There are 3 multisource benchmarks with a >0.5% size increase (0.7, 1.3 and 2.1 are their % increases). On the other side of the spectrum, 31 benchmarks see >10% size reduction and 6 of them are MultiSource. I haven't run the test-suite with other values of inlinecold-threshold. Since we have a cold callsite threshold of 45, I picked this value. Differential revision: https://reviews.llvm.org/D33106 llvm-svn: 302829
* De-virtualize TerminatorInst successor accessorsReid Kleckner2017-05-111-0/+36
| | | | | | | | | Use the same switch technique to eliminate virtual successor accessors from TerminatorInst. Extracted from D31261. NFC llvm-svn: 302827
* De-virtualize GlobalValueReid Kleckner2017-05-113-33/+53
| | | | | | | | | | | | | | | The erase/remove from parent methods now use a switch table to remove themselves from their appropriate parent ilist. The copyAttributesFrom method is now completely non-virtual, since we only ever copy attributes from a global of the appropriate type. Pre-requisite to de-virtualizing Value to save a vptr (https://reviews.llvm.org/D31261). NFC llvm-svn: 302823
* [AArch64][MachineCombine] Fold FNMUL+FSUB -> FNMADD.Chad Rosier2017-05-111-0/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D33101. llvm-svn: 302822
* [AMDGPU] Placate unused variable warning in release builds.Davide Italiano2017-05-111-0/+1
| | | | llvm-svn: 302821
* [MSP430] Generate EABI-compliant libcallsVadzim Dambrouski2017-05-114-38/+237
| | | | | | | | | | | | | Updates the MSP430 target to generate EABI-compatible libcall names. As a byproduct, adjusts the hardware multiplier options available in the MSP430 target, adds support for promotion of the ISD::MUL operation for 8-bit integers, and correctly marks R11 as used by call instructions. Patch by Andrew Wygle. Differential Revision: https://reviews.llvm.org/D32676 llvm-svn: 302820
* [LiveVariables] Switch Kill/Defs sets to be DenseSet(s).Davide Italiano2017-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The testcase in PR32984 shows a non linear compile time increase after a change that made the LoopUnroll pass more aggressive (increasing the threshold). My profiling shows all the time of PHI elimination goes to llvm::LiveVariables::addNewBlock. This is because we keep Defs/Kills registers in a SmallSet and vfind(const T &V); is O(N). Switching to a DenseSet reduces the time spent in the pass from 297 seconds to 97 seconds. Profiling still shows a lot of time is spent iterating the data structure, so I guess there's room for improvement. Dan tells me GCC uses real set operations for live registers and it takes no-time on this testcase. Matthias points out we might want to switch all this to LiveIntervalAnalysis so it's not entirely sure if a rewrite is worth it. Differential Revision: https://reviews.llvm.org/D33088 llvm-svn: 302819
* [APInt] Remove an APInt copy from the return of APInt::multiplicativeInverse.Craig Topper2017-05-111-1/+4
| | | | llvm-svn: 302816
* [APInt] Fix typo in comment. NFCCraig Topper2017-05-111-1/+1
| | | | llvm-svn: 302815
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-113-23/+22
| | | | | | | | | | We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
* AMDGPU: Pull fneg out of extract_vector_eltMatt Arsenault2017-05-114-1/+31
| | | | | | | This allows folding source modifiers in more f16 cases. Makes it easier to select per-component packed neg modifiers. llvm-svn: 302813
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