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* [NFC] remove unused functionsGuillaume Chatelet2019-09-161-8/+0
| | | | | | | | | | | | Reviewers: courbet Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67616 llvm-svn: 371994
* AMDGPU/GlobalISel: Fail select of G_INSERT non-32-bit sourceMatt Arsenault2019-09-161-4/+16
| | | | | | | This was producing an illegal copy which would hit an assert later. Error on selection for now until this is implemented. llvm-svn: 371993
* AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEILMatt Arsenault2019-09-161-0/+2
| | | | llvm-svn: 371991
* [X86][NFC] Add a `use-aa` feature.Clement Courbet2019-09-162-0/+8
| | | | | | | | | | | | | | | | | | Summary: This allows enabling useaa on the command-line and will allow enabling the feature on a per-CPU basis where benchmarking shows improvements. This is modelled after the ARM/AArch64 target. Reviewers: RKSimon, andreadb, craig.topper Subscribers: javed.absar, kristof.beyls, hiraditya, ychen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67266 llvm-svn: 371989
* [ARM] Fold VCMP into VPTDavid Green2019-09-162-18/+118
| | | | | | | | | | | | | | | MVE has VPT instructions, which perform the duties of both a VCMP and a VPST in a single instruction, performing the compare and starting the VPT block in one. This teaches the MVEVPTBlockPass to fold them, searching back through the basicblock for a valid VCMP and creating the VPT from its operands. There are some changes to the VPT instructions to accommodate this, altering the order of the operands to match the VCMP better, and changing P0 register defs to be VPR defs, as is used in other places. Differential Revision: https://reviews.llvm.org/D66577 llvm-svn: 371982
* [InstCombine] remove unneeded one-use checks for icmp foldSanjay Patel2019-09-161-4/+1
| | | | | | | | | | | | | | | | | | | | This fold and several others were added in: rL125734 <https://reviews.llvm.org/rL125734> ...with no explanation for the one-use checks other than the code comments about register pressure. Given that this is IR canonicalization, we shouldn't be worried about register pressure though; the backend should be able to adjust for that as needed. This is part of solving PR43310 the theoretically right way: https://bugs.llvm.org/show_bug.cgi?id=43310 ...ie, if we don't cripple basic transforms, then we won't need to add special-case code to detect larger patterns. rL371940 is a related patch in this series. llvm-svn: 371981
* [InstCombine] fix comments to match code; NFCSanjay Patel2019-09-161-25/+27
| | | | | | | | | | This blob was written before match() existed, so it could probably be reduced significantly. But I suspect it isn't well tested, so tests would have to be added to reduce risk from logic changes. llvm-svn: 371978
* [VPlanSLP] Don't dereference a cast_or_null<VPInstruction> result. NFCI.Simon Pilgrim2019-09-161-5/+8
| | | | | | The static analyzer is warning about a potential null dereference of the cast_or_null result, I've split the cast_or_null check from the ->getUnderlyingInstr() call to avoid this, but it appears that we weren't seeing any null pointers in the dumped bundles in the first place. llvm-svn: 371975
* [SLPVectorizer] Assert that we find a LastInst to silence analyzer null ↵Simon Pilgrim2019-09-161-0/+1
| | | | | | dereference warning. NFCI. llvm-svn: 371974
* [SLPVectorizer] Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-161-4/+4
| | | | | | The static analyzer is warning about potential null dereferences of dyn_cast<> results - in these cases we can safely use cast<> directly as we know that these cases should all be the correct type, which is why its working atm and anyway cast<> will assert if they aren't. llvm-svn: 371973
* [SVE][Inline-Asm] Add constraints for SVE predicate registersKerry McLaughlin2019-09-164-1/+53
| | | | | | | | | | | | | | | | | | | Summary: Adds the following inline asm constraints for SVE: - Upl: One of the low eight SVE predicate registers, P0 to P7 inclusive - Upa: SVE predicate register with full range, P0 to P15 Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened, rengolin Reviewed By: rovka Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66524 llvm-svn: 371967
* [AArch64] Some more FP16 FMA pattern matchingSjoerd Meijer2019-09-161-2/+19
| | | | | | | | | After our previous machinecombiner exercises (rL371321, rL371818, rL371833), we were still missing a few FP16 FMA patterns. Differential Revision: https://reviews.llvm.org/D67576 llvm-svn: 371960
* [SystemZ] Merge the SystemZExpandPseudo pass into SystemZPostRewrite.Jonas Paulsson2019-09-168-278/+175
| | | | | | | | | | | | | | | | | SystemZExpandPseudo:s only job was to expand LOCRMux instructions into jump sequences. This needs to be done if expandLOCRPseudo() or expandSELRPseudo() fails to find a legal opcode (all registers "high" or "low"). This task has now been moved to SystemZPostRewrite while removing the SystemZExpandPseudo pass. It is in fact preferred to expand these pseudos directly after register allocation in SystemZPostRewrite since the hinted register combinations are then not subject to later optimizations. Review: Ulrich Weigand https://reviews.llvm.org/D67432 llvm-svn: 371959
* AMDGPU/GlobalISel: Select SMRD loads for more typesMatt Arsenault2019-09-161-3/+12
| | | | llvm-svn: 371954
* AMDGPU/GlobalISel: RegBankSelect for killMatt Arsenault2019-09-161-0/+4
| | | | llvm-svn: 371953
* AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFPMatt Arsenault2019-09-161-1/+2
| | | | llvm-svn: 371952
* AMDGPU/GlobalISel: Set type on vgpr live in special argumentsMatt Arsenault2019-09-161-1/+2
| | | | | | | Fixes assertion with workitem ID intrinsics used in non-kernel functions. llvm-svn: 371951
* AMDGPU/GlobalISel: Select S16->S32 fptointMatt Arsenault2019-09-162-3/+3
| | | | llvm-svn: 371950
* AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFPMatt Arsenault2019-09-161-2/+2
| | | | llvm-svn: 371949
* AMDGPU/GlobalISel: Fix VALU s16 fnegMatt Arsenault2019-09-161-0/+10
| | | | llvm-svn: 371948
* [Attributor] Heap-To-Stack ConversionStefan Stipanovic2019-09-151-5/+259
| | | | | | | | | | | | D53362 gives a prototype heap-to-stack conversion pass. With addition of new attributes in the attributor, this can now be revisted and improved. This will place it in the Attributor to make it easier to use new attributes (eg. nofree, nosync, willreturn, etc.) and other attributor features. Reviewers: jdoerfert, uenoku, hfinkel, efriedma Subscribers: lebedev.ri, xbolva00, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D65408 llvm-svn: 371942
* [InstCombine] remove unneeded one-use checks for icmp foldSanjay Patel2019-09-151-3/+4
| | | | | | | | | | | | | | | | | | | | | | | This fold and several others were added in: rL125734 ...with no explanation for the one-use checks other than the code comments about register pressure. Given that this is IR canonicalization, we shouldn't be worried about register pressure though; the backend should be able to adjust for that as needed. There are similar checks as noted with the TODO comments. I'm hoping to remove those restrictions too, but if any of these does cause a regression, it should be easier to correct by making small, individual commits. This is part of solving PR43310 the theoretically right way: https://bugs.llvm.org/show_bug.cgi?id=43310 ...ie, if we don't cripple basic transforms, then we won't need to add special-case code to detect larger patterns. llvm-svn: 371940
* [GlobalISel] findGISelOptimalMemOpLowering - remove dead initalization. NFCI.Simon Pilgrim2019-09-151-3/+1
| | | | | | Fixes static analyzer warning that "Value stored to 'NewTySize' during its initialization is never read". llvm-svn: 371937
* [LoadStoreVectorizer] vectorizeLoadChain - ensure we find a valid Type down ↵Simon Pilgrim2019-09-151-1/+2
| | | | | | | | the load chain. NFCI. Silence static analyzer uninitialized variable warning by setting the LoadTy to null and then asserting we find a real value. llvm-svn: 371936
* InterleavedLoadCombine - merge isa<> and dyn_cast<> duplicates. NFCI.Simon Pilgrim2019-09-151-2/+2
| | | | | | Silence static analyzer null dereference warning of *dyn_cast<BinaryOperator> by merging with the isa<BinaryOperator> above. llvm-svn: 371935
* [DebugInfo] Don't dereference a dyn_cast<PDBSymbolData> result. NFCI.Simon Pilgrim2019-09-151-1/+1
| | | | | | The static analyzer is warning about a potential null dereference - but as we're in DataMemberLayoutItem we should be able to guarantee that the Symbol is a PDBSymbolData type, allowing us to use cast<PDBSymbolData> - and if not assert will fire for us. llvm-svn: 371933
* [ARM] Masked loads and storesDavid Green2019-09-154-0/+137
| | | | | | | | | | | | | | | | Masked loads and store fit naturally with MVE, the instructions being easily predicated. This adds lowering for the simple cases of masked loads and stores. It does not yet deal with widening/narrowing or pre/post inc, and so is currently behind an option. The llvm masked load intrinsic will accept a "passthru" value, dictating the values used for the zero masked lanes. In MVE the instructions write 0 to the zero predicated lanes, so we need to match a passthru that isn't 0 (or undef) with a select instruction to pull in the correct data after the load. Differential Revision: https://reviews.llvm.org/D67186 llvm-svn: 371932
* [SLP] limit vectorization of Constant subclasses (PR33958)Sanjay Patel2019-09-151-2/+5
| | | | | | | | | | | | | | This is a fix for: https://bugs.llvm.org/show_bug.cgi?id=33958 It seems universally true that we would not want to transform this kind of sequence on any target, but if that's not correct, then we could view this as a target-specific cost model problem. We could also white-list ConstantInt, ConstantFP, etc. rather than blacklist Global and ConstantExpr. Differential Revision: https://reviews.llvm.org/D67362 llvm-svn: 371931
* [TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support.Simon Pilgrim2019-09-141-0/+15
| | | | | | Call SimplifyDemandedBits on the source vector. llvm-svn: 371923
* [InstSimplify] simplifyUnsignedRangeCheck(): handle few tautological cases ↵Roman Lebedev2019-09-141-16/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | (PR43251) Summary: This is split off from D67356, since these cases produce a constant, no real need to keep them in instcombine. Alive proofs: https://rise4fun.com/Alive/u7Fk https://rise4fun.com/Alive/4lV https://bugs.llvm.org/show_bug.cgi?id=43251 Reviewers: spatel, nikic, xbolva00 Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67498 llvm-svn: 371921
* [ScheduleDAGMILive] Fix typo in comment.Mingjie Xing2019-09-141-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D67478 llvm-svn: 371916
* [Attributor][Fix] Use right type to replace expressionsJohannes Doerfert2019-09-141-3/+8
| | | | | | | | | | | | | | Summary: This should be obsolete once the functionality in D66967 is integrated. Reviewers: uenoku, sstefan1 Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67231 llvm-svn: 371915
* [Reproducer] Add reproducer dump command.Jonas Devlieghere2019-09-131-10/+12
| | | | | | | | | | | This adds a reproducer dump commands which makes it possible to inspect a reproducer from inside LLDB. Currently it supports the Files, Commands and Version providers. I'm planning to add support for the GDB Remote provider in a follow-up patch. Differential revision: https://reviews.llvm.org/D67474 llvm-svn: 371909
* [WebAssembly] Narrowing and widening SIMD opsThomas Lively2019-09-131-0/+36
| | | | | | | | | | | | | | | | Summary: Implements target-specific LLVM intrinsics and clang builtins for these new SIMD operations, as described at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67425 llvm-svn: 371906
* [GlobalISel] Fix insertion point of new instructions to be after PHIs.Amara Emerson2019-09-131-3/+3
| | | | | | | | | | For some reason we sometimes insert new instructions one instruction before the first non-PHI when legalizing. This can result in having non-PHI instructions before PHIs, which mean that PHI elimination doesn't catch them. Differential Revision: https://reviews.llvm.org/D67570 llvm-svn: 371901
* Add dependency from Orc to PassesSanjoy Das2019-09-131-2/+2
| | | | | | | | | | | | | | Summary: Orc uses registerFunctionAnalyses that's defined in Passes. Reviewers: dblaikie Subscribers: mcrosier, bixia, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67477 llvm-svn: 371898
* [AArch64][GlobalISel] Tail call memory intrinsicsJessica Paquette2019-09-132-1/+46
| | | | | | | | | | | | | | | | | | | | | | Because memory intrinsics are handled differently than other calls, we need to check them for tail call eligiblity in the legalizer. This allows us to still inline them when it's beneficial to do so, but also tail call when possible. This adds simple tail calling support for when the intrinsic is followed by a return. It ports the attribute checks from `TargetLowering::isInTailCallPosition` into a similarly-named function in LegalizerHelper.cpp. The target-specific `isUsedByReturnOnly` hook is not ported here. Update tailcall-mem-intrinsics.ll to show that GlobalISel can now tail call memory intrinsics. Update legalize-memcpy-et-al.mir to have a case where we don't tail call. Differential Revision: https://reviews.llvm.org/D67566 llvm-svn: 371893
* [Support] Add overload writeFileAtomically(std::function Writer)Jan Korous2019-09-132-30/+65
| | | | | | Differential Revision: https://reviews.llvm.org/D67424 llvm-svn: 371890
* [aarch64] move custom isel of extract_vector_elt to td file - NFCSebastian Pop2019-09-132-43/+10
| | | | | | | | | | | | | | | | | | | In preparation for def-pat selection of dot product instructions, this patch moves the custom instruction selection of extract_vector_elt to the td file. Without this change it is impossible to catch a pattern that starts with an extract_vector_elt: the custom cpp code is executed first ahead of the patterns in the td files that are only executed at the end of the switch statement in SelectCode(Node). With this patch applied, it becomes possible to select a different pattern that starts with extract_vector_elt by selecting a higher complexity than this pattern. The patch has been tested on aarch64-linux with make check-all. Differential Revision: https://reviews.llvm.org/D67497 llvm-svn: 371887
* AArch64: fix EXPENSIVE_CHECKS for arm64_32.Tim Northover2019-09-131-1/+1
| | | | | | | For some reason I'd decided to mark the end-result of a GOT load as dead. It's clearly not (necessarily). llvm-svn: 371883
* Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-134-64/+19
| | | | llvm-svn: 371873
* [AArch64][GlobalISel] Add support for sibcalling callees with varargsJessica Paquette2019-09-131-6/+19
| | | | | | | | | | | | | | | This adds support for tail calling callees with varargs, equivalent to how it is done in AArch64ISelLowering. This only works for sibling calls, and does not add the necessary support for musttail with varargs. (See r345641 for equivalent ISelLowering support.) This should be implemented when we stop falling back on musttail. Update call-translator-tail-call.ll to show that we can now tail call varargs. Differential Revision: https://reviews.llvm.org/D67518 llvm-svn: 371868
* [yaml2obj/ObjectYAML] - Cleanup the error reporting API, add custom errors ↵George Rimar2019-09-136-298/+258
| | | | | | | | | | | | | | | | | | | | | handlers. This is a continuation of the YAML library error reporting refactoring/improvement and the idea by itself was mentioned in the following thread: https://reviews.llvm.org/D67182?id=218714#inline-603404 This performs a cleanup of all object emitters in the library. It allows using the custom one provided by the caller. One of the nice things is that each tool can now print its tool name, e.g: "yaml2obj: error: <text>" Also, the code became a bit simpler. Differential revision: https://reviews.llvm.org/D67445 llvm-svn: 371865
* [X86] Use incDecVectorConstant to simplify the min/max code in LowerVSETCC.Craig Topper2019-09-131-14/+12
| | | | | | | incDecVectorConstant is used for a similar reason in LowerVSETCCWithSUBUS so we might as well share the code. llvm-svn: 371861
* [Orc] Roll back ThreadPool to std::functionBenjamin Kramer2019-09-131-1/+3
| | | | | | MSVC doesn't allow move-only types in std::packaged_task. Boo. llvm-svn: 371844
* [Orc] Address the remaining move-capture FIXMEsBenjamin Kramer2019-09-135-24/+18
| | | | | | | This required spreading unique_function a bit more, which I think is a good thing. llvm-svn: 371843
* [X86] negateFMAOpcode - extend to support FMADDSUB/FMSUBADD and output ↵Simon Pilgrim2019-09-131-27/+40
| | | | | | | | | | negation. NFCI. Some prep work for PR42863, this change allows us to move all the FMA opcode mappings into the negateFMAOpcode helper. For the FMADDSUB/FMSUBADD cases, we can only negate the accumulator - any other negations will result in an error. llvm-svn: 371840
* [ARM] Add earlyclobber for cross beat MVE instructionsDavid Green2019-09-131-40/+39
| | | | | | | | | | | | | | | | | | | | | | | | | rL367544 added @earlyclobbers for the MVE VREV64 instruction. This adds the same for a number of other 32bit instructions that are similarly unpredictable if the destination equals the source (due to the cross beat nature of the instructions). This includes: VCADD.f32 VCADD.i32 VCMUL.f32 VHCADD.s32 VMULLT/B.s/u32 VQDMLADH{X}.s32 VQRDMLADH{X}.s32 VQDMLSDH{X}.s32 VQRDMLSDH{X}.s32 VQDMULLT/B.s32 with Qm and Rm No tests here as this would require intrinsics (or very interesting codegen) to manifest. The tests will follow naturally as the intrinsics are added. Differential Revision: https://reviews.llvm.org/D67462 llvm-svn: 371838
* [Alignment] Introduce llvm::Align to MCSectionGuillaume Chatelet2019-09-138-20/+23
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, JDevlieghere Subscribers: arsenm, sdardis, jvesely, nhaehnle, sbc100, hiraditya, aheejin, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67486 llvm-svn: 371831
* [lib/ObjectYAML] - Change interface to return `bool` instead of `int`. NFCIGeorge Rimar2019-09-136-31/+29
| | | | | | | | It was suggested in comments for D67445 to split this part. Differential revision: https://reviews.llvm.org/D67488 llvm-svn: 371828
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