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* [DebugInfo][NFCI] Split salvageDebugInfo into helper functionsJeremy Morse2019-02-051-82/+82
| | | | | | | | | | | | | | | Some use cases are appearing where salvaging is needed that does not correspond to an instruction being deleted -- for example an instruction being sunk, or a Value not being available in a block being isel'd. Enable more fine grained control over how salavging occurs by splitting the logic into helper functions, separating things that are specific to working on DbgVariableIntrinsics from those specific to interpreting IR and building DIExpressions. Differential Revision: https://reviews.llvm.org/D57696 llvm-svn: 353156
* [X86][AVX] Attempt to share broadcasts of different widths (PR39454)Simon Pilgrim2019-02-051-0/+8
| | | | | | | | If we have broadcasts of different vector widths, keep the longest vector width and extract subvectors for the shorter vectors (which should be free). Differential Revision: https://reviews.llvm.org/D57663 llvm-svn: 353154
* [CGP] Add support for sinking operands to their users, if they are free.Florian Hahn2019-02-053-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch improves code generation for some AArch64 ACLE intrinsics. It adds support to CGP to duplicate and sink operands to their user, if they can be folded into a target instruction, like zexts and sub into usubl. It adds a TargetLowering hook shouldSinkOperands, which looks at the operands of instructions to see if sinking is profitable. I decided to add a new target hook, as for the sinking to be profitable, at least on AArch64, we have to look at multiple operands of an instruction, instead of looking at the users of a zext for example. The sinking is done in CGP, because it works around an instruction selection limitation. If instruction selection is not limited to a single basic block, this patch should not be needed any longer. Alternatively this could be done in the LoopSink pass, which tries to undo LICM for instructions in blocks that are not executed frequently. Note that we do not force the operands to sink to have a single user, because we duplicate them before sinking. Therefore this is only desirable if they really can be done for free. Additionally we could consider the impact on live ranges later on. This should fix https://bugs.llvm.org/show_bug.cgi?id=40025. As for performance, we have internal code that uses intrinsics and can be speed up by 10% by this change. Reviewers: SjoerdMeijer, t.p.northover, samparker, efriedma, RKSimon, spatel Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D57377 llvm-svn: 353152
* [ARM GlobalISel] Support G_GEP for Thumb2Diana Picus2019-02-052-3/+3
| | | | | | Same as ARM, but use a different opcode in the instruction selection. llvm-svn: 353151
* [NFC] fix trivial typos in commentsHiroshi Inoue2019-02-058-13/+13
| | | | llvm-svn: 353147
* [DAG] BaseIndexOffset: FrameIndexSDNodes with the same FrameIndex compare equal.Clement Courbet2019-02-051-5/+9
| | | | | | | | | | | | Reviewers: niravd Subscribers: arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57692 llvm-svn: 353143
* [X86] Connect the default fpsr and dirflag clobbers in inline assembly to ↵Craig Topper2019-02-052-1/+9
| | | | | | | | | | | | | | | | | | | | | the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 llvm-svn: 353141
* [LSR] Check SCEV on isZero() after extend. PR40514Max Kazantsev2019-02-051-3/+21
| | | | | | | | | | | | | | | | | | | | | When LSR first adds SCEVs to BaseRegs, it only does it if `isZero()` has returned false. In the end, in invocation of `InsertFormula`, it asserts that all values there are still not zero constants. However between these two points, it makes some transformations, in particular extends them to wider type. SCEV does not give us guarantee that if `S` is not a constant zero, then `sext(S)` is also not a constant zero. It might have missed some optimizing transforms when it was calculating `S` and then made them when it took `sext`. For example, it may happen if previously optimizing transforms were limited by depth or somehow else. This patch adds a bailout when we may end up with a zero SCEV after extension. Differential Revision: https://reviews.llvm.org/D57565 Reviewed By: samparker llvm-svn: 353136
* [SamplePGO] More pipeline changes when flattened profile used in ThinLTO ↵Teresa Johnson2019-02-051-20/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | postlink Summary: Follow on to D54819/r351476. We also don't need to perform extra InstCombine pass when we aren't loading the sample profile in the ThinLTO backend because we have a flattened sample profile. Additionally, for consistency and clarity, when we aren't reloading the sample profile, perform ICP in the same location as non-sample PGO backends. To this end I have moved the ICP invocation for non-SamplePGO ThinLTO down into buildModuleSimplificationPipeline (partly addresses the FIXME where we were previously setting this up). Reviewers: wmi Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57705 llvm-svn: 353135
* Fix narrowing issue from r353129Richard Trieu2019-02-051-1/+2
| | | | llvm-svn: 353134
* [WebAssembly] Fix indentation after adding IsCanonical property (NFC)Heejin Ahn2019-02-052-11/+11
| | | | llvm-svn: 353132
* [WebAssembly] Make disassembler always emit most canonical name.Wouter van Oortmerssen2019-02-054-11/+22
| | | | | | | | | | | | | | | | | | | | | Summary: There are a few instructions that all map to the same opcode, so when disassembling, we have to pick one. That was just the first one before (the except_ref variant in the case of "call"), now it is the one marked as IsCanonical in tablegen, or failing that, the shortest name (which is typically the "canonical" one). Also introduced a canonical "end" instruction for this purpose. Reviewers: dschuff, tlively Subscribers: sbc100, jgravelle-google, aheejin, llvm-commits, sunfish Tags: #llvm Differential Revision: https://reviews.llvm.org/D57713 llvm-svn: 353131
* [SamplePGO][NFC] Minor improvement to replace a temporary vector with aWei Mi2019-02-051-3/+2
| | | | | | | | brace-enclosed init list. Differential Revision: https://reviews.llvm.org/D57726 llvm-svn: 353129
* GlobalISel: Fix verifier crashing on non-register operandsMatt Arsenault2019-02-051-1/+6
| | | | | | Also correct the wording of error on subregisters. llvm-svn: 353128
* [WebAssembly] memory.copyThomas Lively2019-02-056-0/+66
| | | | | | | | | | | | Summary: Depends on D57495. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57498 llvm-svn: 353127
* GlobalISel: Consolidate load/store legalizationMatt Arsenault2019-02-051-103/+14
| | | | | | | | | | The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
* [DAGCombiner] Discard pointer info when combining extract_vector_elt of a ↵Craig Topper2019-02-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | vector load when the index isn't constant Summary: If the index isn't constant, this transform inserts a multiply and an add on the index to calculating the base pointer for a scalar load. But we still create a memory operand with an offset of 0 and the size of the scalar access. But the access is really to an unknown offset within the original access size. This can cause the machine scheduler to incorrectly calculate dependencies between this load and other accesses. In the case we saw, there was a 32 byte vector store that was split into two 16 byte stores, one with offset 0 and one with offset 16. The size of the memory operand for both was 16. The scheduler correctly detected the alias with the offset 0 store, but not the offset 16 store. This patch discards the pointer info so we don't incorrectly detect aliasing. I wasn't sure if we could keep using the original offset and size without risking some other transform on the load changing the size. I tried to reduce a test case, but there's still a lot of memory operations needed to get the scheduler to do the bad reordering. So it looked pretty fragile to maintain. Reviewers: efriedma Reviewed By: efriedma Subscribers: arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57616 llvm-svn: 353124
* [SamplePGO] Minor efficiency improvement in samplePGO ICPTeresa Johnson2019-02-051-3/+3
| | | | | | | | | | | | | | | | | | | | Summary: When attaching prof metadata to promoted direct calls in SamplePGO mode, no need to construct and use a SmallVector to pass a single count to the ArrayRef parameter, we can simply use a brace-enclosed init list. This made a small but consistent improvement for a ThinLTO backend compile I was measuring. Reviewers: wmi Subscribers: mehdi_amini, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57706 llvm-svn: 353123
* GlobalISel: Implement narrowScalar for selectMatt Arsenault2019-02-051-0/+53
| | | | | | | | | | Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
* GlobalISel: Combine g_extract with g_merge_valuesMatt Arsenault2019-02-041-0/+1
| | | | | | | | | | | | | | Try to use the underlying source registers. This enables legalization in more cases where some irregular operations are widened and others narrowed. This seems to make the test_combines_2 AArch64 test worse, since the MERGE_VALUES has multiple uses. Since this should be required for legalization, a hasOneUse check is probably inappropriate (or maybe should only be used if the merge is legal?). llvm-svn: 353121
* Revert "[PATCH] [TargetLibraryInfo] Update run time support for Windows"Evandro Menezes2019-02-041-59/+53
| | | | | | This reverts accidental commit ff5527718d5d3b9966f6e8948866c0dc15ffcf3c. llvm-svn: 353118
* [PATCH] [TargetLibraryInfo] Update run time support for WindowsEvandro Menezes2019-02-041-53/+59
| | | | | | | | | | | | | It seems that the run time for Windows has changed and supports more math functions than before. Since LLVM requires at least VS2015, I assume that this is the run time that would be redistributed with programs built with Clang. Thus, I based this update on the header file `math.h` that accompanies it. This patch addresses the PR40541. Unfortunately, I have no access to a Windows development environment to validate it. llvm-svn: 353114
* GlobalISel: Enforce operand types for constantsMatt Arsenault2019-02-041-0/+23
| | | | | | | | A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
* GlobalISel: Verify g_selectMatt Arsenault2019-02-041-24/+40
| | | | | | | Factor the common vector element consistency check many instructions need out, although this makes the error messages worse. llvm-svn: 353112
* MachineVerifier: Move verification of G_* instructions to functionMatt Arsenault2019-02-041-100/+117
| | | | llvm-svn: 353111
* [WebAssembly] MC: Mark more function aliases as functionsSam Clegg2019-02-041-1/+11
| | | | | | | | | | | | | Aliases of functions are now marked as function symbols even if they are bitcast to some other other non-function type. This is important for WebAssembly where object and function symbols can't alias each other. Fixes PR38866 Differential Revision: https://reviews.llvm.org/D57538 llvm-svn: 353109
* MIR: Validate LLT types when parsingMatt Arsenault2019-02-041-6/+35
| | | | llvm-svn: 353107
* GlobalISel: Fix not calling observer when legalizing bitcount opsMatt Arsenault2019-02-041-11/+12
| | | | | | This was hiding bugs from never legalizing the source type. llvm-svn: 353102
* AMDGPU: Don't rematerialize mov with implicit operandsMatt Arsenault2019-02-041-1/+2
| | | | | | | This was pulling the mov used for register indexing on gfx9 out of the loop. llvm-svn: 353101
* [SanitizerCoverage] Clang crashes if user declares `__sancov_lowest_stack` ↵Julian Lettner2019-02-041-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | variable Summary: If the user declares or defines `__sancov_lowest_stack` with an unexpected type, then `getOrInsertGlobal` inserts a bitcast and the following cast fails: ``` Constant *SanCovLowestStackConstant = M.getOrInsertGlobal(SanCovLowestStackName, IntptrTy); SanCovLowestStack = cast<GlobalVariable>(SanCovLowestStackConstant); ``` This variable is a SanitizerCoverage implementation detail and the user should generally never have a need to access it, so we emit an error now. rdar://problem/44143130 Reviewers: morehouse Differential Revision: https://reviews.llvm.org/D57633 llvm-svn: 353100
* [InstCombine] Cleanup the TFE/LWE check in AMDGPU SimplifyDemandedNicolai Haehnle2019-02-042-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The fix added in r352904 is not quite correct, or rather misleading: 1. When the texfailctrl (TFC) argument was non-constant, the fix assumed non-TFE/LWE, which is incorrect. 2. Regardless, this code path cannot even be hit for correct TFE/LWE-enabled calls, because those return a struct. Added a test case for those for completeness. Change-Id: I92d314dbc67a2670f6d7adaab765ef45f56a49cf Reviewers: hliao, dstuttard, arsenm Subscribers: kzhuravl, jvesely, wdng, yaxunl, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57681 llvm-svn: 353097
* [CodeGen][ARC][SystemZ][WebAssembly] Use MachineInstr::isInlineAsm in more ↵Craig Topper2019-02-044-7/+7
| | | | | | | | | | places instead of just comparing opcode. NFCI I'm looking at adding a second INLINEASM opcode for better modeling asm-goto as a terminator. Using the existing predicate will reduce teh number of places that will need to use the new opcode. llvm-svn: 353095
* [NewPM][MSan] Add Options HandlingPhilip Pfaffe2019-02-043-21/+50
| | | | | | | | | | | | | | Summary: This patch enables passing options to msan via the passes pipeline, e.e., -passes=msan<recover;kernel;track-origins=4>. Reviewers: chandlerc, fedor.sergeev, leonardchan Subscribers: hiraditya, bollu, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57640 llvm-svn: 353090
* [DEBUGINFO] Reposting r352642: Handle restore instructions in LiveDebugValuesWolfgang Pieb2019-02-043-92/+216
| | | | | | | | | | | | | | | | | The LiveDebugValues pass recognizes spills but not restores, which can cause large gaps in location information for some variables, depending on control flow. This patch make LiveDebugValues recognize restores and generate appropriate DBG_VALUE instructions. This patch was posted previously with r352642 and reverted in r352666 due to buildbot errors. A missing return statement was the cause for the failures. Reviewers: aprantl, NicolaPrica Differential Revision: https://reviews.llvm.org/D57271 llvm-svn: 353089
* [AMDGPU] Support emitting GOT relocations for function callsScott Linder2019-02-043-41/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D57416 llvm-svn: 353083
* [WarnMissedTransforms] Do not warn about already vectorized loops.Michael Kruse2019-02-041-7/+7
| | | | | | | | | | | | | LoopVectorize adds llvm.loop.isvectorized, but leaves llvm.loop.vectorize.enable. Do not consider such a loop for user-forced vectorization since vectorization already happened -- by prioritizing llvm.loop.isvectorized except for TM_SuppressedByUser. Fixes http://llvm.org/PR40546 Differential Revision: https://reviews.llvm.org/D57542 llvm-svn: 353082
* GlobalISel: Fix CSE handling of buildConstantMatt Arsenault2019-02-042-40/+51
| | | | | | | | | | | | | | | | This fixes two problems with CSE done in buildConstant. First, this would hit an assert when used with a vector result type. Solve this by allowing CSE on the vector elements, but not on the result vector for now. Second, this was also performing the CSE based on the input ConstantInt pointer. The underlying buildConstant could potentially convert the constant depending on the result type, giving in a different ConstantInt*. Stop allowing the APInt and ConstantInt forms from automatically casting to the result type to avoid any similar problems in the future. llvm-svn: 353077
* [WebAssembly] clang-tidy (NFC)Heejin Ahn2019-02-0441-500/+483
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch fixes clang-tidy warnings on wasm-only files. The list of checks used is: `-*,clang-diagnostic-*,llvm-*,misc-*,-misc-unused-parameters,readability-identifier-naming,modernize-*` (LLVM's default .clang-tidy list is the same except it does not have `modernize-*`. But I've seen in multiple CLs in LLVM the modernize style was recommended and code was fixed based on the style, so I added it as well.) The common fixes are: - Variable names start with an uppercase letter - Function names start with a lowercase letter - Use `auto` when you use casts so the type is evident - Use inline initialization for class member variables - Use `= default` for empty constructors / destructors - Use `using` in place of `typedef` Reviewers: sbc100, tlively, aardappel Subscribers: dschuff, sunfish, jgravelle-google, yurydelendik, kripken, MatzeB, mgorny, rupprecht, llvm-commits Differential Revision: https://reviews.llvm.org/D57500 llvm-svn: 353075
* [X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bitsRoman Lebedev2019-02-041-17/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
* Adjust cardinality of internal inliner thresholdsDavid Callahan2019-02-041-4/+4
| | | | | | | | | | | | | | | | | | | Summary: While compiling openJDK11 (also other workloads), some make files would pass both CFLAGS and LDFLAGS at link step ; resulting in duplicate options on the command line when one is using LTO and trying to influence the inliner. Most of the internal flags are ZeroOrMore, this diff changes the remaining ones. Reviewers: david2050, twoh, modocache Reviewed By: twoh Subscribers: mehdi_amini, dexonsmith, eraman, haicheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57537 Patch by: Abdoul-Kader Keita llvm-svn: 353071
* [X86] Add ST0 as an implicit def/use of x87 load/store instructions during ↵Craig Topper2019-02-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | FP stackifying. These instructions implicitly operate on ST0, but we don't currently add that information to the MachineInstr. We also don't add it the tablegen definitions either. For the most part this doesn't cause any problems because the stackifying occurs after register allocation. All the instructions are marked as having side effects so the postRA scheduler won't reorder them amongst themselves. But nothing stops inline assembly using X87 instructions from being reordered around other x87 instructions if that inline assembly wasn't marked volatile. The two test cases I've identified so far in PR40539 involve loads and stores used to set up the inline assembly or capture the results of the inline assembly ending up in the wrong order. This patch adds implicit ST0 uses/defs to the load/store instructions to prevent this from happening. I plan to fix all of the FP instructions, but the binops are bit trickier to get right. So I've chosen fixing the known test cases as a good first step. I think we also need to update the tablegen descriptions so MS inline assembly infers the right clobbers, but I haven't checked that yet. Differential Revision: https://reviews.llvm.org/D57644 llvm-svn: 353070
* GlobalISel: Fix moreElementsToNextPow2Matt Arsenault2019-02-042-8/+7
| | | | | | | | | This was completely broken. The condition was inverted, and changed the element type for vectors of pointers. Fixes bug 40592. llvm-svn: 353069
* [WebAssembly] Make segment/size/type directives optional in asmWouter van Oortmerssen2019-02-042-5/+44
| | | | | | | | | | | | | | | | | | | | Summary: These were "boilerplate" that repeated information already present in .functype and end_function, that needed to be repeated to Please the particular way our object writing works, and missing them would generate errors. Instead, we generate the information for these automatically so the user can concern itself with writing more canonical wasm functions that always work as expected. Reviewers: dschuff, sbc100 Subscribers: jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D57546 llvm-svn: 353067
* Revert "[GlobalISel] Add IRTranslator support for G_FFLOOR"Jessica Paquette2019-02-041-5/+0
| | | | | | | | | This reverts commit 8bbd570fd5205a04d88d2e5513a6e4adbd028039. Apparently adding ffloor breaks AMDGPU somehow, so I need to back this out while I look into it. llvm-svn: 353064
* [WebAssembly] Rename relocations from R_WEBASSEMBLY_ to R_WASM_Sam Clegg2019-02-043-61/+61
| | | | | | | | | | | | | | | | See https://github.com/WebAssembly/tool-conventions/pull/95. This is less typing and IMHO more readable, and it also fits with our naming around the binary format which tends to use the short name. e.g. include/llvm/BinaryFormat/Wasm.h tools/llvm-objdump/WasmDump.cpp etc.. Differential Revision: https://reviews.llvm.org/D57611 llvm-svn: 353062
* [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two ↵Craig Topper2019-02-042-42/+44
| | | | | | | | | | arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. llvm-svn: 353061
* [Intrinsic] Unsigned Fixed Point Multiplication IntrinsicLeonard Chan2019-02-0410-44/+106
| | | | | | | | | | | | | Add an intrinsic that takes 2 unsigned integers with the scale of them provided as the third argument and performs fixed point multiplication on them. This is a part of implementing fixed point arithmetic in clang where some of the more complex operations will be implemented as intrinsics. Differential Revision: https://reviews.llvm.org/D55625 llvm-svn: 353059
* [GlobalISel] Add IRTranslator support for G_FFLOORJessica Paquette2019-02-041-0/+5
| | | | | | | | | | Follow-up to https://reviews.llvm.org/D57484 Adds G_FFLOOR to translateKnownIntrinsic and update arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D57485 llvm-svn: 353058
* [CGP] use IRBuilder to simplify codeSanjay Patel2019-02-041-26/+25
| | | | | | | | | | | | | | | | This is no-functional-change-intended although there could be intermediate variations caused by a difference in the debug info produced by setting that from the builder's insertion point. I'm updating the IR test file associated with this code just to show that the naming differences from using the builder are visible. The motivation for adding a helper function is that we are likely to extend this code to deal with other overflow ops. llvm-svn: 353056
* [CommandLine] Don't print empty sentinel values from EnumValN lists in help textJames Henderson2019-02-041-16/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make an option value truly optional, both the ValueOptional attribute and an empty-named value are required. Prior to this change, this empty-named value appears in the command-line help text: -some-option - some help text =v1 - description 1 =v2 - description 2 = - This change improves the help text for these sort of options in a number of ways: 1) ValueOptional options with an empty-named value now print their help text twice: both without and then with '=<value>' after the name. The latter version then lists the allowed values after it. 2) Empty-named values with no help text in ValueOptional options are not listed in the permitted values. -some-option - some help text -some-option=<value> - some help text =v1 - description 1 =v2 - description 2 3) Otherwise empty-named options are printed as =<empty> rather than simply '='. 4) Option values without help text do not have the '-' separator printed. -some-option=<value> - some help text =v1 - description 1 =v2 =<empty> - description It also tweaks the llvm-symbolizer -functions help text to not print a trailing ':' as that looks bad combined with 1) above. This is mostly a reland of r353048 which in turn was a reland of r352750. Reviewed by: ruiu, thopre, mstorsjo Differential Revision: https://reviews.llvm.org/D57030 llvm-svn: 353053
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