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* Insert modified DBG_VALUE into LiveDbgValueMap. Devang Patel2011-11-151-1/+1
| | | | llvm-svn: 144696
* Fix typo.Jim Grosbach2011-11-151-1/+1
| | | | llvm-svn: 144695
* ARM alternate size suffices for VTRN instructions.Jim Grosbach2011-11-151-0/+16
| | | | | | rdar://10435076 llvm-svn: 144694
* Fix a misplaced paren bug.Owen Anderson2011-11-151-1/+1
| | | | llvm-svn: 144692
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-151-0/+11
| | | | | | Yet more of rdar://10435076. llvm-svn: 144691
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+6
| | | | | | rdar://10449856. llvm-svn: 144689
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+4
| | | | | | Ongoing rdar://10435114. llvm-svn: 144688
* Thumb2 two-operand 'mul' instruction wide encoding parsing.Jim Grosbach2011-11-152-0/+19
| | | | | | rdar://10449724 llvm-svn: 144684
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and ↵Owen Anderson2011-11-152-8/+66
| | | | | | VMOVv4f32. llvm-svn: 144683
* Thumb2 assembly parsing for mul.w in IT block fix.Jim Grosbach2011-11-151-0/+1
| | | | | | | | | | When the 3rd operand is not a low-register, and the first two operands are the same low register, the parser was incorrectly trying to use the 16-bit instruction encoding. rdar://10449281 llvm-svn: 144679
* StringRefize and simplify.Benjamin Kramer2011-11-152-13/+10
| | | | llvm-svn: 144675
* We currently use a callback to handle an IL pass deleting a BB that stillRafael Espindola2011-11-151-0/+12
| | | | | | | | | | | has a reference to it. Unfortunately, that doesn't work for codegen passes since we don't get notified of MBB's being deleted (the original BB stays). Use that fact to our advantage and after printing a function, check if any of the IL BBs corresponds to a symbol that was not printed. This fixes pr11202. llvm-svn: 144674
* Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka2011-11-152-18/+24
| | | | | | registers and instructions when ABI is N64. llvm-svn: 144666
* Set nomacro before emitting the sequence of instructions that set global pointerAkira Hatanaka2011-11-151-3/+2
| | | | | | register. llvm-svn: 144665
* Simplify function PassByValArg64.Akira Hatanaka2011-11-151-14/+18
| | | | llvm-svn: 144664
* Remove function printMipsSymbolRef.Akira Hatanaka2011-11-151-35/+0
| | | | llvm-svn: 144663
* Remove Value::getNameStr. It has been deprecated for a while and provides no ↵Benjamin Kramer2011-11-151-4/+0
| | | | | | additional value over getName(). llvm-svn: 144657
* Missed some users of Value::getNameStr.Benjamin Kramer2011-11-151-4/+2
| | | | llvm-svn: 144656
* Delete files.Akira Hatanaka2011-11-152-137/+0
| | | | llvm-svn: 144655
* Remove MipsMCSymbolRefExpr.Akira Hatanaka2011-11-152-2/+0
| | | | llvm-svn: 144654
* ARM parsing datatype suffix variants for register-writeback VLD1/VST1 ↵Jim Grosbach2011-11-151-0/+78
| | | | | | | | instructions. rdar://10435076 llvm-svn: 144650
* Tidy up. 80 columns.Jim Grosbach2011-11-155-28/+34
| | | | llvm-svn: 144649
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-1522-61/+63
| | | | llvm-svn: 144648
* Twinify GraphWriter a little bit.Benjamin Kramer2011-11-155-11/+11
| | | | llvm-svn: 144647
* Check all overlaps when looking for used registers.Jakob Stoklund Olesen2011-11-151-4/+5
| | | | | | A function using any RC alias is enough to enable the ExeDepsFix pass. llvm-svn: 144636
* Make use of MachinePointerInfo::getFixedStack.Jay Foad2011-11-151-2/+1
| | | | llvm-svn: 144635
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-157-7/+0
| | | | llvm-svn: 144634
* Fix typo in comment.Jay Foad2011-11-151-1/+1
| | | | llvm-svn: 144633
* Make use of MachinePointerInfo::getFixedStack. This removes all mentionJay Foad2011-11-155-24/+10
| | | | | | of PseudoSourceValue from lib/Target/. llvm-svn: 144632
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-158-8/+0
| | | | llvm-svn: 144631
* Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 ↵Craig Topper2011-11-151-9/+17
| | | | | | 256-bit integer instructions when AVX2 isn't enabled. llvm-svn: 144629
* Set SeenStore to true to prevent loads from being moved; also eliminates a ↵Evan Cheng2011-11-151-2/+2
| | | | | | non-deterministic behavior. llvm-svn: 144628
* Rather than trying to use the loop block sequence *or* the functionChandler Carruth2011-11-151-27/+24
| | | | | | | | | | | | | | | | | | | | | | | block sequence when recovering from unanalyzable control flow constructs, *always* use the function sequence. I'm not sure why I ever went down the path of trying to use the loop sequence, it is fundamentally not the correct sequence to use. We're trying to preserve the incoming layout in the cases of unreasonable control flow, and that is only encoded at the function level. We already have a filter to select *exactly* the sub-set of blocks within the function that we're trying to form into a chain. The resulting code layout is also significantly better because of this. In several places we were ending up with completely unreasonable control flow constructs due to the ordering chosen by the loop structure for its internal storage. This change removes a completely wasteful vector of basic blocks, saving memory allocation in the common case even though it costs us CPU in the fairly rare case of unnatural loops. Finally, it fixes the latest crasher reduced out of GCC's single source. Thanks again to Benjamin Kramer for the reduction, my bugpoint skills failed at it. llvm-svn: 144627
* Properly qualify AVX2 specific parts of execution dependency table. Also ↵Craig Topper2011-11-152-9/+16
| | | | | | enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. llvm-svn: 144622
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-153-0/+28
| | | | | | integer variants. rdar://10437054 llvm-svn: 144608
* ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.Jim Grosbach2011-11-151-3/+66
| | | | | | rdar://10435076 llvm-svn: 144606
* Move WEAK marking to the declaration.Nick Lewycky2011-11-151-6/+6
| | | | llvm-svn: 144603
* Break false dependencies before partial register updates.Jakob Stoklund Olesen2011-11-153-0/+84
| | | | | | | | | | | | | | Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix about instructions with partial register updates causing false unwanted dependencies. The ExecutionDepsFix pass will break the false dependencies if the updated register was written in the previoius N instructions. The small loop added to sse-domains.ll runs twice as fast with dependency-breaking instructions inserted. llvm-svn: 144602
* Track register ages more accurately.Jakob Stoklund Olesen2011-11-151-101/+184
| | | | | | | | | | | | | | | Keep track of the last instruction to define each register individually instead of per DomainValue. This lets us track more accurately when a register was last written. Also track register ages across basic blocks. When entering a new basic block, use the least stale predecessor def as a worst case estimate for register age. The register age is used to arbitrate between conflicting domains. The most recently defined register wins. llvm-svn: 144601
* Fix linking for some users who already have tsan enabled code and are trying toNick Lewycky2011-11-151-6/+6
| | | | | | link it against llvm code, by making our definitions weak. "Some users." llvm-svn: 144596
* ARM parsing datatype suffix variants for non-writeback VST1 instructions.Jim Grosbach2011-11-141-0/+44
| | | | | | rdar://10435076 llvm-svn: 144593
* ARM parsing datatype suffix variants for non-writeback VLD1 instructions.Jim Grosbach2011-11-141-0/+41
| | | | | | rdar://10435076 llvm-svn: 144592
* Add explanatory comment.Jim Grosbach2011-11-141-0/+1
| | | | llvm-svn: 144589
* Split out the plain '.{8|16|32|64}' suffix handling.Jim Grosbach2011-11-141-8/+24
| | | | | | | Make it easier to deal with aliases for instructions that do require a suffix but accept more specific variants of the same size. llvm-svn: 144588
* ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.Jim Grosbach2011-11-142-1/+38
| | | | | | rdar://10435076 llvm-svn: 144587
* Supporting inline memmove isn't going to be worthwhile. The only way to avoidChad Rosier2011-11-141-16/+9
| | | | | | | violating a dependency is to emit all loads prior to stores. This would likely cause a great deal of spillage offsetting any potential gains. llvm-svn: 144585
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-142-18/+11
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* Refactor capture tracking (which already had a couple flags for whether returnsNick Lewycky2011-11-142-117/+110
| | | | | | | | | | and stores capture) to permit the caller to see each capture point and decide whether to continue looking. Use this inside memdep to do an analysis that basicaa won't do. This lets us solve another devirtualization case, fixing PR8908! llvm-svn: 144580
* Add support for inlining small memcpys.Chad Rosier2011-11-141-2/+63
| | | | | | rdar://10412592 llvm-svn: 144578
* Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier2011-11-141-3/+3
| | | | | | into registers, rather then encoded directly in the load/store. llvm-svn: 144576
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