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* [NVPTX] Emit .pragma "nounroll" for loops marked with nounrollJingyue Wu2015-02-014-22/+76
| | | | | | | | | | | | | | | | | | | | | | | Summary: CUDA driver can unroll loops when jit-compiling PTX. To prevent CUDA driver from unrolling a loop marked with llvm.loop.unroll.disable is not unrolled by CUDA driver, we need to emit .pragma "nounroll" at the header of that loop. This patch also extracts getting unroll metadata from loop ID metadata into a shared helper function. Test Plan: test/CodeGen/NVPTX/nounroll.ll Reviewers: eliben, meheff, jholewinski Reviewed By: jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D7041 llvm-svn: 227703
* Fix PR22393. When recursively replacing an aggregate with a smallerAdrian Prantl2015-02-011-3/+12
| | | | | | | | aggregate or scalar, the debug info needs to refer to the absolute offset (relative to the entire variable) instead of storing the offset inside the smaller aggregate. llvm-svn: 227702
* [CMake] LLVMLTO requires Intrinsics.gen since r227685 introduced ↵NAKAMURA Takumi2015-02-011-0/+2
| | | | | | llvm/Analysis/TargetTransformInfo.h. llvm-svn: 227700
* [CMake] LLVMTarget requires Intrinsics.gen since r227669 introduced ↵NAKAMURA Takumi2015-02-011-2/+2
| | | | | | llvm/Analysis/TargetTransformInfo.h. llvm-svn: 227699
* [PM] Remove a bunch of stale TTI creation method declarations. I nukedChandler Carruth2015-02-017-19/+0
| | | | | | | their definitions, but forgot to clean up all the declarations which are in different files. llvm-svn: 227698
* Fix typoMatt Arsenault2015-01-311-1/+1
| | | | llvm-svn: 227697
* R600/SI: Only select cvt_flr/cvt_rpi with no NaNs.Matt Arsenault2015-01-311-2/+4
| | | | | | These have different behavior from cvt_i32_f32 on NaN. llvm-svn: 227693
* X86: silence a GCC warningSaleem Abdulrasool2015-01-311-1/+1
| | | | | | | | GCC 4.9 gives the following warning: warning: enumeral and non-enumeral type in conditional expression Cast the enumeral value to an integer within the ternary operation. NFC. llvm-svn: 227692
* Remove unused variable.Diego Novillo2015-01-311-2/+2
| | | | | | | | | | | | | | Summary: This variable is only used inside an assert. This breaks builds with asserts disabled. OK for trunk? Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7314 llvm-svn: 227691
* Removed a spurious semicolon; NFCAaron Ballman2015-01-311-1/+0
| | | | llvm-svn: 227690
* Removed SSE lane blend findCommutedOpIndices overrides. NFCI.Simon Pilgrim2015-01-311-14/+0
| | | | | | The default op indices frmo TargetInstrInfo::findCommutedOpIndices are being commuted so we don't need to do this. llvm-svn: 227689
* [X86][SSE] Shuffle mask decode support for zero extend, scalar float/double ↵Simon Pilgrim2015-01-314-399/+606
| | | | | | | | | | | | moves and integer load instructions This patch adds shuffle mask decodes for integer zero extends (pmovzx** and movq xmm,xmm) and scalar float/double loads/moves (movss/movsd). Also adds shuffle mask decodes for integer loads (movd/movq). Differential Revision: http://reviews.llvm.org/D7228 llvm-svn: 227688
* [PM] Switch the TargetMachine interface from accepting a pass managerChandler Carruth2015-01-3136-646/+710
| | | | | | | | | | | | | | | | | | | | | | | base which it adds a single analysis pass to, to instead return the type erased TargetTransformInfo object constructed for that TargetMachine. This removes all of the pass variants for TTI. There is now a single TTI *pass* in the Analysis layer. All of the Analysis <-> Target communication is through the TTI's type erased interface itself. While the diff is large here, it is nothing more that code motion to make types available in a header file for use in a different source file within each target. I've tried to keep all the doxygen comments and file boilerplate in line with this move, but let me know if I missed anything. With this in place, the next step to making TTI work with the new pass manager is to introduce a really simple new-style analysis that produces a TTI object via a callback into this routine on the target machine. Once we have that, we'll have the building blocks necessary to accept a function argument as well. llvm-svn: 227685
* [asan][mips] Fix MIPS64 Asan mappingKumar Sukhani2015-01-311-1/+1
| | | | llvm-svn: 227684
* ARM: make a table more readable (NFC)Saleem Abdulrasool2015-01-311-28/+40
| | | | | | | | This adds some comments and splits the flag calculation on type boundaries to make the table more readable. Addresses some post-commit review comments to SVN r227603. NFC. llvm-svn: 227670
* [PM] Change the core design of the TTI analysis to use a polymorphicChandler Carruth2015-01-3140-1839/+727
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type erased interface and a single analysis pass rather than an extremely complex analysis group. The end result is that the TTI analysis can contain a type erased implementation that supports the polymorphic TTI interface. We can build one from a target-specific implementation or from a dummy one in the IR. I've also factored all of the code into "mix-in"-able base classes, including CRTP base classes to facilitate calling back up to the most specialized form when delegating horizontally across the surface. These aren't as clean as I would like and I'm planning to work on cleaning some of this up, but I wanted to start by putting into the right form. There are a number of reasons for this change, and this particular design. The first and foremost reason is that an analysis group is complete overkill, and the chaining delegation strategy was so opaque, confusing, and high overhead that TTI was suffering greatly for it. Several of the TTI functions had failed to be implemented in all places because of the chaining-based delegation making there be no checking of this. A few other functions were implemented with incorrect delegation. The message to me was very clear working on this -- the delegation and analysis group structure was too confusing to be useful here. The other reason of course is that this is *much* more natural fit for the new pass manager. This will lay the ground work for a type-erased per-function info object that can look up the correct subtarget and even cache it. Yet another benefit is that this will significantly simplify the interaction of the pass managers and the TargetMachine. See the future work below. The downside of this change is that it is very, very verbose. I'm going to work to improve that, but it is somewhat an implementation necessity in C++ to do type erasure. =/ I discussed this design really extensively with Eric and Hal prior to going down this path, and afterward showed them the result. No one was really thrilled with it, but there doesn't seem to be a substantially better alternative. Using a base class and virtual method dispatch would make the code much shorter, but as discussed in the update to the programmer's manual and elsewhere, a polymorphic interface feels like the more principled approach even if this is perhaps the least compelling example of it. ;] Ultimately, there is still a lot more to be done here, but this was the huge chunk that I couldn't really split things out of because this was the interface change to TTI. I've tried to minimize all the other parts of this. The follow up work should include at least: 1) Improving the TargetMachine interface by having it directly return a TTI object. Because we have a non-pass object with value semantics and an internal type erasure mechanism, we can narrow the interface of the TargetMachine to *just* do what we need: build and return a TTI object that we can then insert into the pass pipeline. 2) Make the TTI object be fully specialized for a particular function. This will include splitting off a minimal form of it which is sufficient for the inliner and the old pass manager. 3) Add a new pass manager analysis which produces TTI objects from the target machine for each function. This may actually be done as part of #2 in order to use the new analysis to implement #2. 4) Work on narrowing the API between TTI and the targets so that it is easier to understand and less verbose to type erase. 5) Work on narrowing the API between TTI and its clients so that it is easier to understand and less verbose to forward. 6) Try to improve the CRTP-based delegation. I feel like this code is just a bit messy and exacerbating the complexity of implementing the TTI in each target. Many thanks to Eric and Hal for their help here. I ended up blocked on this somewhat more abruptly than I expected, and so I appreciate getting it sorted out very quickly. Differential Revision: http://reviews.llvm.org/D7293 llvm-svn: 227669
* ARM: support stack probe size on Windows on ARMSaleem Abdulrasool2015-01-311-3/+7
| | | | | | | | | Now that -mstack-probe-size is piped through to the backend via the function attribute as on Windows x86, honour the value to permit handling of non-default values for stack probes. This is needed /Gs with the clang-cl driver or -mstack-probe-size with the clang driver when targeting Windows on ARM. llvm-svn: 227667
* [fuzzer] add flags to run fuzzer in multiple parallel processesKostya Serebryany2015-01-312-0/+40
| | | | llvm-svn: 227664
* Remove the last vestiges of resetOperationActions.Eric Christopher2015-01-312-28/+0
| | | | llvm-svn: 227648
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-315-29/+31
| | | | | | without a Function argument. llvm-svn: 227647
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-308-51/+37
| | | | | | without a Function argument. llvm-svn: 227644
* Avoid using the cast and use the templated accessor function.Eric Christopher2015-01-301-1/+1
| | | | llvm-svn: 227643
* Factor out statepoint verification into separate function. (NFC)Philip Reames2015-01-301-93/+102
| | | | | | | | | | Patch by: Igor Laevsky "Simple refactoring. This is done in preparation to support verification of invokable statepoints." Differential Revision: http://reviews.llvm.org/D7276 llvm-svn: 227640
* [fuzzer] Add a gtest-style testKostya Serebryany2015-01-306-24/+101
| | | | | | | | | | | | | | | | Summary: Add one gtest-style test. Test Plan: run on bot Reviewers: samsonov Reviewed By: samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7287 llvm-svn: 227639
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-3022-167/+139
| | | | | | without a Function argument. llvm-svn: 227638
* Add ARM test for r227489, but XFAIL because this is actually more work than ↵David Blaikie2015-01-301-7/+7
| | | | | | | | | | | | | | it appeared to be. Also revert r227489 since it didn't actually fix the thing I thought I was fixing (since the test case was targeting the wrong architecture initially). The change might be correct & demonstrated by other test cases, but it's not a priority for me to find those test cases right now. Filed PR22417 for the failure. llvm-svn: 227632
* NFC. Making printOptionValues an API on the parser class.Chris Bieneman2015-01-301-3/+7
| | | | llvm-svn: 227626
* Fix memory leak in WinEHPrepare introduced in r227405.Alexey Samsonov2015-01-301-1/+3
| | | | | | This leak was detected by ASan bootstrap of LLVM. llvm-svn: 227625
* Remove unused function.Eric Christopher2015-01-301-4/+0
| | | | llvm-svn: 227624
* Remove extraneous forward declaration.Eric Christopher2015-01-301-1/+0
| | | | llvm-svn: 227623
* Use the cached subtargets and remove calls to getSubtarget/getSubtargetImplEric Christopher2015-01-309-174/+154
| | | | | | without a Function argument. llvm-svn: 227622
* [Hexagon] Adding vector shift instructions and tests.Colin LeMahieu2015-01-304-2/+107
| | | | llvm-svn: 227619
* R600/SI: Handle SI_SPILL_V96_RESTORE in SIRegisterInfo::eliminateFrameIndex()Tom Stellard2015-01-301-0/+1
| | | | | | This fixes a crash in Unigine Heaven. llvm-svn: 227618
* Silence "not all paths return a value" warning in MSVCReid Kleckner2015-01-301-0/+1
| | | | llvm-svn: 227614
* [Hexagon] Adding vector predicate instructions.Colin LeMahieu2015-01-302-0/+65
| | | | llvm-svn: 227613
* [Hexagon] Adding vector permutation instructions and tests.Colin LeMahieu2015-01-302-0/+85
| | | | llvm-svn: 227612
* Win64: Put a REX_W prefix on all TAILJMP* instructionsReid Kleckner2015-01-306-15/+43
| | | | | | | | | | | | | MSDN's x64 software conventions page says that this is one of the fixed list of legal epilogues: https://msdn.microsoft.com/en-us/library/tawsa7cb.aspx Presumably this is how the unwinder distinguishes epilogue jumps from in-function control flow. Also normalize the way we place "## TAILCALL" comments on such jumps. llvm-svn: 227611
* [Hexagon] Adding vector multiplies. Cleaning up tests.Colin LeMahieu2015-01-303-20/+208
| | | | llvm-svn: 227609
* [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests.Colin LeMahieu2015-01-304-0/+297
| | | | llvm-svn: 227607
* [AArch64] Make AArch64A57FPLoadBalancing output stable.Chad Rosier2015-01-301-2/+9
| | | | | | | | | | | | | Add tie breaker to colorChainSet() sort so that processing order doesn't depend on std::set order, which depends on pointer order, which is unstable from run to run. No test case as this is nearly impossible to reproduce. Phabricator Review: http://reviews.llvm.org/D7265 Patch by Geoff Berry <gberry@codeaurora.org>! llvm-svn: 227606
* Remove a redundant dyn_cast.Adrian Prantl2015-01-301-3/+2
| | | | llvm-svn: 227605
* Inliner: Use replaceDbgDeclareForAlloca() instead of splicing theAdrian Prantl2015-01-303-18/+20
| | | | | | | instruction and generalize it to optionally dereference the variable. Follow-up to r227544. llvm-svn: 227604
* ARM: further correct .fpu directive handlingSaleem Abdulrasool2015-01-301-7/+9
| | | | | | | | | | If the original FPU specification involved a restricted VFP unit (d16), ensure that we reset the functionality when we encounter a new FPU type. In particular, if the user specified vfpv3-d16, but switched to a VFPv3 (which has 32 double precision registers), we would fail to reset the D16 feature, and treat it as being equivalent to vfpv3-d16. llvm-svn: 227603
* Revert "Revert "Matching ARM change for r227481: DebugInfo: Teach Fast ISel ↵Renato Golin2015-01-301-7/+7
| | | | | | | | to respect the debug location of comparisons in jumps."" This reverts commit r227600, since that reverted the wrong comit. Sorry. llvm-svn: 227601
* Revert "Matching ARM change for r227481: DebugInfo: Teach Fast ISel to ↵Renato Golin2015-01-301-7/+7
| | | | | | | | respect the debug location of comparisons in jumps." This reverts commit r227488 as it was failing ARM bots. llvm-svn: 227600
* [Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files.Colin LeMahieu2015-01-303-8/+213
| | | | llvm-svn: 227598
* ARM: improve caret diagnostics for invalid FPU nameSaleem Abdulrasool2015-01-301-1/+2
| | | | | | | In the case of an invalid FPU name, place the caret at the name rather than FPU directive. llvm-svn: 227595
* Check bit widths before trying to get a type.Filipe Cabecinhas2015-01-301-2/+7
| | | | | | | | | Added a test case for it. Also added run lines for the test case in r227566. Bugs found with afl-fuzz llvm-svn: 227589
* [Hexagon] Adding a number of vector load variants and organizing tests.Colin LeMahieu2015-01-302-16/+92
| | | | llvm-svn: 227588
* Move DebugInfo to DebugInfo/DWARF.Zachary Turner2015-01-3029-61/+102
| | | | | | | | | | | | | In preparation for adding PDB support to LLVM, this moves the DWARF parsing code to its own subdirectory under DebugInfo, and renames LLVMDebugInfo to LLVMDebugInfoDWARF. This is purely a mechanical / build system change. Differential Revision: http://reviews.llvm.org/D7269 Reviewed by: Eric Christopher llvm-svn: 227586
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