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* add basic PPC register-pressure feedback; adjust the vaarg test to match the ↵Hal Finkel2011-11-224-5/+28
| | | | | | new register-allocation pattern llvm-svn: 145065
* More fixes to the X86InstComments for shuffle instructions. In particular ↵Craig Topper2011-11-223-44/+60
| | | | | | add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. llvm-svn: 145063
* Fix a devilish miscompile exposed by block placement. TheChandler Carruth2011-11-221-2/+8
| | | | | | | | | | | | | | | | | | | | | updateTerminator code didn't correctly handle EH terminators in one very specific case. AnalyzeBranch would find no terminator instruction, and so the fallback in updateTerminator is to assume fallthrough. This is correct, but the destination of the fallthrough was assumed to be the first successor. This is *almost always* true, but in certain cases the loop transformations will cause the landing pad to be the first successor! Instead of this brittle logic, actually look through the successors for a non-landing-pad accessor, and to assert if more than one is found. This will hopefully fix some (if not all) of the self host miscompiles with block placement. Thanks to Benjamin Kramer for reporting, Nick Lewycky for an initial stab at a reduction, and Duncan for endless advice on EH (which I know nothing about) as well as reviewing the actual fix. llvm-svn: 145062
* Add configure checking for pread(2) and use it to save a syscall when ↵Benjamin Kramer2011-11-221-0/+7
| | | | | | reading files. llvm-svn: 145061
* Fix an obvious omission in the SelectionDAGBuilder where we wereChandler Carruth2011-11-221-2/+2
| | | | | | | | | | | | | dropping weights on the floor for invokes. This was impeding my writing further test cases for invoke when interacting with probabilities and block placement. No test case as there doesn't appear to be a way to test this stuff. =/ Suggestions for a test case of course welcome. I hope to be able to add test cases that indirectly cover this eventually by adding probabilities to the exceptional edge and reordering blocks as a result. llvm-svn: 145060
* Turn error recovery into an assert.Benjamin Kramer2011-11-221-6/+1
| | | | | | | This was put in because in a certain version of DragonFlyBSD stat(2) lied about the size of some files. This was fixed a long time ago so we can remove the workaround. llvm-svn: 145059
* If a register is both an early clobber and part of a tied use, handle the useRafael Espindola2011-11-221-7/+16
| | | | | | | | before the clobber so that we copy the value if needed. Fixes pr11415. llvm-svn: 145056
* Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors ↵Craig Topper2011-11-224-21/+73
| | | | | | correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. llvm-svn: 145055
* Add methods for querying minimum SSE version along with AVX. Simplifies all ↵Craig Topper2011-11-222-43/+38
| | | | | | the places that had to check a version of SSE and AVX. llvm-svn: 145053
* Fix crasher in GVN due to my recent capture tracking changes.Nick Lewycky2011-11-212-1/+4
| | | | llvm-svn: 145047
* Add virtual destructor. Whoops!Nick Lewycky2011-11-211-0/+2
| | | | llvm-svn: 145044
* Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled.Craig Topper2011-11-214-84/+30
| | | | llvm-svn: 145028
* Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if ↵Craig Topper2011-11-214-47/+115
| | | | | | AVX2 is enabled. llvm-svn: 145026
* Fixing a commentJoe Abbey2011-11-211-1/+1
| | | | llvm-svn: 145025
* Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and ↵Craig Topper2011-11-211-8/+42
| | | | | | use AVX2 shifts when AVX2 is enabled. llvm-svn: 145022
* Less template, more virtual! Refactoring suggested by Chris in code review.Nick Lewycky2011-11-202-4/+109
| | | | llvm-svn: 145014
* Refactor code to use new attribute getters on CallSite for NoCapture and ByVal.Nick Lewycky2011-11-206-11/+8
| | | | | | | | Suggested in code review by Eli. That code in InstCombine looks kinda suspicious. llvm-svn: 145013
* The logic for breaking the CFG in the presence of hot successors didn'tChandler Carruth2011-11-201-3/+29
| | | | | | | | | | | | | | | | properly account for the *global* probability of the edge being taken. This manifested as a very large number of unconditional branches to blocks being merged against the CFG even though they weren't particularly hot within the CFG. The fix is to check whether the edge being merged is both locally hot relative to other successors for the source block, and globally hot compared to other (unmerged) predecessors of the destination block. This introduces a new crasher on GCC single-source, but it's currently behind a flag, and Ben has offered to work on the reduction. =] llvm-svn: 145010
* SCEV: Actually set overflow flags on add expressions.Benjamin Kramer2011-11-201-2/+2
| | | | | | setFlags doesn't modify its arguments. llvm-svn: 145007
* Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift ↵Craig Topper2011-11-202-45/+45
| | | | | | instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. llvm-svn: 145005
* Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled.Craig Topper2011-11-194-16/+33
| | | | llvm-svn: 145004
* Remove some of the special classes that worked around an old tablegen ↵Craig Topper2011-11-191-100/+50
| | | | | | limitation of not being able to remove redundant bitconverts from patterns. llvm-svn: 145003
* Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove ↵Craig Topper2011-11-192-74/+42
| | | | | | the intrinsic patterns. llvm-svn: 144999
* Move the handling of unanalyzable branches out of the loop-driven chainChandler Carruth2011-11-191-25/+33
| | | | | | | | | | | | | | | | | | | | | | | | formation phase and into the initial walk of the basic blocks. We essentially pre-merge all blocks where unanalyzable fallthrough exists, as we won't be able to update the terminators effectively after any reorderings. This is quite a bit more principled as there may be CFGs where the second half of the unanalyzable pair has some analyzable predecessor that gets placed first. Then it may get placed next, implicitly breaking the unanalyzable branch even though we never even looked at the part that isn't analyzable. I've included a test case that triggers this (thanks Benjamin yet again!), and I'm hoping to synthesize some more general ones as I dig into related issues. Also, to make this new scheme work we have to be able to handle branches into the middle of a chain, so add this check. We always fallback on the incoming ordering. Finally, this starts to really underscore a known limitation of the current implementation -- we don't consider broken predecessors when merging successors. This can caused major missed opportunities, and is something I'm planning on looking at next (modulo more bug reports). llvm-svn: 144994
* Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from ↵Craig Topper2011-11-194-3/+62
| | | | | | add/sub of appropriate shuffle vectors. llvm-svn: 144989
* Collapse X86 PSIGNB/PSIGNW/PSIGND node types.Craig Topper2011-11-194-33/+18
| | | | llvm-svn: 144988
* Extend VPBLENDVB and VPSIGN lowering to work for AVX2.Craig Topper2011-11-193-111/+127
| | | | llvm-svn: 144987
* Remove unused parameters from the AVX maskmov classes.Craig Topper2011-11-191-12/+6
| | | | llvm-svn: 144985
* Fix a corner case in updating LoopInfo after fully unrolling an outer loop.Andrew Trick2011-11-181-11/+9
| | | | | | | | | | | The loop tree's inclusive block lists are painful and expensive to update. (I have no idea why they're inclusive). The design was supposed to handle this case but the implementation missed it and my unit tests weren't thorough enough. Fixes PR11335: loop unroll update. llvm-svn: 144970
* Add AVX2 vpbroadcast supportNadav Rotem2011-11-182-28/+62
| | | | llvm-svn: 144967
* [asan] workaround for reg alloc bug 11395: don't instrument functions with ↵Kostya Serebryany2011-11-181-0/+13
| | | | | | large chunks of inline assembler llvm-svn: 144962
* Guard call to getRegForValue with isTypeLegal check to avoid unnecessary ↵Chad Rosier2011-11-181-3/+5
| | | | | | work/dead code. llvm-svn: 144959
* DISubrange supports unsigned lower/upper array bounds, so let's not fake it ↵Devang Patel2011-11-171-4/+4
| | | | | | in the end while emitting DWARF. If a FE needs to encode signed lower/upper array bounds then we need to extend DISubrange or ad DISignedSubrange. llvm-svn: 144937
* quick fix: remove GlobalVariable::GlobalVariable mistakenly commited at ↵Kostya Serebryany2011-11-171-3/+3
| | | | | | r144933. For some reason this compiles on linux llvm-svn: 144936
* Fix an overly general check in SimplifyIndvar to handle useless phi cycles.Andrew Trick2011-11-171-2/+2
| | | | | | | | | | | | | | The right way to check for a binary operation is cast<BinaryOperator>. The original check: cast<Instruction> && numOperands() == 2 would match phi "instructions", leading to an infinite loop in extreme corner case: a useless phi with operands [self, constant] that prior optimization passes failed to remove, being used in the loop by another useless phi, in turn being used by an lshr or udiv. Fixes PR11350: runaway iteration assertion. llvm-svn: 144935
* fall back to explicit list of allowed linkages when instrumenting globals in ↵Kostya Serebryany2011-11-171-2/+5
| | | | | | asan; add a test check that asan does not touch linkonce_odr llvm-svn: 144933
* Add TODO comment.Chad Rosier2011-11-171-0/+2
| | | | llvm-svn: 144920
* Fix SSE/AVX integer comparison patterns to understand that all integer ↵Craig Topper2011-11-171-24/+42
| | | | | | vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. llvm-svn: 144896
* Dead code.Chad Rosier2011-11-171-14/+0
| | | | llvm-svn: 144888
* When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier2011-11-171-11/+35
| | | | | | | | | | | | | ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs being: (1) If we can't materialize the large constant then we'll cause fast-isel to bail. (2) Too large of an offset can't be directly encoded in the ADD resulting in a MOV+ADD. Generally not a bad thing because otherwise we would have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix for that. (3) Conversely, too low of a threshold we'll miss opportunities to coalesce ADDs. rdar://10412592 llvm-svn: 144886
* Remove seemingly unnecessary duplicate VROUND definitions.Craig Topper2011-11-171-80/+4
| | | | llvm-svn: 144885
* Add support for custom names for library functions in TargetLibraryInfo. ↵Eli Friedman2011-11-173-13/+50
| | | | | | | | | | Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom names for fwrite and fputs. Fixes <rdar://problem/9815881>. llvm-svn: 144876
* Don't unconditionally set the kill flag.Chad Rosier2011-11-171-1/+1
| | | | | | rdar://10456186 llvm-svn: 144872
* Turn on vzeroupper insertion on call boundaries for AVX; it works as far as ↵Eli Friedman2011-11-171-1/+1
| | | | | | I know, and I'd like to see wider testing. llvm-svn: 144867
* Make sure to replace the chain properly when DAGCombining a ↵Eli Friedman2011-11-161-4/+17
| | | | | | LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393. llvm-svn: 144863
* Object/COFF: Support common symbols.Michael J. Spencer2011-11-161-1/+3
| | | | llvm-svn: 144861
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
| | | | | | | We don't (yet) have the granularity in the fixups to be specific about which bitranges are affected. That's a future cleanup, but we're not there yet. llvm-svn: 144852
* Lower 64-bit constant pool node.Akira Hatanaka2011-11-161-8/+12
| | | | llvm-svn: 144849
* Lower 64-bit block address.Akira Hatanaka2011-11-161-9/+11
| | | | llvm-svn: 144847
* Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach2011-11-161-1/+1
| | | | llvm-svn: 144842
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