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* [MemorySSA] Add const to getClobberingMemoryAccess.George Burgess IV2016-10-281-3/+3
| | | | | | | | Thanks to bryant for the patch! Differential Revision: https://reviews.llvm.org/D26086 llvm-svn: 285432
* Move the DWARF attribute constants into Dwarf.def and delete 300 lines of ↵Adrian Prantl2016-10-281-195/+6
| | | | | | silly code. llvm-svn: 285425
* MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun2016-10-286-7/+6
| | | | llvm-svn: 285423
* TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.Matthias Braun2016-10-281-3/+3
| | | | | | | | | TargetPassConfig::addMachinePasses() does some housekeeping first: Handling the -print-machineinstrs flag and doing an initial printing "After Instruction Selection". There is no reason for RegUsageInfoProp to run before those two steps. llvm-svn: 285422
* Import/update constants from the DWARF 5 public review draft document.Adrian Prantl2016-10-285-9/+26
| | | | | | https://reviews.llvm.org/D26051 llvm-svn: 285421
* [Hexagon] Maintain kill flags through splitting in expand-condsetsKrzysztof Parzyszek2016-10-281-40/+96
| | | | | | | Do not use LiveIntervals to recalculate kills, because that cannot be done accurately without implicit uses on predicated instructions. llvm-svn: 285409
* [Loads] Fix crash in is isDereferenceableAndAlignedPointer()Tom Stellard2016-10-281-2/+5
| | | | | | | | | | | | | | | Summary: We were trying to add APInt values with different bit sizes after visiting an addrspacecast instruction which changed the bit width of the pointer. Reviewers: majnemer, hfinkel Subscribers: hfinkel, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D24774 llvm-svn: 285407
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
| | | | | | No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway llvm-svn: 285398
* [SelectionDAG] Increment computeKnownBits recursion depth for ↵Simon Pilgrim2016-10-281-2/+2
| | | | | | SMIN/SMAX/UMIN/UMAX like all other ops llvm-svn: 285397
* [LCSSA] Perform LCSSA verification only for the current loop nest.Igor Laevsky2016-10-284-4/+45
| | | | | | | | | Now LPPassManager will run LCSSA verification only for the top-level loop which was processed on the current iteration. Differential Revision: https://reviews.llvm.org/D25873 llvm-svn: 285394
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
| | | | | | | This seems to have increased LTO compile time bejond 2x of previous builds. See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/ llvm-svn: 285381
* [Reassociate] Removing instructions mutates the IR.Davide Italiano2016-10-281-1/+3
| | | | | | | | | Fixes PR 30784. Discussed with Justin, who pointed out that in the new PassManager infrastructure we can have more fine-grained control on which analyses we want to preserve, but this is the best we can do with the current infrastructure. llvm-svn: 285380
* [ThinLTO] Create AliasSummary when building indexTeresa Johnson2016-10-282-7/+27
| | | | | | | | | | | | | | | | | | | Summary: Previously we were creating the alias summary on the fly while writing the summary to bitcode. This moves the creation of these summaries to the module summary index builder where we build the rest of the summary index. This is going to be necessary for setting the NoRename flag for values possibly used in inline asm or module level asm. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26049 llvm-svn: 285379
* [ThinLTO] Rename HasSection to NoRename (NFC)Teresa Johnson2016-10-283-5/+6
| | | | | | | | | | | | | | Summary: This is in preparation for a change to utilize this flag for symbols referenced/defined in either inline or module level assembly. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26048 llvm-svn: 285376
* [IR] Clang-format my previous commit. NFCI.Davide Italiano2016-10-281-2/+2
| | | | llvm-svn: 285375
* [ConstantFold] Get the correct vector type when folding a getelementptr.Davide Italiano2016-10-281-6/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D26014 llvm-svn: 285371
* AMDGPU/SI: Handle hazard with s_rfe_b64Tom Stellard2016-10-273-1/+35
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25638 llvm-svn: 285368
* AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}laneTom Stellard2016-10-272-1/+34
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25637 llvm-svn: 285367
* AMDGPU/SI: Fix unused variable warning on non-debug buildsTom Stellard2016-10-271-0/+1
| | | | llvm-svn: 285363
* Reverting back r285355: "Update .debug_line section version information to ↵Ekaterina Romanova2016-10-271-7/+2
| | | | | | match DWARF version", while I'm investigating a test failure. llvm-svn: 285362
* AMDGPU/SI: Handle hazard with > 8 byte VMEM storesTom Stellard2016-10-276-22/+124
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25577 llvm-svn: 285359
* Reapply r285351 "[APFloat] Add DoubleAPFloat mode to APFloat. NFC." withTim Shen2016-10-271-59/+115
| | | | | | a workaround for old clang. llvm-svn: 285358
* Update .debug_line section version information to match DWARF version.Ekaterina Romanova2016-10-271-2/+7
| | | | | | | | | | In the past the compiler always emitted .debug_line version 2, though some opcodes from DWARF 3 (e.g. DW_LNS_set_prologue_end, DW_LNS_set_epilogue_begin or DW_LNS_set_isa) and from DWARF 4 could be emitted by the compiler. This patch changes version information of .debug_line to exactly match the DWARF version. For .debug_line version 4, a new field maximum_operations_per_instruction is emitted. Differential Revision: https://reviews.llvm.org/D16697 llvm-svn: 285355
* Revert "[APFloat] Add DoubleAPFloat mode to APFloat. NFC."Tim Shen2016-10-271-115/+59
| | | | | | This reverts r285351, since it breaks the build. llvm-svn: 285354
* [libFuzzer] enable use_cmp by defaultKostya Serebryany2016-10-2711-15/+17
| | | | llvm-svn: 285353
* [APFloat] Add DoubleAPFloat mode to APFloat. NFC.Tim Shen2016-10-271-59/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds DoubleAPFloat mode to APFloat. Now, an APFloat with semantics PPCDoubleDouble will have DoubleAPFloat layout (APFloat.U.Double), which contains two underlying APFloats as PPCDoubleDoubleImpl and IEEEdouble semantics. Currently the IEEEdouble APFloat is not used, and the first APFloat behaves exactly the same before this change. This patch consists of three kinds of logics: 1) Construction and destruction of APFloat. Now the ctors, dtor, assign opertors and factory functions construct different underlying layout based on the semantics passed in. 2) s/IEEE/getIEEE()/ for normal, lifetime-unrelated computation functions. These functions only access Floats[0] in DoubleAPFloat, which is the same as today's semantic. 3) A "Double dispatch" function, APFloat::convert. Converting between two different layouts requires appropriate logic. Neither of these change the external behavior. Reviewers: hfinkel, kbarton, echristo, iteratee Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D25977 llvm-svn: 285351
* BitcodeReader: Require clients to read the block info block at most once.Peter Collingbourne2016-10-271-2/+2
| | | | | | | | | | | | This change makes it the client's responsibility to call ReadBlockInfoBlock() at most once. This is in preparation for a future change that will allow there to be multiple block info blocks. See also: http://lists.llvm.org/pipermail/llvm-dev/2016-October/106512.html Differential Revision: https://reviews.llvm.org/D26016 llvm-svn: 285350
* CodeGen: Handle missed case of block removal during BlockPlacement.Kyle Butt2016-10-271-4/+10
| | | | | | | | | There is a use after free bug in the existing code. Loop layout selects a preferred exit block, and then lays out the loop. If this block is removed during layout, it needs to be invalidated to prevent a use after free. llvm-svn: 285348
* [InstCombine] fix foldSPFofSPF() to handle vector splatsSanjay Patel2016-10-271-22/+18
| | | | llvm-svn: 285345
* Another additional error check for invalid Mach-O files for theKevin Enderby2016-10-271-0/+26
| | | | | | | | | | | | | | | | | | | | | | obsolete load commands. Again the philosophy of the error checking in libObject for Mach-O files, the idea behind the checking is that we never will return a Mach-O file out of libObject that contains unknown things the library code can’t operate on. So known obsolete load commands will cause a hard error. Also to make things clear I have added comments to the values and structures in Support/Mach-O.h and Support/MachO.def as to what is obsolete. As noted in a TODO in the code, there may need to be a non-default mode to allow some unknown values for well structured Mach-O files with things like unknown load load commands. So things like using an old lldb on a newer Mach-O file could still provide some limited functionality. llvm-svn: 285342
* AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizerTom Stellard2016-10-272-0/+20
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25528 llvm-svn: 285338
* [LoopUnroll] Check partial unrolling is enabled before initialization. NFC.Haicheng Wu2016-10-271-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D23891 llvm-svn: 285330
* [X86][AVX512] Fix MUL v8i64 costs on non-AVX512DQ targetsSimon Pilgrim2016-10-271-0/+1
| | | | llvm-svn: 285329
* [InstCombine] handle simple vector integer constants in IsFreeToInvertSanjay Patel2016-10-271-0/+18
| | | | llvm-svn: 285318
* [X86][AVX512DQ] Move v2i64 and v4i64 MUL lowering to tablegenSimon Pilgrim2016-10-272-23/+21
| | | | | | As suggested by @igorb on D26011 llvm-svn: 285313
* ARM: ensure that the Windows DBZ check is in rangeSaleem Abdulrasool2016-10-272-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Windows ARM target expects the compiler to emit a division-by-zero check. The check would use the form of: cmp r?, #0 cbz .Ltrap b .Lbody .Lbody: ... .Ltrap: udf #249 @ __brkdiv0 This works great most of the time. However, if the body of the function is greater than 127 bytes, the branch target limitation of cbz becomes an issue. This occurs in the unoptimized code generation cases sometimes (like in compiler-rt). Since this is a matter of correctness, possibly pay a small penalty instead. We now form this slightly differently: cbnz .Lbody udf #249 @ __brkdiv0 .Lbody: ... The positive case is through the branch instead of being the next instruction. However, because of the basic block layout, the negated branch is going to be a short distance always (2 bytes away, after the inserted __brkdiv0). The new t__brkdiv0 instruction is required to explicitly mark the instruction as a terminator as the generic UDF instruction is not a terminator. Addresses PR30532! llvm-svn: 285312
* Switch all DWARF variables for tags, attributes and forms over to use the ↵Greg Clayton2016-10-274-37/+47
| | | | | | | | llvm::dwarf enumerations instead of using raw uint16_t values. This allows easier debugging as users can see the values of the enumerations in the variables view that will show the enumeration string instead of just a number. https://reviews.llvm.org/D26013 llvm-svn: 285309
* Add Loop Sink pass to reverse the LICM based of basic block frequency.Dehao Chen2016-10-274-14/+337
| | | | | | | | | | | | Summary: LICM may hoist instructions to preheader speculatively. Before code generation, we need to sink down the hoisted instructions inside to loop if it's beneficial. This pass is a reverse of LICM: looking at instructions in preheader and sinks the instruction to basic blocks inside the loop body if basic block frequency is smaller than the preheader frequency. Reviewers: hfinkel, davidxl, chandlerc Subscribers: anna, modocache, mgorny, beanz, reames, dberlin, chandlerc, mcrosier, junbuml, sanjoy, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D22778 llvm-svn: 285308
* [mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass.Vasileios Kalintiris2016-10-271-3/+0
| | | | | | | | | | | | | | r282428 added the MipsOptimizePICCall as an opt-in pass that can be skipped when using the -opt-bisect-limit option. However, this pass is needed because it generates code that conforms to the o32 ABI specification by using the $t9 register for PIC calls with JALR instructions. This bug was exposed by the fact that skipFunction() also checks for the "optnone" attribute. This caused functions with that attribute to break the requirements of the o32 ABI. llvm-svn: 285305
* [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64Simon Pilgrim2016-10-272-0/+32
| | | | | | | | | | With DQI but without VLX, lower v2i64 and v4i64 MUL operations with v8i64 MUL (vpmullq). Updated cost table accordingly. Differential Revision: https://reviews.llvm.org/D26011 llvm-svn: 285304
* [ValueTracking] fix matchSelectPattern to allow vector splat folds of ↵Sanjay Patel2016-10-271-6/+8
| | | | | | min/max/abs/nabs llvm-svn: 285303
* Fix memory issue in AttrBuilder::removeAttribute uses.Bjorn Pettersson2016-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Found when running Valgrind. This removes two unnecessary assignments when using AttrBuilder::removeAttribute. AttrBuilder::removeAttribute returns a reference to the object. As the LHSes were the same as the callees, the assignments resulted in memcpy calls where dst = src. Commited on behalf-of: dstenb (David Stenberg) Reviewers: mkuper, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25460 llvm-svn: 285298
* [Hexagon] Do not expand ISD::SELECT for HVX vectorsKrzysztof Parzyszek2016-10-272-16/+19
| | | | llvm-svn: 285297
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
| | | | | | | | | | | | | | | | Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285296
* [SLP] Fix for PR30626: Compiler crash inside SLP Vectorizer.Alexey Bataev2016-10-271-4/+11
| | | | | | | | | | | | | | | | After successfull horizontal reduction vectorization attempt for PHI node vectorizer tries to update root binary op by combining vectorized tree and the ReductionPHI node. But during vectorization this ReductionPHI can be vectorized itself and replaced by the `undef` value, while the instruction itself is marked for deletion. This 'marked for deletion' PHI node then can be used in new binary operation, causing "Use still stuck around after Def is destroyed" crash upon PHI node deletion. Also the test is fixed to make it perform actual testing. Differential Revision: https://reviews.llvm.org/D25671 llvm-svn: 285286
* [ARM] Predicate UMAAL selection on hasDSP.Sam Parker2016-10-272-2/+3
| | | | | | | | | | | | UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets. Also fix wrong CHECK prefix in longMAC.ll test. Patch by Vadzim Dambrouski. Differential Revision: https://reviews.llvm.org/D25890 llvm-svn: 285278
* [AVR] Generate all of the TableGen files we needDylan McKay2016-10-271-1/+6
| | | | | | | This enables generation of all of the TableGen files that are used downstream. llvm-svn: 285274
* AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged due register ↵Nicolai Haehnle2016-10-271-11/+31
| | | | | | | | | | | | | | | | | | | | | | | | dependencies Summary: When finding a match for a merge and collecting the instructions that must be moved, keep in mind that the instruction we merge might actually use one of the defs that are being moved. Fixes piglit spec/arb_enhanced_layouts/execution/component-layout/vs-tcs-load-output[-indirect]. The fact that the ds_read in the test case is not eliminated suggests that there might be another problem related to alias analysis, but that's a separate problem: this pass should still work correctly even when earlier optimization passes missed something or were disabled. Reviewers: tstellarAMD, arsenm Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25829 llvm-svn: 285273
* [AVR] Compile the disassemblerDylan McKay2016-10-273-6/+3
| | | | | | | This also updates references of 'TheAVRTarget' to the new 'getTheAVRTarget()' method. llvm-svn: 285272
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