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* use repmovsb when optimizing forminsizeClement Courbet2017-04-211-8/+31
| | | | llvm-svn: 300960
* Rename FastString flag.Clement Courbet2017-04-215-12/+15
| | | | llvm-svn: 300959
* X86 memcpy: use REPMOVSB instead of REPMOVS{Q,D,W} for inline copiesClement Courbet2017-04-215-1/+20
| | | | | | | | | | | | when the subtarget has fast strings. This has two advantages: - Speed is improved. For example, on Haswell thoughput improvements increase linearly with size from 256 to 512 bytes, after which they plateau: (e.g. 1% for 260 bytes, 25% for 400 bytes, 40% for 508 bytes). - Code is much smaller (no need to handle boundaries). llvm-svn: 300957
* [DWARF] - Refactoring: localize handling of relocations in a single place.George Rimar2017-04-215-41/+27
| | | | | | | | | | | This is splitted from D32228, currently DWARF parsers code has few places that applied relocations values manually. These places has similar duplicated code. Patch introduces separate method that can be used to obtain relocated value. That helps to reduce code and simplifies things. Differential revision: https://reviews.llvm.org/D32284 llvm-svn: 300956
* Delete dead codeClement Courbet2017-04-211-15/+1
| | | | llvm-svn: 300952
* [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing ↵Artyom Skrobov2017-04-211-1/+2
| | | | | | | | | | | | | | `Uses = [CPSR]` Summary: Thanks to Oliver Stannard for helping catch this. Reviewers: olista01, efriedma Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D31815 llvm-svn: 300951
* [AsmWriter] Eliminate warning. NFCSerguei Katkov2017-04-211-4/+4
| | | | | | | | | | | | | | This patch eliminates the following warning lib/IR/AsmWriter.cpp:1128:57: warning: suggest parentheses around '&&' within '||' [-Wparentheses] (StrVal[1] >= '0' && StrVal[1] <= '9')) && Reviewers: timshen, rnk, davide Reviewed By: davide Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D32337 llvm-svn: 300950
* [MSSA] Clean up the updater a bit. NFCGeorge Burgess IV2017-04-211-5/+4
| | | | | | | | - Mark an internal function static - Remove the llvm namespace (just holding on to the `using namespace llvm;` Works on My Machine(TM)) llvm-svn: 300947
* [PartialInliner] Fix crash when inlining functions with unreachable blocks.Davide Italiano2017-04-211-12/+13
| | | | | | | | | | | | | | | | CodeExtractor looks up the dominator node corresponding to return blocks when splitting them. If one of these blocks is unreachable, there's no node in the Dom and CodeExtractor crashes because it doesn't check for domtree node validity. In theory, we could add just a check for skipping null DTNodes in `splitReturnBlock` but the fix I propose here is slightly different. To the best of my knowledge, unreachable blocks are irrelevant for the algorithm, therefore we can just skip them when building the candidate set in the constructor. Differential Revision: https://reviews.llvm.org/D32335 llvm-svn: 300946
* [AsmWriter/APFloat] FP constant printing: Avoid usage of locale dependent ↵Serguei Katkov2017-04-212-31/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | snprinf This should fix the bug https://bugs.llvm.org/show_bug.cgi?id=12906 To print the FP constant AsmWriter does the following: 1) convert FP value to String (actually using snprintf function which is locale dependent). 2) Convert String back to FP Value 3) Compare original and got FP values. If they are not equal just dump as hex. The problem happens on the 2nd step when APFloat does not expect group delimiter or fraction delimiter other than period symbol and so on, which can be produced on the first step if LLVM library is used in an environment with corresponding locale set. To fix this issue the locale independent APFloat:toString function is used. However it prints FP values slightly differently than snprintf does. Specifically it suppress trailing zeros in significant, use capital E and so on. It results in 117 test failures during make check. To avoid this I've also updated APFloat.toString a bit to pass make check at least. Reviewers: sberg, bogner, majnemer, sanjoy, timshen, rnk Reviewed By: timshen, rnk Subscribers: rnk, llvm-commits Differential Revision: https://reviews.llvm.org/D32276 llvm-svn: 300943
* Revert r300932 and r300930.Akira Hatanaka2017-04-217-186/+37
| | | | | | | | | It seems that r300930 was creating an infinite loop in dag-combine when compling the following file: MultiSource/Benchmarks/MiBench/consumer-typeset/z21.c llvm-svn: 300940
* [AArch64] Use suffix ULL to shift a 64-bit value.Akira Hatanaka2017-04-211-1/+1
| | | | llvm-svn: 300932
* [CodeExtractor] Remove an unneeded level of indirection. NFCI.Davide Italiano2017-04-211-11/+6
| | | | llvm-svn: 300931
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-217-37/+186
| | | | | | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300913, which broke bots because I didn't fix a call to ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of TargetLoweringOpt and TargetLowering. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300930
* Revert r300746 (SCEV analysis for or instructions).Eli Friedman2017-04-201-6/+22
| | | | | | | | There have been multiple reports of this causing problems: a compile-time explosion on the LLVM testsuite, and a stack overflow for an opencl kernel. llvm-svn: 300928
* [InstCombine] Remove the zextOrTrunc from ShrinkDemandedConstant.Craig Topper2017-04-201-4/+2
| | | | | | | | The demanded mask and the constant should always be the same width for all callers today. Also stop copying the demanded mask as its passed in. We should avoid allocating memory unless we are going to do something. The final AND to create the new constant will take care of it. llvm-svn: 300927
* X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFCMatthias Braun2017-04-203-35/+23
| | | | | | | | | | | | | | X86RegisterInfo::eliminateFrameIndex() and X86FrameLowering::getFrameIndexReference() both had logic to compute the base register. This consolidates the code. Also use MachineInstr::isReturn instead of manually enumerating tail call instructions (return instructions were not included in the previous list because they never reference frame indexes). Differential Revision: https://reviews.llvm.org/D32206 llvm-svn: 300923
* X86RegisterInfo: eliminateFrameIndex: Force SP for AfterFPPop; NFCMatthias Braun2017-04-201-3/+4
| | | | | | | | | | | | | AfterFPPop is used for tailcall/tailjump instructions. We shouldn't ever have frame-pointer/base-pointer relative addressing for those. After all the frame/base pointer should already be restored to their previous values at the return. Make this fact explicit in preparation for an upcoming refactoring. Differential Revision: https://reviews.llvm.org/D32205 llvm-svn: 300922
* Revert "[AArch64] Improve code generation for logical instructions taking"Akira Hatanaka2017-04-206-185/+36
| | | | | | | | This reverts r300913. This broke bots. llvm-svn: 300916
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-206-36/+185
| | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300913
* [InstCombine] function names start with lower-case letter; NFCSanjay Patel2017-04-202-3/+3
| | | | | | Forgot to make this fix with the signature change in r300911. llvm-svn: 300912
* [InstCombine] allow shl+shr demanded bits folds with splat constantsSanjay Patel2017-04-202-22/+17
| | | | llvm-svn: 300911
* AArch64: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-204-0/+14
| | | | | | | | Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300905
* ARM: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-202-1/+12
| | | | | | | | Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300904
* Use basicblock split block utility functionXinliang David Li2017-04-201-8/+2
| | | | | | | | | Instead of calling BasicBlock::SplitBasicBlock directly in CodeExtractor. Differential Revision: https://reviews.llvm.org/D32308 llvm-svn: 300899
* [InstCombine] allow shl demanded bits folds with splat constantsSanjay Patel2017-04-201-2/+4
| | | | | | More fixes are needed to enable the helper SimplifyShrShlDemandedBits(). llvm-svn: 300898
* [InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few ↵Craig Topper2017-04-201-4/+4
| | | | | | more places in SimplifyDemandedBits. llvm-svn: 300896
* [AArch64] Whitespace/ordering fixes for Falkor machine description. NFC.Chad Rosier2017-04-201-2/+4
| | | | llvm-svn: 300893
* [AArch64] Refine Falkor machine description for pre/post-inc and stores.Chad Rosier2017-04-201-5/+5
| | | | llvm-svn: 300892
* [InstCombine] allow ashr/lshr demanded bits folds with splat constantsSanjay Patel2017-04-201-11/+14
| | | | llvm-svn: 300888
* [InstCombine] Use APInt::isSubsetOf to simplify some code in ↵Craig Topper2017-04-201-37/+27
| | | | | | | | SimplifyDemandedBits. NFC This allows us to use less temporary APInt for And and Invert operations. llvm-svn: 300885
* Don't emit locations that need a DW_OP_stack_value in DWARF 2 & 3.Adrian Prantl2017-04-202-1/+10
| | | | | | https://bugs.llvm.org/show_bug.cgi?id=32382 llvm-svn: 300883
* ARM: handle post-indexed NEON ops where the offset isn't the access width.Tim Northover2017-04-202-14/+24
| | | | | | | | | | | Before, we assumed that any ConstantInt offset was precisely the access width, so we could use the "[rN]!" form. ISelLowering only ever created that kind, but further simplification during combining could lead to unexpected constants and incorrect codegen. Should fix PR32658. llvm-svn: 300878
* [InstCombine] Remove redundant code from SimplifyDemandedBits handling for ↵Craig Topper2017-04-201-18/+0
| | | | | | Or. The code above it is equivalent if you work through the bitwise math. llvm-svn: 300876
* [DWARF] Versioning for DWARF constants; verify FORMsPaul Robinson2017-04-202-16/+170
| | | | | | | | | | | | | Associate the version-when-defined with definitions of standard DWARF constants. Identify the "vendor" for DWARF extensions. Use this information to verify FORMs in .debug_abbrev are defined as of the DWARF version specified in the associated unit. Removed two tests that had specified DWARF v1 (which essentially does not exist). Differential Revision: http://reviews.llvm.org/D30785 llvm-svn: 300875
* [AArch64] Improve scheduling of logical operations on Falkor.Chad Rosier2017-04-201-0/+6
| | | | llvm-svn: 300871
* [Thumb-1] Fix corner cases for compressed jump tablesWeiming Zhao2017-04-201-0/+9
| | | | | | | | | | | | | | | | | | | | | Summary: When synthesized TBB/TBH is expanded, we need to avoid the case of: BaseReg is redefined after the load of branching target. E.g.: %R2 = tLEApcrelJT <jt#1> %R1 = tLDRr %R1, %R2 ==> %R2 = tLEApcrelJT <jt#1> %R2 = tLDRspi %SP, 12 %R2 = tLDRspi %SP, 12 tBR_JTr %R1 tTBB_JT %R2, %R1 ` Reviewers: jmolloy Reviewed By: jmolloy Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D32250 llvm-svn: 300870
* [CodeExtractor] Remove a bunch of unneeded constructors.Davide Italiano2017-04-201-24/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D32305 llvm-svn: 300869
* [Recycler] Add asan/msan annotations.Benjamin Kramer2017-04-201-2/+5
| | | | | | | | | | This enables use after free and uninit memory checking for memory returned by a recycler. SelectionDAG currently relies on the opcode of a free'd node being ISD::DELETED_NODE, so poke a hole in the asan poison for SDNode opcodes. This means that we won't find some issues, but only in SDag. llvm-svn: 300868
* Fix use-after-frees on memory allocated in a Recycler.Benjamin Kramer2017-04-205-12/+16
| | | | | | | | This will become asan errors once the patch lands that poisons the memory after free. The x86 change is a hack, but I don't see how to solve this properly at the moment. llvm-svn: 300867
* CodeGen: Let frame index value type match alloca addr spaceYaxun Liu2017-04-202-7/+7
| | | | | | | | | | | | | | | | | | | | | | Recently alloca address space has been added to data layout. Due to this change, pointer returned by alloca may have different size as pointer in address space 0. However, currently the value type of frame index is assumed to be of the same size as pointer in address space 0. This patch fixes that. Most targets assume alloca returning pointer in address space 0, which is the default alloca address space. Therefore it is NFC for them. AMDGCN target with amdgiz environment requires this change since it assumes alloca returning pointer to addr space 5 and its size is 32, which is different from the size of pointer in addr space 0 which is 64. Differential Revision: https://reviews.llvm.org/D32021 llvm-svn: 300864
* Remove duplicate AttributeList::removeAttributes implementationReid Kleckner2017-04-201-63/+12
| | | | | | | | | | | | | | | Have the AttributeList overload delegate to the AttrBuilder one. Simplify the AttrBuilder overload by avoiding getSlotAttributes, which creates temporary AttributeLists. Simplify `AttrBuilder::removeAttributes(AttributeList, unsigned)` by using getAttributes instead of manually iterating over slots. Extracted from https://reviews.llvm.org/D32262 NFC llvm-svn: 300863
* [DAGCombiner] use more local variables in isAlias(); NFCISanjay Patel2017-04-201-9/+11
| | | | llvm-svn: 300860
* [WebAssembly] Add known failures for wasm object file backendSam Clegg2017-04-201-0/+28
| | | | | | | | Subscribers: jfb, dschuff Differential Revision: https://reviews.llvm.org/D32300 llvm-svn: 300859
* [APInt] Rename getSignBit to getSignMaskCraig Topper2017-04-2016-91/+91
| | | | | | | | getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask. Differential Revision: https://reviews.llvm.org/D32108 llvm-svn: 300856
* [DAGCombiner] fix variable names in isAlias(); NFCISanjay Patel2017-04-201-27/+28
| | | | | | | We started with zero-based params and switched to one-based locals... Also, variables start with a capital and functions do not. llvm-svn: 300854
* [APInt] Add isSubsetOf method that can check if one APInt is a subset of ↵Craig Topper2017-04-202-1/+9
| | | | | | | | | | | | | | another without creating temporary APInts This question comes up in many places in SimplifyDemandedBits. This makes it easy to ask without allocating additional temporary APInts. The BitVector class provides a similar functionality through its (IMHO badly named) test(const BitVector&) method. Though its output polarity is reversed. I've provided one example use case in this patch. I plan to do more as a follow up. Differential Revision: https://reviews.llvm.org/D32258 llvm-svn: 300851
* [DAGCombiner] give names to repeated calcs in isAlias(); NFCISanjay Patel2017-04-201-13/+11
| | | | llvm-svn: 300850
* In SimplifyDemandedUseBits, use computeKnownBits directly to handle ConstantsCraig Topper2017-04-201-15/+4
| | | | | | | | | | | | Currently we don't explicitly process ConstantDataSequential, ConstantAggregateZero, or ConstantVector, or Undef before applying the Depth limit. Instead they occur after the depth check in the non-instruction path. For the constant types that we do handle, the code is replicated from computeKnownBits. This patch fixes the missing constant handling and the reduces the amount of code by just using computeKnownBits directly for any type of Constant. Differential Revision: https://reviews.llvm.org/D32123 llvm-svn: 300849
* [globalisel] Enable tracing the legalizer with --debug-only=legalize-mirDaniel Sanders2017-04-202-6/+32
| | | | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka, kristof.beyls Reviewed By: kristof.beyls Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31750 llvm-svn: 300847
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