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* Merging r339166:Hans Wennborg2018-08-161-7/+1
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339166 | abataev | 2018-08-07 21:21:05 +0200 (Tue, 07 Aug 2018) | 12 lines [SLP] Fix insert point for reused extract instructions. Summary: Reworked the previously committed patch to insert shuffles for reused extract element instructions in the correct position. Previous logic was incorrect, and might lead to the crash with PHIs and EH instructions. Reviewers: efriedma, javed.absar Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D50143 ------------------------------------------------------------------------ llvm-svn: 339853
* Merging r339636:Reid Kleckner2018-08-141-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339636 | rnk | 2018-08-13 18:24:35 -0700 (Mon, 13 Aug 2018) | 17 lines [BasicAA] Don't assume tail calls with byval don't alias allocas Summary: Calls marked 'tail' cannot read or write allocas from the current frame because the current frame might be destroyed by the time they run. However, a tail call may use an alloca with byval. Calling with byval copies the contents of the alloca into argument registers or stack slots, so there is no lifetime issue. Tail calls never modify allocas, so we can return just ModRefInfo::Ref. Fixes PR38466, a longstanding bug. Reviewers: hfinkel, nlewycky, gbiv, george.burgess.iv Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D50679 ------------------------------------------------------------------------ llvm-svn: 339698
* Merging r339600:Hans Wennborg2018-08-141-2/+2
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339600 | scott.linder | 2018-08-13 20:44:21 +0200 (Mon, 13 Aug 2018) | 8 lines [CodeGen] Fix assert in SelectionDAG::computeKnownBits Fix SelectionDAG::computeKnownBits asserting when handling EXTRACT_SUBVECTOR when zero extending the demanded elements mask if it is already as long as the source vector. Differential Revision: https://reviews.llvm.org/D49574 ------------------------------------------------------------------------ llvm-svn: 339664
* Merging r339411:Hans Wennborg2018-08-131-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339411 | gbiv | 2018-08-10 07:14:43 +0200 (Fri, 10 Aug 2018) | 17 lines [MemorySSA] "Fix" lifetime intrinsic handling MemorySSA currently creates MemoryAccesses for lifetime intrinsics, and sometimes treats them as clobbers. This may/may not be the best way forward, but while we're doing it, we should consider MayAlias/PartialAlias to be clobbers. The ideal fix here is probably to remove all of this reasoning about lifetimes from MemorySSA + put it into the passes that need to care. But that's a wayyy broader fix that needs some consensus, and we have miscompiles + a release branch today, and this should solve the miscompiles just as well. differential revision is D43269. Landing without an explicit LGTM (and without using the special please-autoclose-this syntax) so we can still use that revision as a place to decide what the right fix here is. ------------------------------------------------------------------------ llvm-svn: 339545
* Merging r339225:Hans Wennborg2018-08-131-16/+37
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339225 | thopre | 2018-08-08 11:35:26 +0200 (Wed, 08 Aug 2018) | 11 lines Support inline asm with multiple 64bit output in 32bit GPR Summary: Extend fix for PR34170 to support inline assembly with multiple output operands that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR as in the PR). Reviewers: bogner, t.p.northover, lattner, javed.absar, efriedma Reviewed By: efriedma Subscribers: efriedma, tra, eraman, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45437 ------------------------------------------------------------------------ llvm-svn: 339539
* Merging r339316:Hans Wennborg2018-08-091-34/+82
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339316 | hahnfeld | 2018-08-09 09:45:49 +0200 (Thu, 09 Aug 2018) | 16 lines [NVPTX] Select atomic loads and stores According to PTX ISA .volatile has the same memory synchronization semantics as .relaxed.sys, so it can be used to implement monotonic atomic loads and stores. This is important for OpenMP's atomic construct where - 'read's and 'write's are lowered to atomic loads and stores, and - an update of float or double types are lowered into a cmpxchg loop. (Note that PTX could do better because it has atom.add.f{32,64} but LLVM's atomicrmw instruction only allows integer types.) Higher levels of atomicity (like acquire and release) need additional synchronization properties which were added with PTX ISA 6.0 / sm_70. So using these instructions still results in an error. Differential Revision: https://reviews.llvm.org/D50391 ------------------------------------------------------------------------ llvm-svn: 339338
* Merging r338902:Hans Wennborg2018-08-081-39/+43
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r338902 | jgalenson | 2018-08-03 19:12:23 +0200 (Fri, 03 Aug 2018) | 5 lines Fix crash in bounds checking. In r337830 I added SCEV checks to enable us to insert fewer bounds checks. Unfortunately, this sometimes crashes when multiple bounds checks are added due to SCEV caching issues. This patch splits the bounds checking pass into two phases, one that computes all the conditions (using SCEV checks) and the other that adds the new instructions. Differential Revision: https://reviews.llvm.org/D49946 ------------------------------------------------------------------------ llvm-svn: 339239
* Merging r339190:Hans Wennborg2018-08-081-11/+0
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r339190 | jvesely | 2018-08-07 23:54:37 +0200 (Tue, 07 Aug 2018) | 12 lines AMDGPU: Remove broken i16 ternary patterns Fixup test to check for GCN prefix These patterns always zero extend the result even though it might need sign extension. This has been broken since the addition of i16 support. It has popped up in mad_sat(char) test since min(max()) combination is turned into v_med3, resulting in the following (incorrect) sequence: v_mad_i16 v2, v10, v9, v11 v_med3_i32 v2, v2, v8, v7 Fixes mad_sat(char) piglit on VI. Differential Revision: https://reviews.llvm.org/D49836 ------------------------------------------------------------------------ llvm-svn: 339235
* Merging r338716:Hans Wennborg2018-08-081-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338716 | spatel | 2018-08-02 15:46:20 +0200 (Thu, 02 Aug 2018) | 41 lines [ValueTracking] fix maxnum miscompile for cannotBeOrderedLessThanZero (PR37776) This adds the NAN checks suggested in PR37776: https://bugs.llvm.org/show_bug.cgi?id=37776 If both operands to maxnum are NAN, that should get constant folded, so we don't have to handle that case. This is the same assumption as other FP ops in this function. Returning 'false' is always conservatively correct. Copying from the bug report: Currently, we have this for "when is cannotBeOrderedLessThanZero (mustBePositiveOrNaN) true for maxnum": L ------------------- | Pos | Neg | NaN | ------------------------ |Pos | x | x | x | ------------------------ R |Neg | x | | x | ------------------------ |NaN | x | x | x | ------------------------ The cases with (Neg & NaN) are wrong. We should have: L ------------------- | Pos | Neg | NaN | ------------------------ |Pos | x | x | x | ------------------------ R |Neg | x | | | ------------------------ |NaN | x | | x | ------------------------ Differential Revision: https://reviews.llvm.org/D50081 ------------------------------------------------------------------------ llvm-svn: 339234
* Merging r338915:Hans Wennborg2018-08-071-11/+28
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r338915 | ctopper | 2018-08-03 22:14:18 +0200 (Fri, 03 Aug 2018) | 5 lines [SelectionDAG] Teach LegalizeVectorTypes to widen the mask input to a masked store. The mask operand is visited before the data operand so we need to be able to widen it. Fixes PR38436. ------------------------------------------------------------------------ llvm-svn: 339106
* Merging r338610:Hans Wennborg2018-08-072-27/+69
| | | | | | | | | | | | ------------------------------------------------------------------------ r338610 | jvesely | 2018-08-01 20:36:07 +0200 (Wed, 01 Aug 2018) | 3 lines AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS Non ext aligned i32 loads are still optimized to use CONSTANT_BUFFER (AS 8) ------------------------------------------------------------------------ llvm-svn: 339105
* Merging r338569:Hans Wennborg2018-08-072-9/+9
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r338569 | jvesely | 2018-08-01 17:04:36 +0200 (Wed, 01 Aug 2018) | 5 lines AMDGPU: Allow fp32-denormals feature for r600 targets This was accidentally removed in r335942. Differential Revision: https://reviews.llvm.org/D49934 ------------------------------------------------------------------------ llvm-svn: 339103
* Merging r338968:Hans Wennborg2018-08-071-36/+16
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338968 | echristo | 2018-08-05 16:23:37 +0200 (Sun, 05 Aug 2018) | 6 lines Revert "Add a warning if someone attempts to add extra section flags to sections" There are a bunch of edge cases and inconsistencies in how we're emitting sections cause this warning to fire and it needs more work. This reverts commit r335558. ------------------------------------------------------------------------ llvm-svn: 339099
* Merging r338665:Hans Wennborg2018-08-071-16/+12
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338665 | lliu0 | 2018-08-02 03:54:12 +0200 (Thu, 02 Aug 2018) | 11 lines Fix FCOPYSIGN expansion In expansion of FCOPYSIGN, the shift node is missing when the two operands of FCOPYSIGN are of the same size. We should always generate shift node (if the required shift bit is not zero) to put the sign bit into the right position, regardless of the size of underlying types. Differential Revision: https://reviews.llvm.org/D49973 ------------------------------------------------------------------------ llvm-svn: 339098
* Merging r338817:Hans Wennborg2018-08-071-0/+34
| | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338817 | inouehrs | 2018-08-03 07:39:48 +0200 (Fri, 03 Aug 2018) | 10 lines [InstSimplify] fold extracting from std::pair (2/2) This is the second patch of the series which intends to enable jump threading for an inlined method whose return type is std::pair<int, bool> or std::pair<bool, int>. The first patch is https://reviews.llvm.org/rL338485. This patch handles code sequences that merges two values using `shl` and `or`, then extracts one value using `and`. Differential Revision: https://reviews.llvm.org/D49981 ------------------------------------------------------------------------ llvm-svn: 339097
* Merging r338599:Hans Wennborg2018-08-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338599 | vlad.tsyrklevich | 2018-08-01 19:44:37 +0200 (Wed, 01 Aug 2018) | 16 lines [X86] FastISel fall back on !absolute_symbol GVs Summary: D25878, which added support for !absolute_symbol for normal X86 ISel, did not add support for materializing references to absolute symbols for X86 FastISel. This causes build failures because FastISel generates PC-relative relocations for absolute symbols. Fall back to normal ISel for references to !absolute_symbol GVs. Fix for PR38200. Reviewers: pcc, craig.topper Reviewed By: pcc Subscribers: hiraditya, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D50116 ------------------------------------------------------------------------ llvm-svn: 338847
* Merging r338762:Hans Wennborg2018-08-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338762 | gbiv | 2018-08-02 21:50:27 +0200 (Thu, 02 Aug 2018) | 15 lines [Support] Add an enable bit to our DebugCounters r337748 made us start incrementing DebugCounters all of the time. This makes tsan unhappy in multithreaded environments. Since it doesn't make much sense to use DebugCounters with multiple threads, this patch makes us only count anything if the user passed a -debug-counter option or if some other piece of code explicitly asks for it (e.g. the pass in D50031). The amount of global state here makes writing a unittest for this behavior somewhat awkward. So, no test is provided. Differential Revision: https://reviews.llvm.org/D50150 ------------------------------------------------------------------------ llvm-svn: 338846
* Merging r338554:Hans Wennborg2018-08-021-1/+3
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338554 | bryanpkc | 2018-08-01 15:50:29 +0200 (Wed, 01 Aug 2018) | 11 lines [AArch64] Fix FCCMP with FP16 operands Summary: This patch adds support for FCCMP instruction with FP16 operands, avoiding an assertion during instruction selection. Reviewers: olista01, SjoerdMeijer, t.p.northover, javed.absar Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D50115 ------------------------------------------------------------------------ llvm-svn: 338692
* Merging r338658:Hans Wennborg2018-08-022-3/+105
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r338658 | nemanjai | 2018-08-02 02:03:22 +0200 (Thu, 02 Aug 2018) | 13 lines [PowerPC] Do not round values prior to converting to integer Adding the FP_ROUND nodes when combining FP_TO_[SU]INT of elements feeding a BUILD_VECTOR into an FP_TO_[SU]INT of the built vector loses precision. This patch removes the code that adds these nodes to true f64 operands. It also adds patterns required to ensure the code is still vectorized rather than converting individual elements and inserting into a vector. Fixes https://bugs.llvm.org/show_bug.cgi?id=38342 Differential Revision: https://reviews.llvm.org/D50121 ------------------------------------------------------------------------ llvm-svn: 338678
* [X86] Use isNullConstant helper. NFCI.Simon Pilgrim2018-08-011-2/+1
| | | | llvm-svn: 338530
* Fix "not all control paths return a value" MSVC warning.Simon Pilgrim2018-08-011-0/+1
| | | | llvm-svn: 338529
* [MC] Report fatal error for DWARF types for non-ELF object filesJonas Devlieghere2018-08-012-3/+15
| | | | | | | | | | | | | | Getting the DWARF types section is only implemented for ELF object files. We already disabled emitting debug types in clang (r337717), but now we also report an fatal error (rather than crashing) when trying to obtain this section in MC. Additionally we ignore the generate debug types flag for unsupported target triples. See PR38190 for more information. Differential revision: https://reviews.llvm.org/D50057 llvm-svn: 338527
* [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor2018-08-014-2/+53
| | | | | | | | | | | | | | | Summary: Add _L to _LZ image intrinsic table mapping to table gen. In ISelLowering check if image intrinsic has lod and if it's equal to zero, if so remove lod and change opcode to equivalent mapped _LZ. Change-Id: Ie24cd7e788e2195d846c7bd256151178cbb9ec71 Subscribers: arsenm, mehdi_amini, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D49483 llvm-svn: 338523
* [SystemZ, TableGen] Fix shift count handlingUlrich Weigand2018-08-015-103/+35
| | | | | | | | | | | | | | | | | | | | | | | | | The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
* [X86] Use isNullConstant helper. NFCI.Simon Pilgrim2018-08-011-2/+1
| | | | llvm-svn: 338516
* [X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko2018-08-0111-48/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D49243 llvm-svn: 338507
* [MIPS GlobalISel] Select global addressPetar Jovanovic2018-08-013-0/+31
| | | | | | | | | | Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
* Revert "Enrich inline messages", tests failDavid Bolvansky2018-08-015-152/+111
| | | | llvm-svn: 338496
* Enrich inline messagesDavid Bolvansky2018-08-015-111/+152
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch improves Inliner to provide causes/reasons for negative inline decisions. 1. It adds one new message field to InlineCost to report causes for Always and Never instances. All Never and Always instantiations must provide a simple message. 2. Several functions that used to return the inlining results as boolean are changed to return InlineResult which carries the cause for negative decision. 3. Changed remark priniting and debug output messages to provide the additional messages and related inline cost. 4. Adjusted tests for changed printing. Patch by: yrouban (Yevgeny Rouban) Reviewers: craig.topper, sammccall, sgraenitz, NutshellySima, shchenz, chandlerc, apilipenko, javed.absar, tejohnson, dblaikie, sanjoy, eraman, xbolva00 Reviewed By: tejohnson, xbolva00 Subscribers: xbolva00, llvm-commits, arsenm, mehdi_amini, eraman, haicheng, steven_wu, dexonsmith Differential Revision: https://reviews.llvm.org/D49412 llvm-svn: 338494
* [AArch64] Disallow the MachO specific .loh directive for windowsMartin Storsjo2018-08-011-6/+6
| | | | | | | | Also add a test for it being unsupported for linux. Differential Revision: https://reviews.llvm.org/D49929 llvm-svn: 338493
* [X86] When looking for (CMOV C-1, (ADD (CTTZ X), C), (X != 0)) -> (ADD (CMOV ↵Craig Topper2018-08-011-27/+26
| | | | | | | | | | (CTTZ X), -1, (X != 0)), C), make sure we really have a compare with 0. It's not strictly required by the transform of the cmov and the add, but it makes sure we restrict it to the cases we know we want to match. While there canonicalize the operand order of the cmov to simplify the matching and emitting code. llvm-svn: 338492
* [DWARF] Basic support for producing DWARFv5 .debug_addr sectionVictor Leschuk2018-08-014-2/+31
| | | | | | | | | | | | | | This revision implements support for generating DWARFv5 .debug_addr section. The implementation is pretty straight-forward: we just check the dwarf version and emit section header if needed. Reviewers: aprantl, dblaikie, probinson Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D50005 llvm-svn: 338487
* [InstSimplify] fold extracting from std::pair (1/2)Hiroshi Inoue2018-08-011-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to enable jump threading when a method whose return type is std::pair<int, bool> or std::pair<bool, int> is inlined. For example, jump threading does not happen for the if statement in func. std::pair<int, bool> callee(int v) { int a = dummy(v); if (a) return std::make_pair(dummy(v), true); else return std::make_pair(v, v < 0); } int func(int v) { std::pair<int, bool> rc = callee(v); if (rc.second) { // do something } SROA executed before the method inlining replaces std::pair by i64 without splitting in both callee and func since at this point no access to the individual fields is seen to SROA. After inlining, jump threading fails to identify that the incoming value is a constant due to additional instructions (like or, and, trunc). This series of patch add patterns in InstructionSimplify to fold extraction of members of std::pair. To help jump threading, actually we need to optimize the code sequence spanning multiple BBs. These patches does not handle phi by itself, but these additional patterns help NewGVN pass, which calls instsimplify to check opportunities for simplifying instructions over phi, apply phi-of-ops optimization to result in successful jump threading. SimplifyDemandedBits in InstCombine, can do more general optimization but this patch aims to provide opportunities for other optimizers by supporting a simple but common case in InstSimplify. This first patch in the series handles code sequences that merges two values using shl and or and then extracts one value using lshr. Differential Revision: https://reviews.llvm.org/D48828 llvm-svn: 338485
* [DebugInfo] Fix build failed in clang-x86_64-linux-selfhost-modules.Hsiangkai Wang2018-08-011-1/+7
| | | | | | Only generate symbol difference expression if needed. llvm-svn: 338484
* [x86] Fix a really subtle miscompile due to a somewhat glaring bug inChandler Carruth2018-08-011-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFLAGS copy lowering. If you have a branch of LLVM, you may want to cherrypick this. It is extremely unlikely to hit this case empirically, but it will likely manifest as an "impossible" branch being taken somewhere, and will be ... very hard to debug. Hitting this requires complex conditions living across complex control flow combined with some interesting memory (non-stack) initialized with the results of a comparison. Also, because you have to arrange for an EFLAGS copy to be in *just* the right place, almost anything you do to the code will hide the bug. I was unable to reduce anything remotely resembling a "good" test case from the place where I hit it, and so instead I have constructed synthetic MIR testing that directly exercises the bug in question (as well as the good behavior for completeness). The issue is that we would mistakenly assume any SETcc with a valid condition and an initial operand that was a register and a virtual register at that to be a register *defining* SETcc... It isn't though.... This would in turn cause us to test some other bizarre register, typically the base pointer of some memory. Now, testing this register and using that to branch on doesn't make any sense. It even fails the machine verifier (if you are running it) due to the wrong register class. But it will make it through LLVM, assemble, and it *looks* fine... But wow do you get a very unsual and surprising branch taken in your actual code. The fix is to actually check what kind of SETcc instruction we're dealing with. Because there are a bunch of them, I just test the may-store bit in the instruction. I've also added an assert for sanity that ensure we are, in fact, *defining* the register operand. =D llvm-svn: 338481
* [DebugInfo] Generate fixups as emitting DWARF .debug_line.Hsiangkai Wang2018-08-012-6/+81
| | | | | | | | | | | | | | | | It is necessary to generate fixups in .debug_line as relaxation is enabled due to the address delta may be changed after relaxation. DWARF will record the mappings of lines and addresses in .debug_line section. It will encode the information using special opcodes, standard opcodes and extended opcodes in Line Number Program. I use DW_LNS_fixed_advance_pc to encode fixed length address delta and DW_LNE_set_address to encode absolute address to make it possible to generate fixups in .debug_line section. Differential Revision: https://reviews.llvm.org/D46850 llvm-svn: 338477
* [GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate.Amara Emerson2018-08-011-5/+8
| | | | | | | | | | | | Previously we were just visiting the blocks in the function in IR order, which is rather arbitrary. Therefore we wouldn't always visit defs before uses, but the translation code relies on this assumption in some places. Only codegen change seen in tests is an elision of a redundant copy. Fixes PR38396 llvm-svn: 338476
* AMDGPU: Add clamp bit to dot intrinsicsKonstantin Zhuravlyov2018-08-013-12/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D49874 llvm-svn: 338470
* Simplify selectELFSectionForGlobal by pulling out the entry sizeEric Christopher2018-08-011-22/+27
| | | | | | determination for mergeable sections into a small static function. llvm-svn: 338469
* Tidy up logic around unique section name creation and remove aEric Christopher2018-08-011-9/+9
| | | | | | mostly unused variable. llvm-svn: 338468
* [MachineOutliner] Clean up subtarget handling.Eli Friedman2018-08-011-23/+22
| | | | | | | | | | | | | | Call shouldOutlineFromFunctionByDefault, isFunctionSafeToOutlineFrom, getOutliningType, and getMachineOutlinerMBBFlags using the correct TargetInstrInfo. And don't create a MachineFunction for a function declaration. The call to getOutliningCandidateInfo is still a little weird, but at least the weirdness is explicitly called out. Differential Revision: https://reviews.llvm.org/D49880 llvm-svn: 338465
* Revert r338354 "[ARM] Revert r337821"Reid Kleckner2018-07-311-1/+1
| | | | | | | | | | | | | | | | | Disable ARMCodeGenPrepare by default again. It is causing verifier failues in V8 that look like: Duplicate integer as switch case switch i32 %trunc, label %if.end13 [ i32 0, label %cleanup36 i32 0, label %if.then8 ], !dbg !4981 i32 0 fatal error: error in backend: Broken function found, compilation aborted! I will continue reducing the test case and send it along. llvm-svn: 338452
* [DWARF] Support for .debug_addr (consumer)Victor Leschuk2018-07-313-10/+252
| | | | | | | This patch implements basic support for parsing and dumping DWARFv5 .debug_addr section. llvm-svn: 338447
* [SLC] Refactor the simplication of pow() (NFC)Evandro Menezes2018-07-311-20/+16
| | | | | | Reword comments and minor code reformatting. llvm-svn: 338446
* Revert r338431: "Add DebugCounters to DivRemPairs"George Burgess IV2018-07-311-6/+0
| | | | | | | This reverts r338431; the test it added is making buildbots unhappy. Locally, I can repro the failure on reverse-iteration builds. llvm-svn: 338442
* [DWARF] Do not create a .debug_ranges section when no ranges are needed.Wolfgang Pieb2018-07-311-1/+1
| | | | | | | | Reviewers: aprantl Differential Revision: https://reviews.llvm.org/D50089 llvm-svn: 338437
* Add DebugCounters to DivRemPairsGeorge Burgess IV2018-07-311-0/+6
| | | | | | | | | | For people who don't use DebugCounters, NFCI. Patch by Zhizhou Yang! Differential Revision: https://reviews.llvm.org/D50033 llvm-svn: 338431
* [SystemZ] Fix bad assert composition.Jonas Paulsson2018-07-311-1/+1
| | | | | | Use '&&' before the string instead of '||' llvm-svn: 338429
* DAG: Correct pointer type used for stack slotMatt Arsenault2018-07-311-1/+2
| | | | | | | | | | Correct the address space for the inserted argument stack slot. AMDGPU seems to not do anything with this information, so I don't think this was breaking anything. llvm-svn: 338428
* AMDGPU: Break 64-bit arguments into 32-bit piecesMatt Arsenault2018-07-311-3/+16
| | | | llvm-svn: 338421
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