summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86] Add all the FMA instructions direclty to the load folding table ↵Craig Topper2018-06-172-100/+544
| | | | | | | | instead of proxying through X86InstrFMA3Info. These increases the size of the static tables, but is closer to what we would get if used the autogenerated table directly. This reduces the remaining large deltas between what's in the manual table and what's in the autogenerated table. llvm-svn: 334915
* [ORC] Suppress an unused variable warning for a debug-mode only use.Lang Hames2018-06-171-0/+1
| | | | llvm-svn: 334911
* [ORC] Erase empty dependence sets when adding new symbol dependencies.Lang Hames2018-06-171-0/+3
| | | | llvm-svn: 334910
* [ORC] In MaterializationResponsibility, only maintain the Materializing flag onLang Hames2018-06-171-2/+12
| | | | | | | | | | | symbols in debug mode. The MaterializationResponsibility class hijacks the Materializing flag to track symbols that have not yet been resolved in order to guard against redundant resolution. Since this is an API contract check and only enforced in debug mode there is no reason to maintain the flag state in release mode. llvm-svn: 334909
* [X86] Pass the parent SDNode to X86DAGToDAGISel::selectScalarSSELoad to ↵Craig Topper2018-06-172-14/+12
| | | | | | | | | | simplify the hasSingleUseFromRoot handling. Some of the calls to hasSingleUseFromRoot were passing the load itself. If the load's chain result has a user this would count against that. By getting the true parent of the match and ensuring any intermediate between the match and the load have a single use we can avoid this case. isLegalToFold will take care of checking users of the load's data output. This fixed at least fma-scalar-memfold.ll to succed without the peephole pass. llvm-svn: 334908
* [AArch64][SVE] Asm: Support for bitwise operations on predicate vectors.Sander de Smalen2018-06-171-0/+29
| | | | | | | | | | | | | | | | | | | This patch adds support for instructions performing bitwise operations on predicate vectors, including AND, BIC, EOR, NAND, NOR, ORN, ORR, and their status flag setting variants ANDS, BICS, EORS, NANDS, ORNS, ORRS. This patch also adds several aliases: orr p0.b, p1/z, p1.b, p1.b => mov p0.b, p1.b orrs p0.b, p1/z, p1.b, p1.b => movs p0.b, p1.b and p0.b, p1/z, p2.b, p2.b => mov p0.b, p1/z, p2.b ands p0.b, p1/z, p2.b, p2.b => movs p0.b, p1/z, p2.b eor p0.b, p1/z, p2.b, p1.b => not p0.b, p1/z, p2.b eors p0.b, p1/z, p2.b, p1.b => nots p0.b, p1/z, p2.b llvm-svn: 334906
* [AArch64][SVE] Asm: Support for SEL (vector/predicate) instructions.Sander de Smalen2018-06-172-0/+81
| | | | | | | | Support for SVE's predicated select instructions to select elements from either vector, both in a data-vector and a predicate-vector variant. llvm-svn: 334905
* [NVPTX] Ignore target-cpu and -features for inliningJonas Hahnfeld2018-06-171-0/+8
| | | | | | | | | | We don't want to prevent inlining because of target-cpu and -features attributes that were added to newer versions of LLVM/Clang: There are no incompatible functions in PTX, ptxas will throw errors in such cases. Differential Revision: https://reviews.llvm.org/D47691 llvm-svn: 334904
* [WebAssembly] Simple comment fix. NFC.Heejin Ahn2018-06-171-1/+1
| | | | llvm-svn: 334899
* [X86] More additions to the load folding tables based on the autogenerated ↵Craig Topper2018-06-165-33/+814
| | | | | | | | tables. Including more additions for NotMemoryFoldable to remove some entries from the autogenerated table. llvm-svn: 334898
* [X86] Hide POP16/32/64rmr and PUSH16/32/64rmr instructions from the assembly ↵Craig Topper2018-06-161-0/+12
| | | | | | | | parser. These all have a short form encoding that the assembler already prefers. Though that preference seems to only be based on order in the .td fie. Hiding the long form saves space in the table and prevents us from breaking the implicit order based priority. llvm-svn: 334897
* [X86] Fix an inconsistency between AVX512 and AVX/SSE version on a couple ↵Craig Topper2018-06-161-2/+2
| | | | | | | | | | instructions. VMOVPQIto64Zmr is not a 64-bit mode only instruction. But I don't know how to test this because VMOVPQIto64mr should always have priority over it in 32-bit mode since its only advantage is XMM16-XMM31 which aren't usable in 32-bit mode. VMOVPQIto64Zrr is a 64-bit mode only instruction, but we don't need to explicitly mark it as such because it uses a GR64 register which won't parse in 32-bit mode. llvm-svn: 334896
* CorrelatedValuePropagation: Preserve DT.Michael Zolotukhin2018-06-161-5/+18
| | | | | | | | | | | | | | Summary: We only modify CFG in a couple of places, and we can preserve DT there with a little effort. Reviewers: davide, vsk Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48059 llvm-svn: 334895
* Fix namespaces. No functionality change.Benjamin Kramer2018-06-162-1/+3
| | | | llvm-svn: 334890
* [AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | ccStanislav Mekhanoshin2018-06-161-17/+43
| | | | | | | | | This is the common case in the BE when we serialize condition and then rematerialize it. Use either original or inverted condition. Differential Revision: https://reviews.llvm.org/D48246 llvm-svn: 334882
* Avoid needing to walk out legalization tables. NFCI.Nirav Dave2018-06-162-193/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Relanding after fixing expensive check from modifying tables. To avoid redundant work, during DAG legalization we keep tables mapping pre-legalized SDValues to post-legalized SDValues and a SDValue-to-SDValue map to enable fast node replacements. However, as the keys are nodes which may be reused it is possible that an entry in a table refers to a now deleted node N (that should have been renamed by the value replacement map) while a new node N' exists. If N' is then replaced that entry would be wrong. Previously we avoided this by when potentially violating this property, walking every table and updating all node pointers. This is very expensive but hopefully rare occurance. This patch assigns each instance of a SDValue used in legalization a unique id and uses these ids in the legalization tables. This avoids any such aliasing issue, avoiding the full table search and allowing more aggressive incremental table pruning. In some cases this is a 1000x speedup to compilation. Reviewers: jyknight, echristo, bogner, tra Reviewed By: bogner Subscribers: dberris, grandinj, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D47959 llvm-svn: 334880
* Revert "[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV." -- breaks MSVC builds.Justin Lebar2018-06-161-34/+38
| | | | | | This reverts D48237. llvm-svn: 334878
* Revert "[SCEV] Simplify some flags expressions." -- dependent revision ↵Justin Lebar2018-06-161-4/+4
| | | | | | | | breaks MSVC builds. This reverts D48238. llvm-svn: 334877
* Utilize new SDNode flag functionality to expand current support for fmaMichael Berg2018-06-161-18/+14
| | | | | | | | | | | | | | Summary: This patch originated from D47388 and is a proper subset of the originating changes, containing only the fmf optimization guard extensions. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar, rampitec, nhaehnle, nemanjai Reviewed By: rampitec, nhaehnle Subscribers: tpr, nemanjai, wdng Differential Revision: https://reviews.llvm.org/D47918 llvm-svn: 334876
* [SCEV] Simplify some flags expressions.Justin Lebar2018-06-151-4/+4
| | | | | | | | | | | | | | Summary: Sending for presubmit review out of an abundance of caution; it would be bad to mess this up. Reviewers: sanjoy Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48238 llvm-svn: 334875
* [SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV.Justin Lebar2018-06-151-38/+34
| | | | | | | | | | | | | | | | | | Summary: Obviates the need for mask/clear/setFlags helpers. There are some expressions here which can be simplified, but to keep this easy to review, I have not simplified them in this patch. No functional change. Reviewers: sanjoy Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D48237 llvm-svn: 334874
* [globalisel][tablegen] Add support for C++ predicates on PatFrags and use it ↵Daniel Sanders2018-06-151-0/+10
| | | | | | | | | | | | | | | | | | | | | to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
* Revert r334729 "[DAG] Avoid needing to walk out legalization tables. NFCI."Francis Visoiu Mistrih2018-06-152-155/+193
| | | | | | This reverts commit r334729. llvm-svn: 334869
* Revert r334731 "Avoid unused variable in non-assert builds."Francis Visoiu Mistrih2018-06-151-1/+0
| | | | | | | | This reverts commit r334731. It breaks EXPENSIVE_CHECKS bots. llvm-svn: 334868
* [X86] Add more instructions to the hasUndefRegUpdate list.Craig Topper2018-06-151-0/+31
| | | | | | Not sure any of these matter today because I don't think we ever produce them with IMPLICIT_DEF as an input. But by listing them we don't be suprised in the future. llvm-svn: 334867
* [BPI] Remove unnecessary std::listBenjamin Kramer2018-06-151-5/+4
| | | | | | vector is sufficient here. No functionality change intended. llvm-svn: 334865
* [FPEnv] Expand constrained FP POWICameron McInally2018-06-152-4/+22
| | | | | | | | | | | | Modify ExpandStrictFPOp(...) to handle nodes that have scalar operands. Also, add a Strict FMA test and do some other light cleanup in the Strict FP code. Differential Revision: https://reviews.llvm.org/D48149 llvm-svn: 334863
* Utilize new SDNode flag functionality to expand current support for fdivMichael Berg2018-06-151-1/+1
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed. Reviewers: spatel, hfinkel, wristow, arsenm Reviewed By: spatel Subscribers: wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D47954 llvm-svn: 334862
* [SanitizerCoverage] Add associated metadata to pc-tables.Matt Morehouse2018-06-151-1/+5
| | | | | | | | | | | | | | | | | | | | Summary: Using associated metadata rather than llvm.used allows linkers to perform dead stripping with -fsanitize-coverage=pc-table. Unfortunately in my local tests, LLD was the only linker that made use of this metadata. Partially addresses https://bugs.llvm.org/show_bug.cgi?id=34636 and fixes https://github.com/google/sanitizers/issues/971. Reviewers: eugenis Reviewed By: eugenis Subscribers: Dor1s, hiraditya, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D48203 llvm-svn: 334858
* [PowerPC] Add support for high and higha symbol modifiers on tls modifers.Sean Fertile2018-06-153-0/+24
| | | | | | | | | | Enables using the high and high-adjusted symbol modifiers on thread local storage modifers in powerpc assembly. Needed to be able to support 64 bit thread-pointer and dynamic-thread-pointer access sequences. Differential Revision: https://reviews.llvm.org/D47754 llvm-svn: 334856
* [PPC64] Support "symbol@high" and "symbol@higha" symbol modifers.Sean Fertile2018-06-156-0/+40
| | | | | | | | | | Add support for the "@high" and "@higha" symbol modifiers in powerpc64 assembly. The modifiers represent accessing the segment consiting of bits 16-31 of a 64-bit address/offset. Differential Revision: https://reviews.llvm.org/D47729 llvm-svn: 334855
* [X86] Lowering sqrt intrinsics to native IRTomasz Krupa2018-06-155-60/+91
| | | | | | | | | | | | | | Summary: Complementary patch to lowering sqrt intrinsics in Clang. Reviewers: craig.topper, spatel, RKSimon, DavidKreitzer, uriel.k Reviewed By: craig.topper Subscribers: tkrupa, mike.dvoretsky, llvm-commits Differential Revision: https://reviews.llvm.org/D41599 llvm-svn: 334849
* [X86] Prevent folding stack reloads into instructions in hasUndefRegUpdate.Craig Topper2018-06-151-4/+10
| | | | | | An earlier commit prevented folds from the peephole pass by checking for IMPLICIT_DEF. But later in the pipeline IMPLICIT_DEF just becomes and Undef flag on the input register so we need to check for that case too. llvm-svn: 334848
* Remove <undef> from rematerialized full registerKrzysztof Parzyszek2018-06-151-0/+5
| | | | | | | | | | | When coalescing a small register into a subregister of a larger register, if the larger register is rematerialized, the function updateRegDefUses can add an <undef> flag to the rematerialized definition (since it's treating it as only definining the coalesced subregister). While with that assumption doing so is not incorrect, make sure to remove the flag later on after the call to updateRegDefUses. llvm-svn: 334845
* [InstCombine] Avoid iteration/mutation conflictJoseph Tremoulet2018-06-151-1/+2
| | | | | | | | | | | | | | | | | | Summary: When iterating users of a multiply in processUMulZExtIdiom, the call to setOperand in the truncation case may replace the use being visited; make sure the iterator has been advanced before doing that replacement. Reviewers: majnemer, davide Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48192 llvm-svn: 334844
* [AArch64][SVE] Asm: Support for CPY SIMD/FP and GPR instructions.Sander de Smalen2018-06-152-0/+79
| | | | | | | Predicated splat/copy of SIMD/FP register or general purpose register to SVE vector, along with MOV-aliases. llvm-svn: 334842
* Avoid copying PrettyStackTrace messages an extra time on Apple OSsJordan Rose2018-06-151-2/+2
| | | | | | | | We were unnecessarily going from SmallString to std::string just to get a null-terminated C string. So just...don't do that. Crash slightly faster! llvm-svn: 334841
* [LV] Prevent LV to run cost model twice for VF=2Diego Caballero2018-06-151-3/+4
| | | | | | | | | | | | | | This is a minor fix for LV cost model, where the cost for VF=2 was computed twice when the vectorization of the loop was forced without specifying a VF. Reviewers: xusx595, hsaito, fhahn, mkuper Reviewed By: hsaito, xusx595 Differential Revision: https://reviews.llvm.org/D48048 llvm-svn: 334840
* [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions.Sander de Smalen2018-06-155-12/+105
| | | | | | | | | | | | | Increment/decrement scalar register by (scaled) element count given by predicate pattern, e.g. 'incw x0, all, mul #4'. Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47713 llvm-svn: 334838
* AMDGPU: Add combine for short vector extract_vector_eltsMatt Arsenault2018-06-151-1/+42
| | | | | | | | | | Try to access pieces 4 bytes at a time. This helps various hasOneUse extract_vector_elt combines, such as load width reductions. Avoids test regressions in a future commit. llvm-svn: 334836
* AMDGPU: Make v4i16/v4f16 legalMatt Arsenault2018-06-158-92/+235
| | | | | | | Some image loads return these, and it's awkward working around them not being legal. llvm-svn: 334835
* [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.Sander de Smalen2018-06-153-0/+57
| | | | | | | | | | Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: javed.absar Differential Revision: https://reviews.llvm.org/D47712 llvm-svn: 334831
* Re-apply "[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue"Bjorn Pettersson2018-06-152-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is r334704 (which was reverted in r334732) with a fix for types like x86_fp80. We need to use getTypeAllocSizeInBits and not getTypeStoreSizeInBits to avoid dropping debug info for such types. Original commit msg: > Summary: > Do not convert a DbgDeclare to DbgValue if the store > instruction only refer to a fragment of the variable > described by the DbgDeclare. > > Problem was seen when for example having an alloca for an > array or struct, and there were stores to individual elements. > In the past we inserted a DbgValue intrinsics for each store, > just as if the store wrote the whole variable. > > When handling store instructions we insert a DbgValue that > indicates that the variable is "undefined", as we do not know > which part of the variable that is updated by the store. > > When ConvertDebugDeclareToDebugValue is used with a load/phi > instruction we assert that the referenced value is large enough > to cover the whole variable. Afaict this should be true for all > scenarios where those methods are used on trunk. If the assert > blows in the future I guess we could simply skip to insert a > dbg.value instruction. > > In the future I think we should examine which part of the variable > that is accessed, and add a DbgValue instrinsic with an appropriate > DW_OP_LLVM_fragment expression. > > Reviewers: dblaikie, aprantl, rnk > > Reviewed By: aprantl > > Subscribers: JDevlieghere, llvm-commits > > Tags: #debug-info > > Differential Revision: https://reviews.llvm.org/D48024 llvm-svn: 334830
* [mips] Add licensing information of the microMIPS tablegen files. (NFC)Simon Dardis2018-06-152-0/+26
| | | | llvm-svn: 334827
* [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates.Sander de Smalen2018-06-158-46/+164
| | | | | | | | | | | | | | | | Some instructions require of a limited set of FP immediates as operands, for example '#0.5 or #1.0' for SVE's FADD instruction. This patch adds support for parsing and printing such FP immediates as exact values (e.g. #0.499999 is not accepted for #0.5). Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47711 llvm-svn: 334826
* DAG: Fix creating concat_vectors with illegal typeMatt Arsenault2018-06-151-3/+6
| | | | | | | Test passes as is, but fails with future patch to make v4i16/v4f16 legal. llvm-svn: 334823
* [InstCombine] Recommit: Fold (x << y) >> y -> x & (-1 >> y)Roman Lebedev2018-06-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Summary: We already do it for splat constants, but not just values. Also, undef cases are mostly non-functional. The original commit was reverted because it broke tests for amdgpu backend, which i didn't check. Now, the backed was updated to recognize these new patterns, so we are good. https://bugs.llvm.org/show_bug.cgi?id=37603 https://rise4fun.com/Alive/cplX Reviewers: spatel, craig.topper, mareko, bogner, rampitec, nhaehnle, arsenm Reviewed By: spatel, rampitec, nhaehnle Subscribers: wdng, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D47980 llvm-svn: 334818
* [AMDGPU] Recognize x & ~(-1 << y) pattern.Roman Lebedev2018-06-151-0/+6
| | | | | | | | | | | | | | | | Summary: The same pattern as D48010, but this one is IR-canonical as of D47428. Reviewers: nhaehnle, bogner, tstellar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #amdgpu Differential Revision: https://reviews.llvm.org/D48012 llvm-svn: 334817
* [AMDGPU] Recognize x & ((1 << y) - 1) pattern.Roman Lebedev2018-06-151-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: As a followup for D48007. Since we already handle `x << (bitwidth - y) >> (bitwidth - y)` pattern, which does not have ub for both the edge cases (`y == 0`, `y == bitwidth`), i think also handling a pattern that is ub for `y == bitwidth` should be fine. Reviewers: nhaehnle, bogner, tstellar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #amdgpu Differential Revision: https://reviews.llvm.org/D48010 llvm-svn: 334816
* [AMDGPU] Recognize x & (-1 >> (32 - y)) pattern.Roman Lebedev2018-06-151-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: D47980 will canonicalize the `x << (32 - y) >> (32 - y)`, which is the pattern the AMDGPU expects to `x & (-1 >> (32 - y))`, which is not recognized by AMDGPU. Thus, it needs to be recognized, too. Reviewers: nhaehnle, bogner, tstellar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #amdgpu Differential Revision: https://reviews.llvm.org/D48007 llvm-svn: 334815
OpenPOWER on IntegriCloud