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* [PowerPC] Fix label address calculation for ppc32Strahinja Petrovic2018-06-191-3/+4
| | | | | | | | This patch fixes calculating address of label on ppc32 (for -fPIC). Differential Revision: https://reviews.llvm.org/D46582 llvm-svn: 335043
* [InstCombine] Replacing X86-specific rounding intrinsics with generic floor-ceilMikhail Dvoretckii2018-06-191-2/+128
| | | | | | | | | | | | This patch replaces calls to X86-specific intrinsics with floor-ceil semantics with calls to target-independent @llvm.floor.* and @llvm.ceil.* intrinsics. This doesn't affect the resulting machine code, as those intrinsics are lowered to the same instructions, but exposes these specific rounding cases to generic optimizations. Differential Revision: https://reviews.llvm.org/D48067 llvm-svn: 335039
* [X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patternsMikhail Dvoretckii2018-06-193-5/+118
| | | | | | | | | | | This patch handles back-end folding of generic patterns created by lowering the X86 rounding intrinsics to native IR in cases where the instruction isn't a straightforward packed values rounding operation, but a masked operation or a scalar operation. Differential Revision: https://reviews.llvm.org/D45203 llvm-svn: 335037
* [LoopSimplifyCFG] Invalidate SCEV in LoopSimplifyCFGDavid Green2018-06-191-3/+7
| | | | | | | | | | LoopSimplifyCFG, being a loop pass, needs to preserve scalar evolution. This invalidates SE for the loops altered during block merging. Differential Revision: https://reviews.llvm.org/D48258 llvm-svn: 335036
* [SLPVectorizer] Pull out AltOpcode determination from reorderAltShuffleOperands.Simon Pilgrim2018-06-191-6/+8
| | | | | | Minor step towards making the alternate opcode system work with a wider range of opcode pairs. llvm-svn: 335032
* Remove valueCoversEntireFragment asserts in ConvertDebugDeclareToDebugValueBjorn Pettersson2018-06-191-6/+0
| | | | | | | | | | | | | | This is a fixup for r334830 causing problems in polly-aosp buildbot. Focus in r334830 was to fix a problem seen with ConvertDebugDeclareToDebugValue involving store instructions. It also added some asserts to find out of similar problems existed for the ConvertDebugDeclareToDebugValue functions involving load and phi instructions. One of those asserts seems to blow in the polly-aosp buildbot, so I'll revert the asserts while debugging. llvm-svn: 335031
* [LoopInterchange] Move PHI handling to adjustLoopBranches.Florian Hahn2018-06-191-30/+40
| | | | | | | | | | | | | | | | | | | | | This patch moves the logic to handle reduction PHI nodes to the end of adjustLoopBranches. Reduction PHI nodes in the outer loop header can be moved to the inner loop header and reduction PHI nodes from the inner loop header can be moved to the outer loop header. In the latter situation, we have to deal with 1 kind of PHI nodes: PHI nodes that are part of inner loop-only reductions. We can replace the PHI node with the value coming from outside the inner loop. Reviewers: mcrosier, efriedma, karthikthecool Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D46198 llvm-svn: 335027
* Test commit.Mikhail Dvoretckii2018-06-191-1/+1
| | | | llvm-svn: 335026
* If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction ↵QingShan Zhang2018-06-192-11/+23
| | | | | | | | | | | when we are loading a floating, and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction. Differential Revision: https://reviews.llvm.org/D47568 Reviewed By: Nemanjai llvm-svn: 335024
* [SimplifyIndVars] Eliminate redundant truncsMax Kazantsev2018-06-191-0/+92
| | | | | | | | | | | | | | | | | | | | | | | This patch adds logic to deal with the following constructions: %iv = phi i64 ... %trunc = trunc i64 %iv to i32 %cmp = icmp <pred> i32 %trunc, %invariant Replacing it with %iv = phi i64 ... %cmp = icmp <pred> i64 %iv, sext/zext(%invariant) In case if it is legal. Specifically, if `%iv` has signed comparison users, it is required that `sext(trunc(%iv)) == %iv`, and if it has unsigned comparison uses then we require `zext(trunc(%iv)) == %iv`. The current implementation bails if `%trunc` has other uses than `icmp`, but in theory we can handle more cases here (e.g. if the user of trunc is bitcast). Differential Revision: https://reviews.llvm.org/D47928 Reviewed By: reames llvm-svn: 335020
* [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td ↵Craig Topper2018-06-192-65/+128
| | | | | | | | | | | | | | files. Remove remaining manual table entries from the tablegen emitter. This adds an EVEX2VEXOverride string to the X86 instruction class in X86InstrFormats.td. If this field is set it will add manual entry in the EVEX->VEX tables that doesn't check the encoding information. Then use this mechanism to map VMOVDU/A8/16, 128-bit VALIGN, and VPSHUFF/I instructions to VEX instructions. Finally, remove the manual table from the emitter. This has the bonus of fully sorting the autogenerated EVEX->VEX tables by their EVEX instruction enum value. We may be able to use this to do a binary search for the conversion and get rid of the need to create a DenseMap. llvm-svn: 335018
* [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have ↵Craig Topper2018-06-192-7/+12
| | | | | | | | | | | | | | VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity. The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1. This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0. This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler. llvm-svn: 335017
* Revert "[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags"Sanjoy Das2018-06-191-19/+6
| | | | | | | | | | | | | | This reverts r334428. It incorrectly marks some multiplications as nuw. Tim Shen is working on a proper fix. Original commit message: [SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags where safe. Summary: Previously we would add them for adds, but not multiplies. llvm-svn: 335016
* [X86] Simplify the TSFlags checking code in EvexToVexInstPass. NFCICraig Topper2018-06-191-16/+6
| | | | | | The code was previously checking the L2 and L flag on 3 separate lines, treating the combination as an encoding. Instead its better to think of the L2 bit as being something that can't be done with VEX and early returning. Then we just need to check the L bit. llvm-svn: 335015
* [WebAssembly] Add more utility functionsHeejin Ahn2018-06-194-17/+192
| | | | | | | | | | | | | | | | Summary: Added more utility functions that will be used in EH-related passes Also changed `LoopBottom` function to `getBottom` and uses templates to be able to handle other classes as well, which will be used in CFGSort later. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48262 llvm-svn: 335006
* [WebAssembly] Add WasmEHFuncInfo for unwind destination informationHeejin Ahn2018-06-193-19/+91
| | | | | | | | | | | | | | | Summary: Add WasmEHFuncInfo and routines to calculate and fill in this struct to keep track of unwind destination information. This will be used in other EH related passes. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D48263 llvm-svn: 335005
* [WebAssembly] Make rethrow instruction take a target BB argumentHeejin Ahn2018-06-181-2/+5
| | | | | | | | | | | | | | | | | | | | | Summary: This patch changes the rethrow instruction to take a BB argument in LLVM backend, like `br` and `br_if`s. This BB is a target catch BB the rethrow instruction unwinds to. This BB argument will be converted to an relative depth immediate at the end of CFGStackify pass, as in the same way of branches. RETHROW_TO_CALLER is a codegen-only instruction that should be used when a rethrow instruction does not have an unwind destination BB, i.e., it should rethrow to its caller function. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48260 llvm-svn: 334998
* Utilize new SDNode flag functionality to expand current support for faddMichael Berg2018-06-182-29/+15
| | | | | | | | | | | | | | Summary: This patch originated from D46562 and is a proper subset, with some issues addressed. Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar Reviewed By: spatel Subscribers: wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D47909 llvm-svn: 334996
* [X86] Remove ReadAfterLd from avx512_shift_rmbi multiclass.Craig Topper2018-06-181-1/+1
| | | | | | The instructions that use this class don't have another source register. So I think this was just marking one of the address operands as ReadAfterLd? llvm-svn: 334994
* Revert "Simplify blockaddress usage before giving up in ↵Xin Tong2018-06-181-8/+1
| | | | | | | | | | | MergeBlockIntoPredecessor" This reverts commit f976cf4cca0794267f28b54e468007fd476d37d9. I am reverting this because it causes break in a few bots and its going to take me sometime to look at this. llvm-svn: 334993
* Simplify blockaddress usage before giving up in MergeBlockIntoPredecessorXin Tong2018-06-181-1/+8
| | | | | | | | | | | | | | | | | Summary: Simplify blockaddress usage before giving up in MergeBlockIntoPredecessor This is a missing small optimization in MergeBlockIntoPredecessor. This helps with one simplifycfg test which expects this case to be handled. Reviewers: davide, spatel, brzycki, asbirlea Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48284 llvm-svn: 334992
* Tidy comment language and explanation.Eric Christopher2018-06-181-5/+5
| | | | llvm-svn: 334990
* Pull non-lazy stub table emission into a separate function alongsideEric Christopher2018-06-181-41/+47
| | | | | | | the individual stub creation to increase readability a bit in the non-object file format specific function. llvm-svn: 334989
* Add return statements to make it clear that all of these are mutually ↵Eric Christopher2018-06-181-0/+4
| | | | | | | | exclusive conditions. else if would have worked just as well, but this keeps the original readability a bit more clear. llvm-svn: 334988
* [WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.Wouter van Oortmerssen2018-06-1811-419/+634
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
* refactor of visitFADD for AllowNewConst casesMichael Berg2018-06-181-17/+20
| | | | | | | | | | | | | | Summary: Refactoring for all constant cases which require AllowNewConst and some staging for future fmf usage. Reviewers: spatel, hfinkel, wristow Reviewed By: spatel Subscribers: nhaehnle Differential Revision: https://reviews.llvm.org/D48289 llvm-svn: 334984
* [AArch64][SVE] Asm: Fix predicate pattern diagnostics.Sander de Smalen2018-06-181-4/+6
| | | | | | | | | | | | | | | This patch uses the DiagnosticPredicate for SVE predicate patterns to improve their diagnostics, now giving a 'invalid operand' diagnostic if the type is not an immediate or one of the expected pattern labels. Reviewers: samparker, SjoerdMeijer, javed.absar, fhahn Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D48220 llvm-svn: 334983
* [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.Sander de Smalen2018-06-186-14/+148
| | | | | | | | | | | | | | | | | | | | | | | The variants added by this patch are: - SQINC signed increment, e.g. sqinc x0, w0, all, mul #4 - SQDEC signed decrement, e.g. sqdec x0, w0, all, mul #4 - UQINC unsigned increment, e.g. uqinc w0, all, mul #4 - UQDEC unsigned decrement, e.g. uqdec w0, all, mul #4 This patch includes asmparser changes to parse a GPR64 as a GPR32 in order to satisfy the constraint check: x0 == GPR64(w0) in: sqinc x0, w0, all, mul #4 ^___^ (must match) Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47716 llvm-svn: 334980
* [WebAssembly] Cleaned up register accessors in WebAssemblyMachineFunctionInfo.hWouter van Oortmerssen2018-06-181-10/+14
| | | | | | | | Tested: llvm-lit -v `find test -name WebAssembly` (This is a commit access "test commit" :) llvm-svn: 334979
* [X86] Encode the EVEX2VEX exception list information in .td files instead of ↵Craig Topper2018-06-182-15/+38
| | | | | | | | the emitter source. Rather than having an exclusion list in tablegen sources, add a flag to the X86 instruction records that can be used to suppress checking for convertibility. llvm-svn: 334971
* [NFC] make MIFlag accessor functions consistant with usage modelMichael Berg2018-06-181-1/+1
| | | | llvm-svn: 334970
* [VPlan] Add VPInstruction to VPRecipe transformation.Florian Hahn2018-06-184-0/+112
| | | | | | | | | | | | | | This patch introduces a VPInstructionToVPRecipe transformation, which allows us to generate code for a VPInstruction based VPlan re-using the existing infrastructure. Reviewers: dcaballe, hsaito, mssimpso, hfinkel, rengolin, mkuper, javed.absar, sguggill Reviewed By: dcaballe Differential Revision: https://reviews.llvm.org/D46827 llvm-svn: 334969
* [ORC] Add an initial implementation of a replacement CompileOnDemandLayer.Lang Hames2018-06-183-1/+346
| | | | | | | | | CompileOnDemandLayer2 is a replacement for CompileOnDemandLayer built on the ORC Core APIs. Functions in added modules are extracted and compiled lazily. CompileOnDemandLayer2 supports multithreaded JIT'd code, and compilation on multiple threads. llvm-svn: 334967
* [ORC] Keep weak flag on VSO symbol tables during materialization, but treatLang Hames2018-06-181-8/+7
| | | | | | | | | | | | materializing weak symbols as strong. This removes some elaborate flag tweaking and plays nicer with RuntimeDyld, which relies of weak/common flags to determine whether it should emit a given weak definition. (Switching to strong up-front makes it appear as if there is already an overriding definition, which would require an extra back-channel to override). llvm-svn: 334966
* Shrink interval after moving copy in removePartialRedundancyKrzysztof Parzyszek2018-06-181-0/+2
| | | | llvm-svn: 334963
* Fix typoed cast to avoid assertion in MCFragment::dump.Nirav Dave2018-06-181-1/+1
| | | | llvm-svn: 334959
* [SLPVectorizer] Tidyup isShuffle helperSimon Pilgrim2018-06-181-31/+10
| | | | | | | | | | Ensure we keep track of the input vectors in all cases instead of just for SK_Select. Ideally we'd reuse the shuffle mask pattern matching in TargetTransformInfo::getInstructionThroughput here to easily add support for all TargetTransformInfo::ShuffleKind without mass code duplication, I've added a TODO for now but D48236 should help us here. Differential Revision: https://reviews.llvm.org/D48023 llvm-svn: 334958
* [VPlanRecipeBase] Add eraseFromParent().Florian Hahn2018-06-182-0/+9
| | | | | | | | | | Reviewers: dcaballe, hsaito, mkuper, hfinkel Reviewed By: dcaballe Differential Revision: https://reviews.llvm.org/D48081 llvm-svn: 334951
* [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) instructions.Sander de Smalen2018-06-182-0/+51
| | | | | | | | | | | | | | | | | | Summary: The variants added by this patch are: - SQINC (signed increment) - UQINC (unsigned increment) - SQDEC (signed decrement) - UQDEC (unsigned decrement) For example: uqincw x0, all, mul #4 Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Differential Revision: https://reviews.llvm.org/D47715 llvm-svn: 334948
* [X86][BtVer2] Flag AVX2+ scheduler classes as unsupportedSimon Pilgrim2018-06-181-20/+20
| | | | | | | | Jaguar only supports up to AVX1 Differential Revision: https://reviews.llvm.org/D48274 llvm-svn: 334947
* [VPlan] Fix sanitizer problem with insertBefore.Florian Hahn2018-06-181-2/+2
| | | | llvm-svn: 334943
* [SLPVectorizer] Avoid calling const VL.size() repeatedly in for-loop. NFCI.Simon Pilgrim2018-06-181-1/+1
| | | | llvm-svn: 334934
* [VPlanRecipeBase] Add insertBefore helper.Florian Hahn2018-06-182-0/+12
| | | | | | | | | | Reviewers: dcaballe, mkuper, hfinkel, hsaito, mssimpso Reviewed By: dcaballe Differential Revision: https://reviews.llvm.org/D48080 llvm-svn: 334933
* [AArch64][SVE] Asm: Support for vector element compares.Sander de Smalen2018-06-182-0/+102
| | | | | | | | | | | | | | | | This patch adds instructions for comparing elements from two vectors, e.g. cmpgt p0.s, p0/z, z0.s, z1.s and also adds support for comparing to a 64-bit wide element vector, e.g. cmpgt p0.s, p0/z, z0.s, z1.d The patch also contains aliases for certain comparisons, e.g.: cmple p0.s, p0/z, z0.s, z1.s => cmpge p0.s, p0/z, z1.s, z0.s cmplo p0.s, p0/z, z0.s, z1.s => cmphi p0.s, p0/z, z1.s, z0.s cmpls p0.s, p0/z, z0.s, z1.s => cmphs p0.s, p0/z, z1.s, z0.s cmplt p0.s, p0/z, z0.s, z1.s => cmpgt p0.s, p0/z, z1.s, z0.s llvm-svn: 334931
* [X86] Fix NOOP sched overrides on BDW/HSW/SKL.Clement Courbet2018-06-183-6/+3
| | | | | | | | | | | | Summary: Noop certainly does not use resources. Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits, gchatelet Differential Revision: https://reviews.llvm.org/D48028 llvm-svn: 334927
* [X86] Create X86InstrFMA3Group objects fully in a static table instead of on ↵Craig Topper2018-06-182-227/+146
| | | | | | | | | | | | | | the heap. NFCI Previously we heap allocated the X86InstrFMA3Group objects which were created by passing them small register/memory opcode arrays that existed as individual static tables. Rather than a bunch of small static arrays we now have one large static table of X86InstrFMA3Group objects. Rather than storing a pointer to the opcode arrays in the X86InstrFMA3Group object, we now store have a register and memory array as part of the object. If a group doesn't have memory or register opcodes, the array entries will be 0. This greatly simplifies the destruction of the X86InstrFMA3Info object. We no longer need to delete the X86InstrFMA3Group objects as we destruct the DenseMap. And we don't need to keep track of which ones we already deleted. This reduces the llc binary size on my local machine by ~50k. I can only assume that's really due to the fact that we had something like 512 small static arrays that we passed to the init functions either one at a time or in pairs. So there were between 256 and 512 distinct calls to the init functions in the initOnceImpl method. llvm-svn: 334925
* [X86] Add '.s' aliases to the assembler for the various redundant move ↵Craig Topper2018-06-184-6/+77
| | | | | | | | | | encodings to match gas and our EVEX instructions. We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions. Also remove the vpextrw.s EVEX alias. That's not something gas implements. llvm-svn: 334922
* [X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves ↵Craig Topper2018-06-181-45/+80
| | | | | | | | | | with reversed operands to InstAliases. The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser. Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported. llvm-svn: 334920
* [ORC] Remove redundant conditionLang Hames2018-06-171-1/+1
| | | | llvm-svn: 334918
* [ORC] Only notify queries that they are resolved/ready when the query stateLang Hames2018-06-171-8/+30
| | | | | | | | changes. This guards against redundant notifications. llvm-svn: 334916
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