summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86][MC] no error diagnostic for out-of-range jrcxz/jecxz/jcxzAlexey Lapshin2019-11-261-6/+21
| | | | | | | | | | | | | | Fix for PR24072: X86 instructions jrcxz/jecxz/jcxz performs short jumps if rcx/ecx/cx register is 0 The maximum relative offset for a forward short jump is 127 Bytes (0x7F). The maximum relative offset for a backward short jump is 128 Bytes (0x80). Gnu assembler warns when the distance of the jump exceeds the maximum but llvm-as does not. Patch by Konstantin Belochapka and Alexey Lapshin Differential Revision: https://reviews.llvm.org/D70652
* [AArch64][SVE] Implement floating-point conversion intrinsicsKerry McLaughlin2019-11-262-41/+64
| | | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - fcvt - fcvtzs & fcvtzu - scvtf & ucvtf - fcvtlt, fcvtnt - fcvtx & fcvtxnt Reviewers: huntergr, sdesmalen, dancgr, mgudim, efriedma Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70180
* [ARM][ReachingDefs] Remove dead code in loloops.Sam Parker2019-11-262-57/+175
| | | | | | | | | | | | Add some more helper functions to ReachingDefs to query the uses of a given MachineInstr and also to query whether two MachineInstrs use the same def of a register. For Arm, while tail-predicating, these helpers are used in the low-overhead loops to remove the dead code that calculates the number of loop iterations. Differential Revision: https://reviews.llvm.org/D70240
* [SystemZ] Don't build a PPA instruction with an immediate 0 operand.Jonas Paulsson2019-11-262-3/+7
| | | | | | | | | | | | The improvement in the machine verifier for operand types (D63973) discovered a bad operand in a test using a PPA instruction. It was an immediate 0 where a register was expected. This patch fixes this (NFC) by now making the PPA second register operand NoRegister instead of a zero immediate in the MIR. Review: Ulrich Weigand https://reviews.llvm.org/D70501
* [ARM][ReachingDefs] RDA in LoLoopsSam Parker2019-11-262-93/+91
| | | | | | | | | | | | | | | | | Add several new methods to ReachingDefAnalysis: - getReachingMIDef, instead of returning an integer, return the MachineInstr that produces the def. - getInstFromId, return a MachineInstr for which the given integer corresponds to. - hasSameReachingDef, return whether two MachineInstr use the same def of a register. - isRegUsedAfter, return whether a register is used after a given MachineInstr. These methods have been used in ARMLowOverhead to replace searching for uses/defs. Differential Revision: https://reviews.llvm.org/D70009
* [InstCombine] Fixed std::min on some bots. NFCIDávid Bolvanský2019-11-261-1/+1
|
* [ARM][ConstantIslands] Correct block size updateSam Parker2019-11-261-10/+10
| | | | | | | | | When inserting a non-decrementing LE, the basic block was being resized to take into consideration that a tCMP and tBcc had been combined into one T1 instruction. This is not true in the LE case where we generate a CBN?Z and an LE. Differential Revision: https://reviews.llvm.org/D70536
* [InstCombine] Optimize some memccpy calls to memcpy/nullDávid Bolvanský2019-11-261-0/+41
| | | | | | | | | | | | | | | | | Summary: return memccpy(d, "helloworld", 'r', 20) => return memcpy(d, "helloworld", 8 /* pos of 'r' in string */), d + 8 Reviewers: efriedma, jdoerfert Reviewed By: jdoerfert Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68089
* [Attributor] Track a GEP Instruction in align deductionHideto Ueno2019-11-261-12/+37
| | | | | | | | | | | | | | | | | | | | Summary: This patch enables us to track GEP instruction in align deduction. If a pointer `B` is defined as `A+Offset` and known to have alignment `C`, there exists some integer Q such that ``` A + Offset = C * Q = B ``` So we can say that the maximum power of two which is a divisor of gcd(Offset, C) is an alignment. Reviewers: jdoerfert, sstefan1 Reviewed By: jdoerfert Subscribers: lebedev.ri, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70392
* [X86] Return Op instead of SDValue() for lowering flags_read/write intrinsicsCraig Topper2019-11-251-1/+1
| | | | | | | | | | Returning SDValue() means we didn't handle it and the common code should try to expand it. But its a target intrinsic so expanding won't do anything and just leave the node alone. But it will print confusing debug messages. By returning Op we tell the common code that the node is legal and shouldn't receive any further processing.
* [BPF] add "llvm." prefix to BPF internally created globalsYonghong Song2019-11-251-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, BPF backend creates some global variables with name like <type_name>:<reloc_type>:<patch_imm>$<access_str> to carry certain information to BPF backend. With direct clang compilation, the following code in llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp is triggered and the above globals are emitted to the ELF file. (clang enabled this as opt flag -faddrsig is on by default.) if (TM.Options.EmitAddrsig) { // Emit address-significance attributes for all globals. OutStreamer->EmitAddrsig(); for (const GlobalValue &GV : M.global_values()) if (!GV.use_empty() && !GV.isThreadLocal() && !GV.hasDLLImportStorageClass() && !GV.getName().startswith("llvm.") && !GV.hasAtLeastLocalUnnamedAddr()) OutStreamer->EmitAddrsigSym(getSymbol(&GV)); } ... 10162: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND tcp_sock:0:2048$0:117 10163: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND tcp_sock:0:2112$0:126:0 10164: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND tcp_sock:1:8$0:31:6 ... While in llc, those globals are not emited since EmitAddrsig default option is false for llc. The llc flag "-addrsig" can be used to enable the above code. This patch added "llvm." prefix to these internal globals so that they can be ignored in the above codes and possible other places. Differential Revision: https://reviews.llvm.org/D70703
* Revert "As a follow-up to my initial mail to llvm-dev here's a first pass at ↵Muhammad Omair Javaid2019-11-262-59/+35
| | | | | | | | | | | | | | | | | | | | | | | the O1 described there." This reverts commit 8ff85ed905a7306977d07a5cd67ab4d5a56fafb4. This commit introduced 9 new failures on lldb buildbot host at http://lab.llvm.org:8014/builders/lldb-aarch64-ubuntu Following tests were failing: lldb-api :: functionalities/tail_call_frames/ambiguous_tail_call_seq1/TestAmbiguousTailCallSeq1.py lldb-api :: functionalities/tail_call_frames/ambiguous_tail_call_seq2/TestAmbiguousTailCallSeq2.py lldb-api :: functionalities/tail_call_frames/disambiguate_call_site/TestDisambiguateCallSite.py lldb-api :: functionalities/tail_call_frames/disambiguate_paths_to_common_sink/TestDisambiguatePathsToCommonSink.py lldb-api :: functionalities/tail_call_frames/disambiguate_tail_call_seq/TestDisambiguateTailCallSeq.py lldb-api :: functionalities/tail_call_frames/inlining_and_tail_calls/TestInliningAndTailCalls.py lldb-api :: functionalities/tail_call_frames/sbapi_support/TestTailCallFrameSBAPI.py lldb-api :: functionalities/tail_call_frames/thread_step_out_message/TestArtificialFrameStepOutMessage.py lldb-api :: functionalities/tail_call_frames/thread_step_out_or_return/TestSteppingOutWithArtificialFrames.py lldb-api :: functionalities/tail_call_frames/unambiguous_sequence/TestUnambiguousTailCalls.py Tags: #llvm Differential Revision: https://reviews.llvm.org/D65410
* [LegalizeTypes] Remove code to create ISD::FP_TO_FP16 from ↵Craig Topper2019-11-251-3/+0
| | | | | | | | | | | | | | | | | | | | | SoftenFloatRes_FTRUNC. There seems to have been a misunderstanding of what ISD::FTRUNC represents. ISD::FTRUNC is equivalent to llvm.trunc which takes a floating point value, truncates it without changing the size of the value and returns it. Despite its similar name, its different than the fptrunc instruction in IR which changes a floating point value to a smaller floating point value. fptrunc is represented by ISD::FP_ROUND in SelectionDAG. Since the ISD::FP_TO_FP16 node takes a floating point value and converts it to f16 its more similar to ISD::FP_ROUND. In fact there is identical code to what is being removed here in SoftenFloatRes_FP_ROUND. I assume this bug was never encountered because it would require f16 to be legalized by softening rather than the default of promoting.
* [X86] Add support for STRICT_FP_ROUND/STRICT_FP_EXTEND from/to fp128 to/from ↵Craig Topper2019-11-251-17/+37
| | | | | | | | | | f32/f64/f80 in 64-bit mode. These need to emit a libcall like we do for the non-strict version. 32-bit mode needs to SoftenFloat support to be implemented for strict FP nodes. Differential Revision: https://reviews.llvm.org/D70504
* As a follow-up to my initial mail to llvm-dev here's a first pass at the O1 ↵Eric Christopher2019-11-252-35/+59
| | | | | | | | | | | | | | | | | | | | | described there. This change doesn't include any change to move from selection dag to fast isel and that will come with other numbers that should help inform that decision. There also haven't been any real debuggability studies with this pipeline yet, this is just the initial start done so that people could see it and we could start tweaking after. Test updates: Outside of the newpm tests most of the updates are coming from either optimization passes not run anymore (and without a compelling argument at the moment) that were largely used for canonicalization in clang. Original post: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131494.html Tags: #llvm Differential Revision: https://reviews.llvm.org/D65410
* [X86] Add proper execution domain information to the avx512vnni instructions.Craig Topper2019-11-251-0/+2
|
* [MemorySSA] Combine verifications.Alina Sbirlea2019-11-251-61/+40
| | | | | | | | | | | | | | | | | | | Summary: Combine three verification methods into one to improve compile time when asserts are enabled. Motivated by PR44066. Sample change of timings on testcase in PR44066 (release+asserts): MSSA off or verification disabled: 1.13s. MSSA on (ToT): 2.48s. With patch: 2.03s. With enabling DefUses after combining Domination+Ordering: 2.6s. After also combining DefUses with Domination+Ordering: 2.06s (candidate to be taken out of EXPENSIVE_CHECKS). Subscribers: Prazek, hiraditya, george.burgess.iv, sanjoy.google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70618
* llvm-symbolizer: fix handling of DW_AT_specification in FRAME.Evgenii Stepanov2019-11-251-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Use getSubroutineName() to the the subrouting name; this function knows how to handle cases when DW_TAG_subprogram refers to an earlier declaration: 0x00000050: DW_TAG_subprogram DW_AT_linkage_name ("_ZN1A1fEv") DW_AT_name ("f") ... 0x00000067: DW_TAG_subprogram DW_AT_low_pc (0x0000000000000000) DW_AT_high_pc (0x0000000000000020) DW_AT_specification (0x00000050 "_ZN1A1fEv") ... 0x0000008c: DW_TAG_variable Reviewers: pcc, vitalybuka, jdoerfert Subscribers: srhines, hiraditya, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70630
* llvm-symbolizer: Support loclist in FRAME.Evgenii Stepanov2019-11-251-4/+56
| | | | | | | | | | | | | | | | Summary: Support location lists in FRAME command. These are used for the majority of local variables in optimized code. Also support DW_OP_breg in addition to DW_OP_fbreg when it refers to the same register as DW_AT_frame_base. Reviewers: pcc, jdoerfert Subscribers: srhines, hiraditya, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70629
* llvm-symbolizer: Fix FRAME handling of missing AT_name.Evgenii Stepanov2019-11-251-2/+13
| | | | | | | | | | | | | | | Summary: llvm-symbolizer protocol is empty string means end-of-output. Do not emit empty string when a function or a variable do not have a name for any reason. Emit "??". Reviewers: pcc, vitalybuka, jdoerfert Subscribers: srhines, hiraditya, rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70626
* [DAGCombiner] avoid crash on out-of-bounds insert index (PR44139)Sanjay Patel2019-11-251-0/+5
| | | | | | | We already have this simplification at node-creation-time, but the test from: https://bugs.llvm.org/show_bug.cgi?id=44139 ...shows that we can combine our way to an assert/crash too.
* Revert "[DDG] Data Dependence Graph - Topological Sort"Bardia Mahjour2019-11-252-32/+5
| | | | | | Revert for now to look into the failures on x86 This reverts commit bec37c3fc766a7b97f8c52c181c325fd47b75259.
* [PowerPC] Rename DarwinDirective to CPUDirective (NFC)Kit Barton2019-11-258-47/+50
| | | | | | | | | | | | | | | | | | | | | Summary: This patch renames the DarwinDirective (used to identify which CPU was defined) to CPUDirective. It also adds the getCPUDirective() method and replaces all uses of getDarwinDirective() with getCPUDirective(). Once this patch lands and downstream users of the getDarwinDirective() method have switched to the getCPUDirective() method, the old getDarwinDirective() method will be removed. Reviewers: nemanjai, hfinkel, power-llvm-team, jsji, echristo, #powerpc, jhibbits Reviewed By: hfinkel, jsji, jhibbits Subscribers: hiraditya, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70352
* [TargetLowering] Merge ExpandChainLibCall with makeLibCallCraig Topper2019-11-253-52/+40
| | | | | | I need to be able to drop an operand for STRICT_FP_ROUND handling on X86. Merging these functions gives me the ArrayRef interface that passes the return type, operands, and debugloc instead of the Node. Differential Revision: https://reviews.llvm.org/D70503
* [InstCombine] remove shuffle mask canonicalization that creates undef elementsSanjay Patel2019-11-251-10/+10
| | | | | | This is NFC-intended because SimplifyDemandedVectorElts() does the same transform later. As discussed in D70641, we may want to change that behavior, so we need to isolate where it happens.
* [ARM] Generate CMSE instructions from CMSE intrinsicsMomchil Velikov2019-11-251-4/+12
| | | | | | | | | | | This patch adds instruction selection patterns for the TT, TTT, TTA, and TTAT instructions and tests for llvm.arm.cmse.tt, llvm.arm.cmse.ttt, llvm.arm.cmse.tta, and llvm.arm.cmse.ttat intrinsics (added in a previous patch). Patch by Javed Absar. Differential Revision: https://reviews.llvm.org/D70407
* [SystemZ] Return the right offsets from getCalleeSavedSpillSlots().Jonas Paulsson2019-11-251-21/+28
| | | | | | | | | | | | | | // Due to the SystemZ ABI, the DWARF CFA (Canonical Frame Address) is not // equal to the incoming stack pointer, but to incoming stack pointer plus // 160. The getOffsetOfLocalArea() returned value is interpreted as "the // offset of the local area from the CFA". The immediate offsets into the Register save area returned by getCalleeSavedSpillSlots() should take this offset into account, which this patch makes sure of. Patch and review by Ulrich Weigand. https://reviews.llvm.org/D70427
* [NFC][LoopFusion] Use isControlFlowEquivalent() from CodeMoverUtils.Whitney Tsang2019-11-252-14/+14
| | | | | | | | Reviewer: kbarton, jdoerfert, Meinersbur, bmahjour, etiotto Reviewed By: Meinersbur Subscribers: hiraditya, llvm-commits Tag: LLVM Differential Revision: https://reviews.llvm.org/D70619
* [PowerPC] Fix VSX clobbers of CSR registersNemanja Ivanovic2019-11-251-0/+11
| | | | | | | | If an inline asm statement clobbers a VSX register that overlaps with a callee-saved Altivec register or FPR, we will not record the clobber and will therefore violate the ABI. This is clearly a bug so this patch fixes it. Differential revision: https://reviews.llvm.org/D68576
* [InstCombine] prevent infinite loop from conflicting shuffle mask transformsSanjay Patel2019-11-251-2/+4
| | | | | | | | | The pattern in question is currently not possible because we aggressively (wrongly) transform mask elements to undef values if they choose from an undef operand. That, however, would change if we tighten our semantics for shuffles as discussed in D70641. Adding this check gives us the flexibility to make that change with minimal overhead for current definitions.
* [DDG] Data Dependence Graph - Topological Sortbmahjour2019-11-252-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | Summary: In this patch the DDG DAG is sorted topologically to put the nodes in the graph in the order that would satisfy all dependencies. This helps transformations that would like to generate code based on the DDG. Since the DDG is a DAG a reverse-post-order traversal would give us the topological ordering. This patch also sorts the basic blocks passed to the builder based on program order to ensure that the dependencies are computed in the correct direction. Authored By: bmahjour Reviewer: Meinersbur, fhahn, myhsu, xtian, dmgreen, kbarton, jdoerfert Reviewed By: Meinersbur Subscribers: ychen, arphaman, simoll, a.elovikov, mgorny, hiraditya, jfb, wuzish, llvm-commits, jsji, Whitney, etiotto, ppc-slack Tags: #llvm Differential Revision: https://reviews.llvm.org/D70609
* [InstCombine] simplify code for shuffle mask canonicalization; NFCSanjay Patel2019-11-251-6/+4
| | | | We never use the local 'Mask' before returning, so that was dead code.
* [InstCombine] remove dead code from shuffle mask canonicalization; NFCSanjay Patel2019-11-251-2/+2
|
* [InstCombine] simplify loop for shuffle mask canonicalization; NFCSanjay Patel2019-11-251-4/+4
|
* [AMDGPU] Fix function name in debug outputJay Foad2019-11-251-3/+3
|
* [AIX][XCOFF] Generate undefined symbol in symbol table for external function ↵jasonliu2019-11-252-9/+47
| | | | | | | | | | | | | | | | call Summary: This patch sets up the infrastructure for 1. Associate MCSymbolXCOFF with an MCSectionXCOFF when it could not get implicitly associated. 2. Generate undefined symbols. The patch itself generates undefined symbol for external function call only. Generate undefined symbol for external global variable and external function descriptors will be handled in separate patch(s) after this is land. Differential Revision: https://reviews.llvm.org/D70443
* [DebugInfo] Avoid register coalesing unsoundly changing DBG_VALUE locationsJeremy Morse2019-11-251-2/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a re-land of D56151 / r364515 with a completely new implementation. Once MIR code leaves SSA form and the liveness of a vreg is considered, DBG_VALUE insts are able to refer to non-live vregs, because their debug-uses do not contribute to liveness. This non-liveness becomes problematic for optimizations like register coalescing, as they can't ``see'' the debug uses in the liveness analyses. As a result registers get coalesced regardless of debug uses, and that can lead to invalid variable locations containing unexpected values. In the added test case, the first vreg operand of ADD32rr is merged with various copies of the vreg (great for performance), but a DBG_VALUE of the unmodified operand is blindly updated to the modified operand. This changes what value the variable will appear to have in a debugger. Fix this by changing any DBG_VALUE whose operand will be resurrected by register coalescing to be a $noreg DBG_VALUE, i.e. give the variable no location. This is an overapproximation as some coalesced locations are safe (others are not) -- an extra domination analysis would be required to work out which, and it would be better if we just don't generate non-live DBG_VALUEs. Differential Revision: https://reviews.llvm.org/D64630
* [ARM][MVE] Select vqnegAnna Welker2019-11-251-11/+19
| | | | | | | | Adds a pattern to ARMInstrMVE.td to use a VQNEG instruction if an equivalent multi-instruction construct is found. Differential Revision: https://reviews.llvm.org/D70491
* [DebugInfo@O2][Utils] Undef instead of delete dbg.values in helper funcOCHyams2019-11-251-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Related bug: https://bugs.llvm.org/show_bug.cgi?id=40648 Static helper function rewriteDebugUsers in Local.cpp deletes dbg.value intrinsics when it cannot move or rewrite them, or salvage the deleted instruction's value. It should instead undef them in this case. This patch fixes that and I've added a test which covers the failing test case in bz40648. I've updated the unit test Local.ReplaceAllDbgUsesWith to check for this behaviour (and fixed a typo in the test which would cause the old test to always pass). Reviewers: aprantl, vsk, djtodoro, probinson Reviewed By: vsk Subscribers: hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D70604
* [AVR] Fix endianness handling in AVR MCserge_sans_paille2019-11-251-5/+3
| | | | Differential Revision: https://reviews.llvm.org/D67926
* [yaml2obj/obj2yaml] - Add support for SHT_LLVM_DEPENDENT_LIBRARIES sections.Georgii Rymar2019-11-252-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | This section contains strings specifying libraries to be added to the link by the linker. The strings are encoded as standard null-terminated UTF-8 strings. This patch adds a way to describe and dump SHT_LLVM_DEPENDENT_LIBRARIES sections. I introduced a new YAMLFlowString type here. That used to teach obj2yaml to dump them like: ``` Libraries: [ foo, bar ] ``` instead of the following (if StringRef would be used): ``` Libraries: - foo - bar ``` Differential revision: https://reviews.llvm.org/D70598
* Revert "[PowerPC] combine rlwinm+rlwinm to rlwinm"czhengsz2019-11-241-100/+0
| | | | This reverts commit 29f6f9b2b2bfecccf903738e2f5a0cd0a70fce31.
* Recommit f0c2a5a "[LV] Generalize conditions for sinking instrs for first ↵Florian Hahn2019-11-242-14/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | order recurrences." This version contains 2 fixes for reported issues: 1. Make sure we do not try to sink terminator instructions. 2. Make sure we bail out, if we try to sink an instruction that needs to stay in place for another recurrence. Original message: If the recurrence PHI node has a single user, we can sink any instruction without side effects, given that all users are dominated by the instruction computing the incoming value of the next iteration ('Previous'). We can sink instructions that may cause traps, because that only causes the trap to occur later, but not on any new paths. With the relaxed check, we also have to make sure that we do not have a direct cycle (meaning PHI user == 'Previous), which indicates a reduction relation, which potentially gets missed by ReductionDescriptor. As follow-ups, we can also sink stores, iff they do not alias with other instructions we move them across and we could also support sinking chains of instructions and multiple users of the PHI. Fixes PR43398. Reviewers: hsaito, dcaballe, Ayal, rengolin Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D69228
* [LoopInterchange] Adjust assertions when updating successors.Florian Hahn2019-11-241-19/+35
| | | | | | | | | | | Currently the assertion in updateSuccessor is overly strict in some cases and overly relaxed in other cases. For branches to the inner and outer loop preheader it is too strict, because they can either be unconditional branches or conditional branches with duplicate targets. Both cases are fine and we can allow updating multiple successors. On the other hand, we have to at least update one successor. This patch adds such an assertion.
* [InstCombine] remove identity shuffle simplification for mask with undefsSanjay Patel2019-11-242-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And simultaneously enhance SimplifyDemandedVectorElts() to rcognize that pattern. That preserves some of the old optimizations in IR. Given a shuffle that includes undef elements in an otherwise identity mask like: define <4 x float> @shuffle(<4 x float> %arg) { %shuf = shufflevector <4 x float> %arg, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3> ret <4 x float> %shuf } We were simplifying that to the input operand. But as discussed in PR43958: https://bugs.llvm.org/show_bug.cgi?id=43958 ...that means that per-vector-element poison that would be stopped by the shuffle can now leak to the result. Also note that we still have (and there are tests for) the same transform with no undef elements in the mask (a fully-defined identity mask). I don't think there's any controversy about that case - it's a valid transform under any interpretation of shufflevector/undef/poison. Looking at a few of the diffs into codegen, I don't see any difference in final asm. So depending on your perspective, that's good (no real loss of optimization power) or bad (poison exists in the DAG, so we only partially fixed the bug). Differential Revision: https://reviews.llvm.org/D70246
* [PowerPC] Spill CR LT bits on P9 using setbAmy Kwan2019-11-241-0/+15
| | | | | | | | | | | | | | | | This patch aims to spill CR[0-7]LT bits on POWER9 using the setb instruction. The sequence on P9 to spill these bits will be: setb %reg, %CRREG stw %reg, $FI Instead of the typical sequence: mfocrf %reg, %CRREG rlwinm %reg1, %reg, $SH, 0, 0 stw %reg1, $FI Differential Revision: https://reviews.llvm.org/D68443
* [ModuloSchedule] Fix a bug in experimental expanderThomas Raoux2019-11-231-14/+62
| | | | | | | | | Fix two problems that popped up after my last patch. One is that the stiching of prologue/epilogue can be wrong when reading a value from a previsou stage. Also changed how we duplicate phi instructions to avoid generating extra phi that we delete later. Differential Revision: https://reviews.llvm.org/D70213
* [pdbutil] Fixed -Wdeprecated-copy in DbiModuleDescriptorDávid Bolvanský2019-11-231-5/+0
|
* Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'Dávid Bolvanský2019-11-232-2/+16
| | | | Fixed hashtable copy ctor.
* Revert 'Fixed -Wdeprecated-copy warnings. NFCI.'Dávid Bolvanský2019-11-232-16/+2
| | | | pdbutil's test is failing.
OpenPOWER on IntegriCloud