summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [ORC][JITLink] Add support for weak references, and improve handling of staticLang Hames2019-11-2813-388/+461
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | libraries. This patch substantially updates ORCv2's lookup API in order to support weak references, and to better support static archives. Key changes: -- Each symbol being looked for is now associated with a SymbolLookupFlags value. If the associated value is SymbolLookupFlags::RequiredSymbol then the symbol must be defined in one of the JITDylibs being searched (or be able to be generated in one of these JITDylibs via an attached definition generator) or the lookup will fail with an error. If the associated value is SymbolLookupFlags::WeaklyReferencedSymbol then the symbol is permitted to be undefined, in which case it will simply not appear in the resulting SymbolMap if the rest of the lookup succeeds. Since lookup now requires these flags for each symbol, the lookup method now takes an instance of a new SymbolLookupSet type rather than a SymbolNameSet. SymbolLookupSet is a vector-backed set of (name, flags) pairs. Clients are responsible for ensuring that the set property (i.e. unique elements) holds, though this is usually simple and SymbolLookupSet provides convenience methods to support this. -- Lookups now have an associated LookupKind value, which is either LookupKind::Static or LookupKind::DLSym. Definition generators can inspect the lookup kind when determining whether or not to generate new definitions. The StaticLibraryDefinitionGenerator is updated to only pull in new objects from the archive if the lookup kind is Static. This allows lookup to be re-used to emulate dlsym for JIT'd symbols without pulling in new objects from archives (which would not happen in a normal dlsym call). -- JITLink is updated to allow externals to be assigned weak linkage, and weak externals now use the SymbolLookupFlags::WeaklyReferencedSymbol value for lookups. Unresolved weak references will be assigned the default value of zero. Since this patch was modifying the lookup API anyway, it alo replaces all of the "MatchNonExported" boolean arguments with a "JITDylibLookupFlags" enum for readability. If a JITDylib's associated value is JITDylibLookupFlags::MatchExportedSymbolsOnly then the lookup will only match against exported (non-hidden) symbols in that JITDylib. If a JITDylib's associated value is JITDylibLookupFlags::MatchAllSymbols then the lookup will match against any symbol defined in the JITDylib.
* [IVDescriptors] Skip FOR where we have multiple sink points for now.Florian Hahn2019-11-281-0/+7
| | | | | This fixes a crash with instructions where multiple operands are first-order-recurrences.
* AMDGPU: Reuse carry out register during FI eliminationAustin Kerbow2019-11-282-6/+14
| | | | | | | | | | | | | | | | | | | Summary: Pre gfx9 we need to scavenge a 64-bit SGPR to use as the carry out for an Add. If only one SGPR was available this crashed when trying to scavenge another 32bit SGPR to materialize the offset. Instead, reuse a 32-bit SGPR from the carry out as the offset register. Also prefer to use vcc for the unused carry out when it is available. Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70614
* [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.Simon Tatham2019-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: In rG643ac6c0420b, the syntax `ldraa x1, [x0]!` was added as an alias for `ldraa x1, [x0, #0]!`. That syntax is less obvious in meaning, and also will not be accepted by assemblers that haven't been updated yet. So it would be better not to emit it as the preferred disassembly for that instruction. This change lowers the EmitPriority of the new alias so that the more explicit syntax `[x0, #0]!` is preferred by the disassembler. The new syntax is still accepted by the assembler. Reviewers: ab, ostannard Reviewed By: ostannard Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70813
* [JITLink] Make sure MachO/x86-64 handles 32-bit signed addends correctly.Lang Hames2019-11-271-4/+4
| | | | These need to be sign extended when loading into Edge addends.
* [InlineCost] Fix infinite loop in indirect call evaluationEhud Katz2019-11-281-85/+85
| | | | | | | | | | | | | | | Currently every time we encounter an indirect call of a known function, we try to evaluate the inline cost of that function. In case of a recursion, that evaluation never stops. The solution I propose is to evaluate only the indirect call of the function, while any further indirect calls (of a known function) will be treated just as direct function calls, which, actually, never tries to evaluate the call. Fixes PR35469. Differential Revision: https://reviews.llvm.org/D69349
* [LegalizeTypes] Remove dead code related to softening f16 which we no longer do.Craig Topper2019-11-272-27/+0
| | | | | | | f16 is promoted to f32 if it is not legal on the target. Found while reviewing what else needed to be done for strict FP in the softening code.
* [LegalTypes][X86] Add SoftenFloatOperand support for ↵Craig Topper2019-11-271-8/+22
| | | | STRICT_FP_TO_SINT/STRICT_FP_TO_UINT.
* [LegalizeTypes][X86] Add ExpandIntegerResult support for ↵Craig Topper2019-11-271-6/+20
| | | | STRICT_FP_TO_SINT/STRICT_FP_TO_UINT.
* [X86] Add support for STRICT_FP_TO_UINT/SINT from fp128.Craig Topper2019-11-271-4/+9
|
* [X86] Add SSEPackedSingle/Double execution domain to COMI/UCOMI SSE/AVX ↵Craig Topper2019-11-272-32/+34
| | | | instructions.
* [AIX] Emit TOC entries for ASM printingDavid Tenty2019-11-275-22/+123
| | | | | | | | | | | | | | | | | | | | Summary: Emit the correct .toc psuedo op when we change to the TOC and emit TC entries. Make sure TOC psuedos get the right symbols via overriding getMCSymbolForTOCPseudoMO on AIX. Add a test for TOC assembly writing and update tests to include TOC entries. Also make sure external globals have a csect set and handle external function descriptor (originally authored by Jason Liu) so we can emit TOC entries for them. Reviewers: DiggerLin, sfertile, Xiangling_L, jasonliu, hubert.reinterpretcast Reviewed By: jasonliu Subscribers: arphaman, wuzish, nemanjai, hiraditya, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70461
* Revert "[Attributor] Move pass after InstCombine to futher eliminate null ↵Dávid Bolvanský2019-11-271-2/+3
| | | | | | pointer checks" This reverts commit 7ca7d62c6ea1680ec0a1861083669596547fdd6f. Commited accidentally.
* [PowerPC] Separate Features that are known to be Power9 specific from Future CPUStefan Pintilie2019-11-271-4/+13
| | | | | | | | The Power 9 CPU has some features that are unlikely to be passed on to future versions of the CPU. This patch separates this out so that future CPU does not inherit them. Differential Revision: https://reviews.llvm.org/D70466
* [Attributor] Move pass after InstCombine to futher eliminate null pointer checksDávid Bolvanský2019-11-271-3/+2
| | | | | | | | | | | | Summary: PR44149 Reviewers: jdoerfert Subscribers: mehdi_amini, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70737
* build: avoid cached literals being linked againstSaleem Abdulrasool2019-11-271-6/+6
| | | | | | If the value of the LibXml2 search is cached, it can cause an errant link against LIBXML2_LIBRARIES-NOTFOUND if libxml2 is not found. Add a guard against this. Should repair the build bots.
* build: avoid hardcoding the libxml2 library nameSaleem Abdulrasool2019-11-271-9/+3
| | | | | | | FindLibXml2 will set the LIBXML2_LIBRARIES variable to the libraries that we must link against. This will be an empty string if libxml2 is not found. Avoid hardcoding the library name as xml2 in the configuration. Simplify the usage in the WindowsManifest library.
* [PowerPC] Add new Future CPU for PowerPC in LLVMStefan Pintilie2019-11-276-4/+26
| | | | | | | | | | This is a continuation of D70262 The previous patch as listed above added the future CPU in clang. This patch adds the future CPU in the PowerPC backend. At this point the patch simply assumes that a future CPU will have the same characteristics as pwr9. Those characteristics may change with later patches. Differential Revision: https://reviews.llvm.org/D70333
* [CriticalAntiDepBreaker] Teach the regmask clobber check to check if any ↵Craig Topper2019-11-271-3/+13
| | | | | | | | | | subregister is preserved before considering the super register clobbered X86 has some calling conventions where bits 127:0 of a vector register are callee saved, but the upper bits aren't. Previously we could detect that the full ymm register was clobbered when the xmm portion was really preserved. This patch checks the subregisters to make sure they aren't preserved. Fixes PR44140 Differential Revision: https://reviews.llvm.org/D70699
* Revert b19ec1eb3d0ctaewookoh2019-11-271-75/+57
| | | | | | Summary: This reverts commit b19ec1eb3d0c as it fails powerpc tests Subscribers: llvm-commits
* [x86] make SLM extract vector element more expensive than defaultSanjay Patel2019-11-271-0/+14
| | | | | | | | | | | | | | | | | | | I'm not sure what the effect of this change will be on all of the affected tests or a larger benchmark, but it fixes the horizontal add/sub problems noted here: https://reviews.llvm.org/D59710?vs=227972&id=228095&whitespace=ignore-most#toc The costs are based on reciprocal throughput numbers in Agner's tables for PEXTR*; these appear to be very slow ops on Silvermont. This is a small step towards the larger motivation discussed in PR43605: https://bugs.llvm.org/show_bug.cgi?id=43605 Also, it seems likely that insert/extract is the source of perf regressions on other CPUs (up to 30%) that were cited as part of the reason to revert D59710, so maybe we'll extend the table-based approach to other subtargets. Differential Revision: https://reviews.llvm.org/D70607
* [LegalizeTypes][FPEnv][X86] Add initial support for softening strict fp nodesCraig Topper2019-11-271-44/+146
| | | | | | This is based on what's required for softening fp128 operations on 32-bit X86 assuming f32/f64/f80 are legal. So there could be some things missing. Differential Revision: https://reviews.llvm.org/D70654
* [BPI] Improve unreachable/ColdCall heurstics to handle loops.Taewook Oh2019-11-271-57/+75
| | | | | | | | | | | | | | | | | Summary: While updatePostDominatedByUnreachable attemps to find basic blocks that are post-domianted by unreachable blocks, it currently cannot handle loops precisely, because it doesn't use the actual post dominator tree analysis but relies on heuristics of visiting basic blocks in post-order. More precisely, when the entire loop is post-dominated by the unreachable block, current algorithm fails to detect the entire loop as post-dominated by the unreachable because when the algorithm reaches to the loop latch it fails to tell all its successors (including the loop header) will "eventually" be post-domianted by the unreachable block, because the algorithm hasn't visited the loop header yet. This makes BPI for the loop latch to assume that loop backedges are taken with 100% of probability. And because of this, block frequency info sometimes marks virtually dead loops (which are post dominated by unreachable blocks) super hot, because 100% backedge-taken probability makes the loop iteration count the max value. updatePostDominatedByColdCall has the exact same problem as well. To address this problem, this patch makes PostDominatedByUnreachable/PostDominatedByColdCall to be computed with the actual post-dominator tree. Reviewers: skatkov, chandlerc, manmanren Reviewed By: skatkov Subscribers: manmanren, vsk, apilipenko, Carrot, qcolombet, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70104
* [ARM][MVE][Intrinsics] Add MVE VAND/VORR/VORN/VEOR/VBIC intrinsics. Add unit ↵Mark Murray2019-11-271-45/+53
| | | | | | | | | | | | | | tests. Summary: Add MVE VAND/VORR/VORN/VEOR/VBIC intrinsics. Add unit tests. Reviewers: simon_tatham, ostannard, dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70547
* [ARM][MVE][Intrinsics] Add MVE VMUL intrinsics. Remove annoying "t1" from ↵Mark Murray2019-11-271-21/+49
| | | | | | | | | | | | | | VMUL* instructions. Add unit tests. Summary: Add MVE VMUL intrinsics. Remove annoying "t1" from VMUL* instructions. Add unit tests. Reviewers: simon_tatham, ostannard, dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70546
* [ARM][MVE][Intrinsics] Add MVE VABD intrinsics. Add unit tests.Mark Murray2019-11-271-9/+53
| | | | | | | | | | | | Summary: Add MVE VABD intrinsics. Add unit tests. Reviewers: simon_tatham, ostannard, dmgreen Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70545
* [Attributor] Handle special case when offset equals zero in nonnull deductionHideto Ueno2019-11-271-6/+18
|
* [ARM] Replace arm_neon_vqadds with sadd_satDavid Green2019-11-273-28/+51
| | | | | | | | | | This replaces the A32 NEON vqadds, vqaddu, vqsubs and vqsubu intrinsics with the target independent sadd_sat, uadd_sat, ssub_sat and usub_sat. This helps generate vqadds from standard IR nodes, which might be produced from the vectoriser. The old variants are removed in the process. Differential Revision: https://reviews.llvm.org/D69350
* AArch64: support the Apple NEON syntax for v8.2 crypto instructions.Tim Northover2019-11-271-11/+15
| | | | Very simple change, just adding the extra syntax variant.
* [MC] Produce proper section relative relocations for COFF in .debug_frameMartin Storsjö2019-11-271-1/+2
| | | | | | | | | | | | | The third parameter to Streamer.EmitSymbolValue() is "bool IsSectionRelative = false". For ELF, these debug sections are mapped to address zero, so a normal, absolute address relocation works just fine, but COFF needs a section relative relocation, and COFF is the only target where needsDwarfSectionOffsetDirective() returns true. This matches how EmitSymbolValue is called elsewhere in the same source file. Differential Revision: https://reviews.llvm.org/D70661
* [X86] [Win64] Avoid truncating large (> 32 bit) stack allocationsMartin Storsjö2019-11-271-1/+1
| | | | | | | This fixes PR44129, which was broken in a7adc3185b (in 7.0.0 and newer). Differential Revision: https://reviews.llvm.org/D70741
* [PowerPC] [NFC] change PPCLoopPreIncPrep class name after D67088.czhengsz2019-11-263-30/+30
| | | | | | | | | | Afer https://reviews.llvm.org/D67088, PPCLoopPreIncPrep pass can prepare more instruction forms except pre inc form, like DS/DQ forms. This patch is a follow-up of https://reviews.llvm.org/D67088 to rename the pass name. Reviewed by: jsji Differential Revision: https://reviews.llvm.org/D70371
* Revert "Revert "As a follow-up to my initial mail to llvm-dev here's a first ↵Eric Christopher2019-11-262-35/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | pass at the O1 described there."" This reapplies: 8ff85ed905a7306977d07a5cd67ab4d5a56fafb4 Original commit message: As a follow-up to my initial mail to llvm-dev here's a first pass at the O1 described there. This change doesn't include any change to move from selection dag to fast isel and that will come with other numbers that should help inform that decision. There also haven't been any real debuggability studies with this pipeline yet, this is just the initial start done so that people could see it and we could start tweaking after. Test updates: Outside of the newpm tests most of the updates are coming from either optimization passes not run anymore (and without a compelling argument at the moment) that were largely used for canonicalization in clang. Original post: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131494.html Tags: #llvm Differential Revision: https://reviews.llvm.org/D65410 This reverts commit c9ddb02659e3ece7a0d9d6b4dac7ceea4ae46e6d.
* [LegalizeTypes] Add SoftenFloatOp_Unary to reduce some duplication for ↵Craig Topper2019-11-262-54/+36
| | | | | | | | | | | | | | | | softening LRINT/LLRINT/LROUND/LLROUND Summary: This will be enhanced in a follow up to add strict fp support Reviewers: efriedma Reviewed By: efriedma Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70751
* [PowerPC] [NFC] rename PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp ↵Jinsong Ji2019-11-272-1/+1
| | | | | | | | | | | | | | | | | | | after D67088 Summary: This is NFC code clean work after D67088. In that patch, we extend loop instructions prep for ds/dq form. This patch only changes the file name PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp for better reviewing of the content change of file PPCLoopInstrFormPrep.cpp. Reviewers: #powerpc, nemanjai, steven.zhang, shchenz Reviewed By: #powerpc, shchenz Subscribers: wuzish, mgorny, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70716
* Initial implementation of -fmacro-prefix-map and -ffile-prefix-mapDan McGregor2019-11-261-9/+32
| | | | | | | | | GCC 8 implements -fmacro-prefix-map. Like -fdebug-prefix-map, it replaces a string prefix for the __FILE__ macro. -ffile-prefix-map is the union of -fdebug-prefix-map and -fmacro-prefix-map Reviewed By: rnk, Lekensteyn, maskray Differential Revision: https://reviews.llvm.org/D49466
* [InstSimplify] fold copysign with same args to the argSanjay Patel2019-11-261-0/+5
| | | | | | | This is correct for any value including NaN/inf. We don't have this fold directly in the backend either, but x86 manages to get it after converting things to bitops.
* [mips] Fix sc, scs, ll, lld instructions expandingSimon Atanasyan2019-11-278-88/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of bugs with the sc, scs, ll, lld instructions expanding: 1. On R6 these instruction pack immediate offset into a 9-bit field. Now if an immediate exceeds 9-bits assembler does not perform expansion and just rejects such instruction. 2. On 64-bit non-PIC code if an operand is a symbol assembler generates incorrect sequence of instructions. It uses R_MIPS_HI16 and R_MIPS_LO16 relocations and skips R_MIPS_HIGHEST and R_MIPS_HIGHER ones. To solve these problems this patch: - Introduces `mem_simm9_exp` to mark 9-bit memory immediate operands which require expansion. Probably later all `mem_simm9` operands will be able to migrate on `mem_simm9_exp` and we rename it to `mem_simm9`. - Adds new `OPERAND_MEM_SIMM9` operand type and assigns it to the `mem_simm9_exp`. That allows to know operand size in the `processInstruction` method and decide whether we need to expand instruction. - Adds `expandMem9Inst` method to expand instructions with 9-bit memory immediate operand. This method just load immediate into a "base" register used by origibal instruction: sc $2, 256($sp) => addiu $1, $sp, 256 sc $2, 0($1) - Fix `expandMem16Inst` to support a correct set of relocations for symbol loading in case of 64-bit non-PIC code. ll $12, symbol => lui $12, 0 R_MIPS_HIGHEST symbol daddiu $12, $12, 0 R_MIPS_HIGHER symbol dsll $12, $12, 16 daddiu $12, $12, 0 R_MIPS_HI16 symbol dsll $12, $12, 16 ll $12, 0($12) R_MIPS_LO16 symbol - Fix `expandMem16Inst` to unify handling of 3 and 4 operands instructions. - Delete unused now `MipsTargetStreamer::emitSCWithSymOffset` method. Task for next patches - implement expanding for other instructions use `mem_simm9` operand and other `mem_simm##` operands. Differential Revision: https://reviews.llvm.org/D70648
* [LegalizeTypes] Add SoftenFloatRes_Unary and SoftenFloatRes_Binary functions ↵Craig Topper2019-11-262-281/+157
| | | | | | | | to factor repeated patterns out of many of the SoftenFloatRes_* functions This has been factored out of D70654 which will add strict FP support to these functions. By making the helpers we avoid repeating even more code. Differential Revision: https://reviews.llvm.org/D70736
* [LegalizeDAG] Use getOperationAction instead of getStrictFPOperationAction ↵Craig Topper2019-11-261-2/+2
| | | | for STRICT_LRINT/LROUND/LLRINT/LLROUND.
* TargetPassConfig: const char * -> const char []Fangrui Song2019-11-261-4/+4
| | | | | The latter has better codegen in non-optimized builds, which do not run ipsccp.
* [X86] Add strict fp support for operations of X87 instructionsCraig Topper2019-11-263-19/+47
| | | | | | | | | | This is the following patch of D68854. This patch adds basic operations of X87 instructions, including +, -, *, / , fp extensions and fp truncations. Patch by Chen Liu(LiuChen3) Differential Revision: https://reviews.llvm.org/D68857
* [ARM] Clean up the load and store code. NFCDavid Green2019-11-261-263/+246
| | | | | | | | | Some of these patterns have grown quite organically. I've tried to organise them a little here, moving all the PatFlags together and giving them a more consistent naming scheme, to allow some of the later patterns to be merged into a single multiclass. Differential Revision: https://reviews.llvm.org/D70178
* [Codegen][ARM] Add addressing modes from masked loads and storesDavid Green2019-11-2613-213/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MVE has a basic symmetry between it's normal loads/store operations and the masked variants. This means that masked loads and stores can use pre-inc and post-inc addressing modes, just like the standard loads and stores already do. To enable that, this patch adds all the relevant infrastructure for treating masked loads/stores addressing modes in the same way as normal loads/stores. This involves: - Adding an AddressingMode to MaskedLoadStoreSDNode, along with an extra Offset operand that is added after the PtrBase. - Extending the IndexedModeActions from 8bits to 16bits to store the legality of masked operations as well as normal ones. This array is fairly small, so doubling the size still won't make it very large. Offset masked loads can then be controlled with setIndexedMaskedLoadAction, similar to standard loads. - The same methods that combine to indexed loads, such as CombineToPostIndexedLoadStore, are adjusted to handle masked loads in the same way. - The ARM backend is then adjusted to make use of these indexed masked loads/stores. - The X86 backend is adjusted to hopefully be no functional changes. Differential Revision: https://reviews.llvm.org/D70176
* [DebugInfo] Disallow fragmenting DIExpressions with shift operatorsstozer2019-11-261-2/+6
| | | | | | | | DIExpressions with shift operators should not be fragmented for the same reason as arithmetic operators: carry over cannot be expressed from one fragment to the other, so an invalid result would be produced. Differential Revision: https://reviews.llvm.org/D70601
* [XCOFF][AIX] Check linkage on the function, and two fixes for commentsjasonliu2019-11-262-8/+12
| | | | | | This is a follow up commit to address post-commit comment in D70443 Differential revision: https://reviews.llvm.org/D70443
* [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register ↵vpykhtin2019-11-261-2/+5
| | | | | | coalescer life easier. Differential revision: https://reviews.llvm.org/D70405
* [LegalizeTypes][RISCV] Soften FCOPYSIGN operandLuís Marques2019-11-262-0/+36
| | | | | | | | | | Summary: Adds support for softening FCOPYSIGN operands. Adds RISC-V tests that exercise the new softening code. Reviewers: asb, lenary, efriedma Reviewed By: efriedma Tags: #llvm Differential Revision: https://reviews.llvm.org/D70679
* [RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32)Luís Marques2019-11-261-0/+3
| | | | | | | | | | | | Summary: Adds tablegen patterns to explicitly handle fcopysign where the magnitude and sign arguments have different types, due to the sign value casts being removed the by DAGCombiner. Support for RV32IF follows in a separate commit. Adds tests for all relevant scenarios except RV32IF. Reviewers: lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D70678
* [yaml2obj] - Teach tool to describe SHT_GNU_verdef section with a "Content" ↵Georgii Rymar2019-11-262-9/+27
| | | | | | | | | property. There is no way to set raw content for SHT_GNU_verdef section. This patch implements it. Differential revision: https://reviews.llvm.org/D70710
OpenPOWER on IntegriCloud