| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
| |
* Convert tabs to spaces
llvm-svn: 21418
|
| |
|
|
| |
llvm-svn: 21417
|
| |
|
|
| |
llvm-svn: 21416
|
| |
|
|
|
|
| |
* Convert tabs to spaces
llvm-svn: 21415
|
| |
|
|
| |
llvm-svn: 21413
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
test1:
movl $N, %eax
movl %eax, G
ret
emit:
test1:
movl $N, G
ret
llvm-svn: 21407
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
printf format strings and other stuff. Instead of generating this:
movl $l1__2E_str_1, %eax
movl %eax, (%esp)
we now emit:
movl $l1__2E_str_1, (%esp)
llvm-svn: 21406
|
| |
|
|
| |
llvm-svn: 21405
|
| |
|
|
|
|
| |
the same block as the setjmp. Thanks to Greg Pettyjohn for noticing this!
llvm-svn: 21403
|
| |
|
|
|
|
|
| |
the newly implemented sys::Process::GetCurrentUserId function. Replace
similarly for getgid.
llvm-svn: 21402
|
| |
|
|
|
|
| |
methods that were recently added to the interface.
llvm-svn: 21401
|
| |
|
|
| |
llvm-svn: 21396
|
| |
|
|
| |
llvm-svn: 21394
|
| |
|
|
| |
llvm-svn: 21393
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
bool %test(int %X) {
%Y = and int %X, 8
%Z = setne int %Y, 0
ret bool %Z
}
we now generate this:
rlwinm r2, r3, 0, 28, 28
srwi r3, r2, 3
instead of this:
rlwinm r2, r3, 0, 28, 28
srwi r2, r2, 3
rlwinm r3, r2, 0, 31, 31
I'll leave it to Nate to get it down to one instruction. :)
---------------------------------------------------------------------
llvm-svn: 21391
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This turns this PPC code:
rlwinm r2, r3, 0, 28, 28
cmpwi cr7, r2, 8
mfcr r2
rlwinm r3, r2, 31, 31, 31
into this:
rlwinm r2, r3, 0, 28, 28
srwi r2, r2, 3
rlwinm r3, r2, 0, 31, 31
Next up, nuking the extra and.
llvm-svn: 21390
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
%shortcirc_val = select bool %tmp.1, bool true, bool %tmp.4 ; <bool> [#uses=1]
%tmp.6 = cast bool %shortcirc_val to int ; <int> [#uses=1]
into this:
%shortcirc_val = or bool %tmp.1, %tmp.4 ; <bool> [#uses=1]
%tmp.6 = cast bool %shortcirc_val to int ; <int> [#uses=1]
not this:
%tmp.4.cast = cast bool %tmp.4 to int ; <int> [#uses=1]
%tmp.6 = select bool %tmp.1, int 1, int %tmp.4.cast ; <int> [#uses=1]
llvm-svn: 21389
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
convert this:
%tmp.1 = seteq int %i, 0 ; <bool> [#uses=1]
br bool %tmp.1, label %shortcirc_done, label %shortcirc_next
shortcirc_next: ; preds = %entry
%tmp.4 = seteq int %j, 0 ; <bool> [#uses=1]
br label %shortcirc_done
shortcirc_done: ; preds = %shortcirc_next, %entry
%shortcirc_val = phi bool [ %tmp.4, %shortcirc_next ], [ true, %entry ] ; <bool> [#uses=1]
to this:
%tmp.1 = seteq int %i, 0 ; <bool> [#uses=1]
%tmp.4 = seteq int %j, 0 ; <bool> [#uses=1]
%shortcirc_val = select bool %tmp.1, bool true, bool %tmp.4 ; <bool> [#uses=1]
... which is later simplified by instcombine into an or.
llvm-svn: 21388
|
| |
|
|
|
|
|
|
| |
Standardize the error messages to be in "path: what failed: why" format.
Also attempt to use the correct errno to ThrowErrno in situations where
the errno value is erased by subsequent system calls.
llvm-svn: 21385
|
| |
|
|
|
|
|
| |
Allow the ThrowErrno function to optionally accept an error number
parameter so that callers can specify the error number to be used.
llvm-svn: 21384
|
| |
|
|
| |
llvm-svn: 21379
|
| |
|
|
|
|
| |
result in returning executable files that won't be runnable.
llvm-svn: 21378
|
| |
|
|
|
|
| |
Patch by Markus Oberhumer.
llvm-svn: 21377
|
| |
|
|
|
|
| |
Thanks to Markus Oberhumer for the patch!
llvm-svn: 21370
|
| |
|
|
|
|
| |
Patch by Markus Oberhumer. Thanks!
llvm-svn: 21369
|
| |
|
|
| |
llvm-svn: 21368
|
| |
|
|
|
|
|
|
| |
Make IPSCCP strip off dead constant exprs that are using functions, making
them appear as though their address is taken. This allows us to propagate
some more pool descriptors, lowering the overhead of pool alloc.
llvm-svn: 21363
|
| |
|
|
| |
llvm-svn: 21360
|
| |
|
|
| |
llvm-svn: 21354
|
| |
|
|
| |
llvm-svn: 21353
|
| |
|
|
| |
llvm-svn: 21352
|
| |
|
|
| |
llvm-svn: 21351
|
| |
|
|
|
|
| |
them away.
llvm-svn: 21350
|
| |
|
|
| |
llvm-svn: 21349
|
| |
|
|
| |
llvm-svn: 21348
|
| |
|
|
| |
llvm-svn: 21347
|
| |
|
|
| |
llvm-svn: 21346
|
| |
|
|
|
|
|
| |
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
llvm-svn: 21345
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
llvm-svn: 21321
|
| |
|
|
| |
llvm-svn: 21320
|
| |
|
|
| |
llvm-svn: 21319
|
| |
|
|
| |
llvm-svn: 21318
|
| |
|
|
| |
llvm-svn: 21317
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
// (X != 0) | (Y != 0) -> (X|Y != 0)
// (X == 0) & (Y == 0) -> (X|Y == 0)
Compiling this:
int %bar(int %a, int %b) {
entry:
%tmp.1 = setne int %a, 0
%tmp.2 = setne int %b, 0
%tmp.3 = or bool %tmp.1, %tmp.2
%retval = cast bool %tmp.3 to int
ret int %retval
}
to this:
_bar:
or r2, r3, r4
addic r3, r2, -1
subfe r3, r3, r2
blr
instead of:
_bar:
addic r2, r3, -1
subfe r2, r2, r3
addic r3, r4, -1
subfe r3, r3, r4
or r3, r2, r3
blr
llvm-svn: 21316
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
eliminating an and for Nate's testcase:
int %bar(int %a, int %b) {
entry:
%tmp.1 = setne int %a, 0
%tmp.2 = setne int %b, 0
%tmp.3 = or bool %tmp.1, %tmp.2
%retval = cast bool %tmp.3 to int
ret int %retval
}
generating:
_bar:
addic r2, r3, -1
subfe r2, r2, r3
addic r3, r4, -1
subfe r3, r3, r4
or r3, r2, r3
blr
instead of:
_bar:
addic r2, r3, -1
subfe r2, r2, r3
addic r3, r4, -1
subfe r3, r3, r4
or r2, r2, r3
rlwinm r3, r2, 0, 31, 31
blr
llvm-svn: 21315
|
| |
|
|
|
|
|
|
| |
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
llvm-svn: 21314
|
| |
|
|
| |
llvm-svn: 21313
|
| |
|
|
| |
llvm-svn: 21312
|
| |
|
|
|
|
|
|
|
|
| |
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
llvm-svn: 21309
|
| |
|
|
|
|
|
|
|
| |
This pass forward branches through conditions when it can show that the
conditions is either always true or false for a predecessor. This currently
only handles the most simple cases of this, but is successful at threading
across 2489 branches and 65 switch instructions in 176.gcc, which isn't bad.
llvm-svn: 21306
|