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* DebugInfo: Drop rest of DIDescriptor subclassesDuncan P. N. Exon Smith2015-04-2122-110/+107
| | | | | | | Delete the remaining subclasses of (the already deleted) `DIDescriptor`. Part of PR23080. llvm-svn: 235404
* DebugInfo: Assert dbg.declare/value insts are validDuncan P. N. Exon Smith2015-04-214-15/+11
| | | | | | | | | | Remove early returns for when `getVariable()` is null, and just assert that it never happens. The Verifier already confirms that there's a valid variable on these intrinsics, so we should assume the debug info isn't broken. I also updated a check for a `!dbg` attachment, which the Verifier similarly guarantees. llvm-svn: 235400
* Re-land r235154-r235156 under the existing -sehprepare flagReid Kleckner2015-04-214-8/+117
| | | | | | | | Keep the old SEH fan-in lowering on by default for now, since projects rely on it. This will make it easy to test this change with a simple flag flip. llvm-svn: 235399
* X86: Match for X86ISD nodes in LowerBUILD_VECTOR instead of BUILD_VECTORCombineMatthias Braun2015-04-211-24/+23
| | | | | | | | | There doesn't seem to be a reason to perform this target ISD node matching in an DAGCombine, moving it to lowering fixes PR23296. Differential Revision: http://reviews.llvm.org/D9137 llvm-svn: 235394
* AVX-512: Added VPMOVx2M instructions for SKX,Elena Demikhovsky2015-04-211-1/+30
| | | | | | fixed encoding of VPMOVM2x. llvm-svn: 235385
* AVX-512: Added VPTESTM and VPTESTNM instructions for SKXElena Demikhovsky2015-04-212-30/+127
| | | | llvm-svn: 235383
* [mips] [IAS] Implement the .asciiz directive.Toma Tabacu2015-04-212-0/+6
| | | | | | | | | | | | | | | | Summary: This directive is exactly the same as .asciz, except it's only used by MIPS. It is used to store null terminated strings in object files. Reviewers: rafael, dsanders, echristo Reviewed By: dsanders, echristo Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D7530 llvm-svn: 235382
* [mips][microMIPSr6] Implement CACHE and PREF instructionsJozef Kolek2015-04-213-3/+32
| | | | | | | | Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
* [mips] Cleanup old floating-point flag conditions definitions. NFC.Vasileios Kalintiris2015-04-211-22/+0
| | | | | | | | Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7947 llvm-svn: 235377
* [mips] Optimize code generation for 64-bit variable shift instructions.Vasileios Kalintiris2015-04-211-0/+10
| | | | | | | | | | | | | | | | Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
* AVX-512: Added logical and arithmetic instructions for SKXElena Demikhovsky2015-04-213-82/+178
| | | | | | by Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 235375
* [X86][SSE] Provide execution domains for scalar floating point operationsSimon Pilgrim2015-04-211-38/+41
| | | | | | | | | | This is an updated version of Chandler's patch D7402 that got accepted but never committed, and has bit-rotted a bit since. I've updated the execution domain declarations to match the approach of the packed templates and also added some extra scalar unary tests. Differential Revision: http://reviews.llvm.org/D9095 llvm-svn: 235372
* CONCAT_VECTOR of BUILD_VECTOR - minor fixSimon Pilgrim2015-04-211-0/+12
| | | | | | | | Fixed issue with the combine of CONCAT_VECTOR of 2 BUILD_VECTOR nodes - the optimisation wasn't ensuring that the scalar operands of both nodes were the same type/size for implicit truncation. Test case spotted by Patrik Hagglund llvm-svn: 235371
* Fix generic shift expansion when shift amount is 0Pawel Bylica2015-04-211-7/+9
| | | | | | | | | | | | | | | | | | | | | Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=16439. This is one possible way to approach this. The other would be to split InL>>(nbits-Amt) into (InL>>(nbits-1-Amt))>>1, which is also valid since since we only need to care about Amt up nbits-1. It's hard to tell which one is better since the shift might be expensive if this stage of expansion is not yet a legal machine integer, whereas comparisons with zero are relatively cheap at all sizes, but more expensive than a shift if the shift is on a legal machine type. Patch by Keno Fischer! Test Plan: regression test from http://reviews.llvm.org/D7752 Reviewers: chfast, resistor Reviewed By: chfast, resistor Subscribers: sanjoy, resistor, chfast, llvm-commits Differential Revision: http://reviews.llvm.org/D4978 llvm-svn: 235370
* X86: Do not select X86 custom vector nodes if operand types don't matchMatthias Braun2015-04-211-4/+16
| | | | | | | | | | | | | X86ISD::ADDSUB, X86ISD::(F)HADD, X86ISD::(F)HSUB should not be selected if the operand types do not match the result type because vector type legalization cannot deal with this for custom nodes. Testcase X86ISD::ADDSUB is attached. I could not create a testcase for the FHADD/FHSUB cases because of: https://llvm.org/bugs/show_bug.cgi?id=23296 Differential Revision: http://reviews.llvm.org/D9120 llvm-svn: 235367
* [MC] When using bundle aligment, align sections to bundle sizeDerek Schuff2015-04-211-0/+15
| | | | | | | | | | | | | | | Summary: Bundle aligment requires that the functions always start at an aligned address. Usually this is ensured by the compiler, but assembly code does not always begin with a .align directive. This change ensures that sections get the correct alignment if they contain any instructions and bundling is enabled. (It also makes LLVM match the behavior of GNU as). Differential Revision: http://reviews.llvm.org/D9131 llvm-svn: 235365
* InstCombine: fold (sitofp (zext x)) to (uitofp x)Fiona Glaser2015-04-211-1/+4
| | | | | | | This is okay because the zext guarantees the high bit is zero, and so the value is unsigned. llvm-svn: 235364
* [WinEH] Fix problem with landing pad return values used in PHI nodes during ↵Andrew Kaylor2015-04-201-0/+4
| | | | | | outlining. llvm-svn: 235358
* DebugInfo: Delete subclasses of DIScopeDuncan P. N. Exon Smith2015-04-2016-68/+70
| | | | | | | Delete subclasses of (the already defunct) `DIScope`, updating users to use the raw pointers from the `Metadata` hierarchy directly. llvm-svn: 235356
* [WinEH] Fix problem with mapping shared empty handler blocks.Andrew Kaylor2015-04-201-2/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D9125 llvm-svn: 235354
* DebugInfo: Delete old subclasses of DITypeDuncan P. N. Exon Smith2015-04-204-32/+29
| | | | | | | | | | | Delete subclasses of (the already deleted) `DIType` in favour of directly using pointers from the `Metadata` hierarchy. While `DICompositeType` wraps `MDCompositeTypeBase` and `DIDerivedType` wraps `MDDerivedTypeBase`, most uses of each really meant the more specific `MDCompositeType` and `MDDerivedType`. llvm-svn: 235351
* DwarfUnit: Split MDSubroutineType version of constructTypeDIE()Duncan P. N. Exon Smith2015-04-203-32/+36
| | | | | | | | | | | | | The version of `constructTypeDIE()` for `MDSubroutineType` is unrelated to (and has different callers than) the `MDCompositeType`. Split the two in half. This simplifies an upcoming patch to delete `DICompositeType`. There shouldn't be any real functionality change here. `createTypeDIE()` is `cast<>`'ing where it didn't need to before, but that function in turn is only called for true `MDCompositeType`s. llvm-svn: 235349
* [Orc] Make the makeStub function propagate argument attributes onto the call toLang Hames2015-04-201-0/+1
| | | | | | | | | | | the function body. This is necessary for correctness when lazily compiling. Also, flesh out the Orc unit test infrastructure slightly, and add a unit test for this. llvm-svn: 235347
* DwarfUnit: Cleanup commentsDuncan P. N. Exon Smith2015-04-202-194/+87
| | | | | | | | | | | | | | Update comment style in `DwarfUnit`. - Drop duplicated comments at definition, and update the comments at the declaration where the definition comments looked newer or more complete. - Drop the `functionName -` prefix. - Add `\brief` in a few places. - Remove a few comments entirely that weren't adding value (just turned the function name and arguments into a sentence). llvm-svn: 235345
* Refactoring and enhancement to FMA combine.Olivier Sallenave2015-04-201-171/+369
| | | | llvm-svn: 235344
* [MIPS] OperationAction for FP_TO_FP16, FP16_TO_FPPirama Arumuga Nainar2015-04-201-2/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: Set operation action for FP16 conversion opcodes, so the Op legalizer can choose the gnu_* libcalls for Mips. Set LoadExtAction and TruncStoreAction for f16 scalars and vectors to prevent (fpext (load )) and (store (fptrunc)) from getting combined into unsupported operations. Added test cases to test that these operations are handled correctly for f16 scalars and vectors. This patch depends on http://reviews.llvm.org/D8755. Reviewers: srhines Subscribers: llvm-commits, ab Differential Revision: http://reviews.llvm.org/D8804 llvm-svn: 235341
* DAGCombine: Remove redundant NaN checks around ISD::FSQRTTom Stellard2015-04-201-0/+35
| | | | | | | | This folds: (select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x) llvm-svn: 235333
* IR: Add ConstantFP::getNaN()Tom Stellard2015-04-201-0/+11
| | | | | | This is a wrapper around APFloat::getNaN(). llvm-svn: 235332
* DebugInfo: Remove DITypeDuncan P. N. Exon Smith2015-04-204-27/+27
| | | | | | | | This is the last major parent class, so I'll probably start deleting classes in batches now. Looks like many of the references to the DI* hierarchy were updated organically along the way. llvm-svn: 235331
* [WinEH] Fix memory leak with catch-all mapping.Andrew Kaylor2015-04-201-5/+12
| | | | llvm-svn: 235328
* DebugInfo: Remove DIScopeDuncan P. N. Exon Smith2015-04-204-28/+29
| | | | | | | | | Replace uses of `DIScope` with `MDScope*`. There was one spot where I've left an `MDScope*` uninitialized (where `DIScope` would have been default-initialized to `nullptr`) -- this is intentional, since the if/else that follows should unconditional assign it to a value. llvm-svn: 235327
* [Orc] Use the 64-bit versions of FXSAVE/FXRSTOR for JIT reentry.Lang Hames2015-04-201-16/+16
| | | | llvm-svn: 235325
* DebugInfo: Remove typedefs for DITypeRef, etc.Duncan P. N. Exon Smith2015-04-203-11/+11
| | | | | | | | | | Remove typedefs for type refs: - DITypeRef => MDTypeRef - DIScopeRef => MDScopeRef - DIDescriptorRef => DebugNodeRef llvm-svn: 235323
* [mips][microMIPSr6] Implement BITSWAP instructionJozef Kolek2015-04-203-2/+30
| | | | | | | | Implement BITSWAP instruction using mapping. Differential Revision: http://reviews.llvm.org/D8857 llvm-svn: 235321
* [AArch64] LORID_EL1 register must be treated as read-onlyVladimir Sukharev2015-04-201-3/+5
| | | | | | | | | | | | Patch by: John Brawn Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9105 llvm-svn: 235314
* [InlineFunction] Don't add lifetime markers for zero-sized allocas.Akira Hatanaka2015-04-201-1/+5
| | | | | | | | | This commit fixes the code which adds lifetime markers in InlineFunction to skip zero-sized allocas instead of asserting on them. rdar://problem/20531155 llvm-svn: 235312
* Recognize n/1 in the SCEV divide functionBrendon Cahoon2015-04-201-0/+7
| | | | | | | | | | | | n/1 generates a quotient equal to n and a remainder of 0. If this case is not recognized, then the SCEV divide() function can return a remainder that is greater than or equal to the denominator, which means the delinearized subscripts for the test case will be incorrect. Differential Revision: http://reviews.llvm.org/D9003 llvm-svn: 235311
* [PowerPC] Flow oversized lines for r235309Bill Schmidt2015-04-201-11/+25
| | | | llvm-svn: 235310
* [PowerPC] Add future work for vector insert/extract to README_ALTIVEC.txtBill Schmidt2015-04-201-0/+14
| | | | llvm-svn: 235309
* [mips][microMIPSr6] Implement disassembler supportJozef Kolek2015-04-202-4/+13
| | | | | | | | Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
* Don't allow pwrite to resize a stream.Rafael Espindola2015-04-201-9/+6
| | | | | | | | | | | | | | | | | | | | | The current implementations could exhibit some behavior differences: raw_fd_ostream: Whatever the underlying fd does with seek+write. In a normal file, the write position would be back to the old offset. raw_svector_ostream: The write position is always the end of the stream, so after pwrite the write position would be the new end. This matches what OS_X (all BSD?) do with a pwrite in a O_APPEND fd. Given that we don't need that feature and don't use O_APPEND a lot in LLVM, just disallow it. I am open to suggestions on renaming pwrite to something else, but this fixes the issue for now. Thanks to Yaron Keren for reporting it. llvm-svn: 235303
* [mips][microMIPSr6] Implement BALC and BC instructionsJozef Kolek2015-04-203-3/+58
| | | | | | | | This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 llvm-svn: 235302
* Look past locals in comdats.Rafael Espindola2015-04-201-9/+8
| | | | | | | | | | | We have to avoid converting a reference to a global into a reference to a local, but it is fine to look past a local. Patch by Vasileios Kalintiris. I just moved the comment and added thet test. llvm-svn: 235300
* [mips][microMIPSr6] Implement initial mapping supportJozef Kolek2015-04-203-2/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D8387 llvm-svn: 235298
* [mips][microMIPSr6] Implement initial subtarget supportJozef Kolek2015-04-204-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D8386 llvm-svn: 235296
* [X86][FastIsel] Fix assertion failure when selecting int-to-double ↵Andrea Di Biagio2015-04-201-5/+6
| | | | | | | | | | | | | | | | | | | | | | conversion (PR23273). This fixes a regression introduced at revision 231243. The target-independent selection algorithm in FastISel knows how to select a SINT_TO_FP if the target is SSE but not AVX. That is because on X86, the tablegen'd 'fastEmit' functions know how to select CVTSI2SSrr and CVTSI2SDrr. Method X86FastISel::X86SelectSIToFP was therefore working under the wrong assumption that the target was AVX. That assumption was incorrect since we can have a target that is neither AVX nor SSE. So, rather than asserting for the presence of AVX, we should have had an early exit from 'X86SelectSIToFP' if the target was not AVX. This patch fixes the issue replacing the invalid assertion with an early exit. Thanks to Dimitry Andric for reporting this problem and for providing a small reproducible testcase. Added test pr23273.ll. llvm-svn: 235295
* [NFC] Refactor identification of reductions as common utility function.Karthik Bhat2015-04-203-519/+484
| | | | | | | | | This patch refactors reduction identification code out of LoopVectorizer and exposes them as common utilities. No functional change. Review: http://reviews.llvm.org/D9046 llvm-svn: 235284
* [InlineAsm] Remove EarlyClobber on registers that are also inputsHal Finkel2015-04-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an inline asm call has an output register marked as early-clobber, but that same register is also an input operand, what should we do? GCC accepts this, and is documented to accept this for read/write operands saying, "Furthermore, if the earlyclobber operand is also a read/write operand, then that operand is written only after it's used." For write-only operands, the situation seems less clear, but I have at least one existing codebase that assumes this will work, in part because it has syscall macros like this: ({ \ register uint64_t r0 __asm__ ("r0") = (__NR_ ## name); \ register uint64_t r3 __asm__ ("r3") = ((uint64_t) (arg0)); \ register uint64_t r4 __asm__ ("r4") = ((uint64_t) (arg1)); \ register uint64_t r5 __asm__ ("r5") = ((uint64_t) (arg2)); \ __asm__ __volatile__ \ ("sc" \ : "=&r"(r0),"=&r"(r3),"=&r"(r4),"=&r"(r5) \ : "0"(r0), "1"(r3), "2"(r4), "3"(r5) \ : "r6","r7","r8","r9","r10","r11","r12","cr0","memory"); \ r3; \ }) Furthermore, with register aliases and subregister relationships that only the backend knows about, rejecting this in the frontend seems like a difficult proposition (if we wanted to do so). However, keeping the early-clobber flag on the INLINEASM MI does not work for us, because it will cause the register's live interval to end to soon (so it will not appear defined to be used as an input). Fortunately, fixing this does not seem hard: When forming the INLINEASM MI, check to see if any of the early-clobber outputs are also inputs, and if so, remove the early-clobber flag. llvm-svn: 235283
* [X86][SSE] Fix for getScalarValueForVectorElement to detect scalar sources ↵Simon Pilgrim2015-04-191-2/+7
| | | | | | | | | | requiring truncation. The fix ensures that scalar sources inserted into a vector are the correct bit size. Integer scalar sources from BUILD_VECTOR and SCALAR_TO_VECTOR nodes may require truncation that this function doesn't currently support. llvm-svn: 235281
* Remove CFIFuncName from TargetOptions as it is currently unused.Eric Christopher2015-04-191-6/+0
| | | | llvm-svn: 235268
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