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* [PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's ↵Fedor Sergeev2017-12-141-2/+3
| | | | | | | | | | | | | | | | | | version of InstCombine Summary: Passing AliasAnalysis results instead of nullptr appears to work just fine. A couple new-pass-manager tests updated to align with new order of analyses. Reviewers: chandlerc, spatel, craig.topper Reviewed By: chandlerc Subscribers: mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D41203 llvm-svn: 320687
* [LV] Support efficient vectorization of an induction with redundant castsDorit Nuzman2017-12-142-14/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | D30041 extended SCEVPredicateRewriter to improve handling of Phi nodes whose update chain involves casts; PSCEV can now build an AddRecurrence for some forms of such phi nodes, under the proper runtime overflow test. This means that we can identify such phi nodes as an induction, and the loop-vectorizer can now vectorize such inductions, however inefficiently. The vectorizer doesn't know that it can ignore the casts, and so it vectorizes them. This patch records the casts in the InductionDescriptor, so that they could be marked to be ignored for cost calculation (we use VecValuesToIgnore for that) and ignored for vectorization/widening/scalarization (i.e. treated as TriviallyDead). In addition to marking all these casts to be ignored, we also need to make sure that each cast is mapped to the right vector value in the vector loop body (be it a widened, vectorized, or scalarized induction). So whenever an induction phi is mapped to a vector value (during vectorization/widening/ scalarization), we also map the respective cast instruction (if exists) to that vector value. (If the phi-update sequence of an induction involves more than one cast, then the above mapping to vector value is relevant only for the last cast of the sequence as we allow only the "last cast" to be used outside the induction update chain itself). This is the last step in addressing PR30654. llvm-svn: 320672
* [EarlyCSE] recognize swapped variants of abs/nabs as equivalentSanjay Patel2017-12-131-9/+12
| | | | | | | | Extends https://reviews.llvm.org/rL320640 Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320653
* Reverting [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-134-311/+89
| | | | | | | Stage 2 bootstrap failed: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434 llvm-svn: 320641
* [EarlyCSE] recognize commuted and swapped variants of min/max as equivalent ↵Sanjay Patel2017-12-131-0/+27
| | | | | | | | | | | | | (PR35642) As shown in: https://bugs.llvm.org/show_bug.cgi?id=35642 ...we can have different forms of min/max, so we should recognize those here in EarlyCSE similar to how we already handle binops and compares that can commute. Differential Revision: https://reviews.llvm.org/D41136 llvm-svn: 320640
* Remove redundant includes from lib/Transforms.Michael Zolotukhin2017-12-1331-48/+0
| | | | llvm-svn: 320628
* [JumpThreading] Preservation of DT and LVI across the passBrian M. Rzycki2017-12-134-89/+311
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: See D37528 for a previous (non-deferred) version of this patch and its description. Preserves dominance in a deferred manner using a new class DeferredDominance. This reduces the performance impact of updating the DominatorTree at every edge insertion and deletion. A user may call DDT->flush() within JumpThreading for an up-to-date DT. This patch currently has one flush() at the end of runImpl() to ensure DT is preserved across the pass. LVI is also preserved to help subsequent passes such as CorrelatedValuePropagation. LVI is simpler to maintain and is done immediately (not deferred). The code to perfom the preversation was minimally altered and was simply marked as preserved for the PassManager to be informed. This extends the analysis available to JumpThreading for future enhancements. One example is loop boundary threading. Reviewers: dberlin, kuhar, sebpop Reviewed By: kuhar, sebpop Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40146 llvm-svn: 320612
* [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases loadAditya Kumar2017-12-131-2/+2
| | | | | | | | | | | | | | w.r.t. the paper "A Practical Improvement to the Partial Redundancy Elimination in SSA Form" (https://sites.google.com/site/jongsoopark/home/ssapre.pdf) Proper dominance check was missing here, so having a loopinfo should not be required. Committing this diff as this fixes the bug, if there are further concerns, I'll be happy to work on them. Differential Revision: https://reviews.llvm.org/D39781 llvm-svn: 320607
* Reintroduce r320049, r320014 and r319894.Igor Laevsky2017-12-131-0/+4
| | | | | | OpenGL issues should be fixed by now. llvm-svn: 320568
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-12-131-83/+195
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: mgrang, dcaballe, hans, mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 llvm-svn: 320548
* [CallSiteSplitting] Refactor creating callsites.Florian Hahn2017-12-131-115/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change makes the call site creation more general if any of the arguments is predicated on a condition in the call site's predecessors. If we find a callsite, that potentially can be split, we collect the set of conditions for the call site's predecessors (currently only 2 predecessors are allowed). To do that, we traverse each predecessor's predecessors as long as it only has single predecessors and record the condition, if it is relevant to the call site. For each condition, we also check if the condition is taken or not. In case it is not taken, we record the inverse predicate. We use the recorded conditions to create the new call sites and split the basic block. This has 2 benefits: (1) it is slightly easier to see what is going on (IMO) and (2) we can easily extend it to handle more complex control flow. Reviewers: davidxl, junbuml Reviewed By: junbuml Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40728 llvm-svn: 320547
* [hwasan] Inline instrumentation & fixed shadow.Evgeniy Stepanov2017-12-131-3/+48
| | | | | | | | | | | | Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x. Reviewers: kcc, alekseyshl Subscribers: kubamracek, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41137 llvm-svn: 320538
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-4/+20
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320525
* Reassociate: add global reassociation algorithmFiona Glaser2017-12-121-2/+110
| | | | | | | | | | | | | | | | | | | | | | | This algorithm (explained more in the source code) takes into account global redundancies by building a "pair map" to find common subexprs. The primary motivation of this is to handle situations like foo = (a * b) * c bar = (a * d) * c where we currently don't identify that "a * c" is redundant. Accordingly, it prioritizes the emission of a * c so that CSE can remove the redundant calculation later. Does not change the actual reassociation algorithm -- only the order in which the reassociated operand chain is reconstructed. Gives ~1.5% floating point math instruction count reduction on a large offline suite of graphics shaders. llvm-svn: 320515
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-121-29/+11
| | | | | | | | bitcast." This reverts commit r320510 - again sanitizers bbots. llvm-svn: 320513
* Split IndirectBr critical edges before PGO gen/use passes.Hiroshi Yamauchi2017-12-122-6/+34
| | | | | | | | | | | | | | | | | | | | | | Summary: The PGO gen/use passes currently fail with an assert failure if there's a critical edge whose source is an IndirectBr instruction and that edge needs to be instrumented. To avoid this in certain cases, split IndirectBr critical edges in the PGO gen/use passes. This works for blocks with single indirectbr predecessors, but not for those with multiple indirectbr predecessors (splitting an IndirectBr critical edge isn't always possible.) Reviewers: davidxl, xur Reviewed By: davidxl Subscribers: efriedma, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D40699 llvm-svn: 320511
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-11/+29
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320510
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-121-21/+4
| | | | | | | | | bitcast." This reverts commit r320499 again to resolve the problem with the sanitizers bbots. llvm-svn: 320501
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-4/+21
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320499
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-121-29/+11
| | | | | | | | | bitcast." This reverts commit r320496 to solve the problems with sanitizer buildbots. llvm-svn: 320498
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-11/+29
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320496
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-121-20/+4
| | | | | | | | bitcast." This reverts commit r320488 because of the failed asan buildbots.. llvm-svn: 320490
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-4/+20
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320488
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-121-17/+2
| | | | | | | | bitcast." This reverts commit r320483 because of the failed Windows buildbots. llvm-svn: 320485
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-121-2/+17
| | | | | | | | | | | | | | | | If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320483
* [InstComineLoadStoreAlloca] Optimize stores to GEP off null baseAnna Thomas2017-12-121-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently, in InstCombineLoadStoreAlloca, we have simplification rules for the following cases: 1. load off a null 2. load off a GEP with null base 3. store to a null This patch adds support for the fourth case which is store into a GEP with null base. Since this is UB as well (and directly analogous to the load off a GEP with null base), we can substitute the stored val with undef in instcombine, so that SimplifyCFG can optimize this code into unreachable code. Note: Right now, simplifyCFG hasn't been taught about optimizing this to unreachable and adding an llvm.trap (this is already done for the above 3 cases). Reviewers: majnemer, hfinkel, sanjoy, davide Reviewed by: sanjoy, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41026 llvm-svn: 320480
* Revert r320464 as it breaks gold plugin testsEugene Leviant2017-12-121-0/+14
| | | | llvm-svn: 320467
* Revert r320049, r320014 and r319894Igor Laevsky2017-12-121-4/+0
| | | | | | | They were causing failures of the piglit OpenGL tests with AMD GPUs using the Mesa radeonsi driver. llvm-svn: 320466
* [ThinLTO] Remove unused code from thinLTOInternalizeModuleEugene Leviant2017-12-121-14/+0
| | | | | | Differential revision: https://reviews.llvm.org/D40970 llvm-svn: 320464
* [LV] Ignore the cost of values that will not appear in the vectorized loopDorit Nuzman2017-12-121-1/+2
| | | | | | | | | VecValuesToIgnore holds values that will not appear in the vectorized loop. We should therefore ignore their cost when VF > 1. Differential Revision: https://reviews.llvm.org/D40883 llvm-svn: 320463
* [CallSiteSplitting] Don't let debug intrinsics affect optimizationsMikael Holmen2017-12-121-4/+5
| | | | | | | | | | | | | | | | | Summary: This solves PR35616. We don't want the compiler to generate different code when we compile with/without -g, so we now ignore debug intrinsics when determining if the optimization can trigger or not. Reviewers: junbuml Subscribers: davide, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41068 llvm-svn: 320460
* LSR: Check more intrinsic pointer operandsMatt Arsenault2017-12-111-22/+45
| | | | llvm-svn: 320424
* Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single ↵Hans Wennborg2017-12-111-17/+2
| | | | | | | | | | | | | | | | | | | | | minmax load bitcast." The tests fail (opt asserts) on Windows. > Summary: > If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, > &V2)))), bitcast)`, but the load is used in other instructions, it leads > to looping in InstCombiner. Patch adds additional check that all users > of the load instructions are stores and then replaces all uses of load > instruction by the new one with new type. > > Reviewers: RKSimon, spatel, majnemer > > Subscribers: llvm-commits > > Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320421
* ASAN: Provide reliable debug info for local variables at -O0.Adrian Prantl2017-12-111-2/+12
| | | | | | | | | | | | | | | | | | | | | | The function stack poisioner conditionally stores local variables either in an alloca or in malloc'ated memory, which has the unfortunate side-effect, that the actual address of the variable is only materialized when the variable is accessed, which means that those variables are mostly invisible to the debugger even when compiling without optimizations. This patch stores the address of the local stack base into an alloca, which can be referred to by the debug info and is available throughout the function. This adds one extra pointer-sized alloca to each stack frame (but mem2reg can optimize it away again when optimizations are enabled, yielding roughly the same debug info quality as before in optimized code). rdar://problem/30433661 Differential Revision: https://reviews.llvm.org/D41034 llvm-svn: 320415
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-111-2/+17
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320407
* [MSan] Hotfix compilationAlexander Potapenko2017-12-111-2/+2
| | | | | | | For some reason the override directives got removed in r320373. I suspect this to be an unwanted effect of clang-format. llvm-svn: 320381
* [MSan] introduce getShadowOriginPtr(). NFC.Alexander Potapenko2017-12-111-129/+191
| | | | | | | | | | | | | | This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and origin pointers for an address as a Value pair. The existing callers of getShadowPtr() and getOriginPtr() are updated to use getShadowOriginPtr(). The rationale for this change is to simplify KMSAN instrumentation implementation. In KMSAN origins tracking is always enabled, and there's no direct mapping between the app memory and the shadow/origin pages. Both the shadow and the origin pointer for a given address are obtained by calling a single runtime hook from the instrumentation, therefore it's easier to work with those pointers together. Reviewed at https://reviews.llvm.org/D40835. llvm-svn: 320373
* [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) callSanjay Patel2017-12-101-14/+11
| | | | | | | Follow-up for a bug that's similar to: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320312
* [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)Sanjay Patel2017-12-101-1/+6
| | | | | | | This should fix the larger problem with sqrt shown in: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320310
* [PGO] change arg type to uint64_t to match member field typeXinliang David Li2017-12-101-2/+2
| | | | llvm-svn: 320285
* [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)Simon Pilgrim2017-12-091-6/+5
| | | | | | Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.) llvm-svn: 320270
* [InlineFunction] Set debug loc for call to forward varargs.Florian Hahn2017-12-091-0/+1
| | | | | | | | | | | | Reviewers: aprantl, dblaikie, rnk Reviewed By: rnk Subscribers: eraman, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D40432 llvm-svn: 320252
* Register NetBSD/x86_64 in MemorySanitizer.cppKamil Rytarowski2017-12-091-0/+22
| | | | | | | | | | | | | | | | | | | Summary: Reuse the Linux new mapping as it is. Sponsored by <The NetBSD Foundation> Reviewers: joerg, eugenis, vitalybuka Reviewed By: vitalybuka Subscribers: llvm-commits, #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D41022 llvm-svn: 320219
* Hardware-assisted AddressSanitizer (llvm part).Evgeniy Stepanov2017-12-096-2/+291
| | | | | | | | | | | | | | | | | | | | | Summary: This is LLVM instrumentation for the new HWASan tool. It is basically a stripped down copy of ASan at this point, w/o stack or global support. Instrumenation adds a global constructor + runtime callbacks for every load and store. HWASan comes with its own IR attribute. A brief design document can be found in clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier). Reviewers: kcc, pcc, alekseyshl Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D40932 llvm-svn: 320217
* Generalize llvm::replaceDbgDeclare and actually support the use-case thatAdrian Prantl2017-12-083-6/+10
| | | | | | is mentioned in the documentation (inserting a deref before the plus_uconst). llvm-svn: 320203
* [CodeExtractor] Add debug locations for new call and branch instrs.Florian Hahn2017-12-081-1/+24
| | | | | | | | | | | | | | | | | | | | | | | Summary: If a partially inlined function has debug info, we have to add debug locations to the call instruction calling the outlined function. We use the debug location of the first instruction in the outlined function, as the introduced call transfers control to this statement and there is no other equivalent line in the source code. We also use the same debug location for the branch instruction added to jump from artificial entry block for the outlined function, which just jumps to the first actual basic block of the outlined function. Reviewers: davide, aprantl, rriddle, dblaikie, danielcdh, wmi Reviewed By: aprantl, rriddle, danielcdh Subscribers: eraman, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D40413 llvm-svn: 320199
* Revert r320104: infinite loop profiling bug fixXinliang David Li2017-12-082-32/+38
| | | | | | | | | | | Causes unexpected memory issue with New PM this time. The new PM invalidates BPI but not BFI, leaving the reference to BPI from BFI invalid. Abandon this patch. There is a more general solution which also handles runtime infinite loop (but not statically). llvm-svn: 320180
* [JumpThreading] Minor comment cleanup. NFC. (test commit)Brian M. Rzycki2017-12-081-2/+2
| | | | llvm-svn: 320179
* [InstCombine] PR35354: Convert store(bitcast, load bitcast (select (Cond, ↵Alexey Bataev2017-12-081-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | &V1, &V2)) --> store (, load (select(Cond, load &V1, load &V2))) Summary: If we have the code like this: ``` float a, b; a = std::max(a ,b); ``` it is converted into something like this: ``` %call = call dereferenceable(4) float* @_ZSt3maxIfERKT_S2_S2_(float* nonnull dereferenceable(4) %a.addr, float* nonnull dereferenceable(4) %b.addr) %1 = bitcast float* %call to i32* %2 = load i32, i32* %1, align 4 %3 = bitcast float* %a.addr to i32* store i32 %2, i32* %3, align 4 ``` After inlinning this code is converted to the next: ``` %1 = load float, float* %a.addr %2 = load float, float* %b.addr %cmp.i = fcmp fast olt float %1, %2 %__b.__a.i = select i1 %cmp.i, float* %a.addr, float* %b.addr %3 = bitcast float* %__b.__a.i to i32* %4 = load i32, i32* %3, align 4 %5 = bitcast float* %arrayidx to i32* store i32 %4, i32* %5, align 4 ``` This pattern is not recognized as minmax pattern. Patch solves this problem by converting sequence ``` store (bitcast, (load bitcast (select ((cmp V1, V2), &V1, &V2)))) ``` to a sequence ``` store (,load (select((cmp V1, V2), &V1, &V2))) ``` After this the code is recognized as minmax pattern. Reviewers: RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40304 llvm-svn: 320157
* [PowerPC][asan] Update asan to handle changed memory layouts in newer kernelsBill Seurer2017-12-071-1/+1
| | | | | | | | | | | | | | | In more recent Linux kernels with 47 bit VMAs the layout of virtual memory for powerpc64 changed causing the address sanitizer to not work properly. This patch adds support for 47 bit VMA kernels for powerpc64 and fixes up test cases. https://reviews.llvm.org/D40907 There is an associated patch for compiler-rt. Tested on several 4.x and 3.x kernel releases. llvm-svn: 320109
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