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llvm-svn: 108139
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x) ^ z which is one instruction shorter. (PR6773)
before:
%and = and i32 %y, %x
%neg = xor i32 %x, -1
%and4 = and i32 %z, %neg
%xor = xor i32 %and4, %and
after:
%xor1 = xor i32 %z, %y
%and2 = and i32 %xor1, %x
%xor = xor i32 %and2, %z
llvm-svn: 108136
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llvm-svn: 100859
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parts of the cmp|cmp and cmp&cmp folding logic wasn't prepared for vectors
(unrelated to the bug but noticed while in the code) and the code was
*definitely* not safe to use by the (cast icmp)|(cast icmp) handling logic
that I added in r95855. Fix all this up by changing the various routines
to more consistently use IRBuilder and not pass in the I which had the wrong
type.
llvm-svn: 97801
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compares, noticed by inspection.
llvm-svn: 97795
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long test(long x) { return (x & 123124) | 3; }
Currently compiles to:
_test:
orl $3, %edi
movq %rdi, %rax
andq $123127, %rax
ret
This is because instruction and DAG combiners canonicalize
(or (and x, C), D) -> (and (or, D), (C | D))
However, this is only profitable if (C & D) != 0. It gets in the way of the
3-addressification because the input bits are known to be zero.
llvm-svn: 97616
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and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
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isInteger, we now have isFloatTy and isIntegerTy. Requested by Chris!
llvm-svn: 96223
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what it does. Enhance it to return false to optimizing vector
sign extensions from vector comparisions, which is the idiom used
to get a splatted vector for a vector comparison.
Doing this breaks vector-casts.ll, add some compensating
transformations to handle the important case they cover without
depending on this canonicalization.
This fixes rdar://7434900 a serious pessimization of vector compares.
llvm-svn: 95855
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llvm-svn: 95781
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llvm-svn: 95643
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xform.
llvm-svn: 95642
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xform it is checking to actually pass. There is no need to match
m_SelectCst<0, -1> since instcombine canonicalizes that into not(sext).
Add matches for sext(not(x)) in addition to not(sext(x)).
llvm-svn: 95420
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for vectors. Codegen is generating awful code or segfaulting
in various cases (e.g. PR6204).
llvm-svn: 95058
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"sext cond" instead of a select. This simplifies some instcombine
code, matches the policy for zext (cond ? 1 : 0 -> zext), and allows
us to generate better code for a testcase on ppc.
llvm-svn: 94339
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Evans!
llvm-svn: 93884
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good code on PR4216:
_test_bitfield: ## @test_bitfield
orl $32962, %edi
movl $4294941946, %eax
andq %rdi, %rax
ret
instead of:
_test_bitfield:
movl $4294941696, %ecx
movl %edi, %eax
orl $194, %edi
orl $32768, %eax
andq $250, %rdi
andq %rax, %rcx
movq %rdi, %rax
orq %rcx, %rax
ret
Evan is looking into the remaining andq+imm -> andl optimization.
llvm-svn: 93147
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it does make sense to keep them together, at least for now.
llvm-svn: 92711
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