summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* MCObjectStreamer: assign MCSymbols in the dummy fragment to offset 0.James Y Knight2019-11-161-2/+1
| | | | | | | | | | | | | | | | | In MCObjectStreamer, when there is no current fragment, initially symbols are created in a "pending" state and assigned to a dummy empty fragment. Previously, they were not being assigned an offset, and thus evaluateAbsolute would fail if trying to evaluate an expression 'a - b', where both 'a' and 'b' were in this pending state. Also slightly refactored the EmitLabel overload which takes an MCFragment for clarity. Fixes: https://llvm.org/PR41825 Differential Revision: https://reviews.llvm.org/D70062
* AMDGPU/SILoadStoreOptimizer: fix a likely bug introduced recentlyNicolai Hähnle2019-11-161-2/+2
| | | | | | | | | | | | | | | | | Summary: We should check for same instruction class before checking whether they have the same base address, else we might iterate out of bounds of a MachineInstr operands list. The InstClass check is also cheaper. This was introduced in SVN r373630. Reviewers: tstellar Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68690
* [RISCV] Handle variable sized objects with the stack need to be realignedShiva Chen2019-11-165-12/+44
| | | | Differential Revision: https://reviews.llvm.org/D68979
* [WebAssembly] Fix miscompile of select with andThomas Lively2019-11-151-7/+0
| | | | | | | | | | | | | | | | | Summary: Rolls back the remaining bad optimizations introduced in eb15d00193f. Some of them were already rolled back in e661f946a7db and this finishes the job. Fixes https://bugs.llvm.org/show_bug.cgi?id=44012. Reviewers: dschuff, aheejin Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70347
* [mips] Enable `la` pseudo instruction on 64-bit arch.Simon Atanasyan2019-11-151-5/+1
| | | | | | | This patch makes LLVM compatible with GAS. It accepts `la` pseudo instruction on arch with 64-bit pointers and just shows a warning. Differential Revision: https://reviews.llvm.org/D70202
* [mips] Do not emit R_MIPS_JALR for sym+offset in case of O32 ABISimon Atanasyan2019-11-151-1/+14
| | | | | | | | | | O32 ABI uses relocations in REL format. Relocation's addend is written in place. R_MIPS_JALR relocation points to the `jalr` instruction which does not have a place to store the relocation addend. So it's impossible to save non-zero "offset". This patch blocks emission of `R_MIPS_JALR` relocations in such cases. Differential Revision: https://reviews.llvm.org/D70201
* Add read-only data assembly writing for aixdiggerlin2019-11-151-1/+3
| | | | | | | | | | SUMMARY: The patch will emit read-only variable assembly code for aix. Reviewers: daltenty,Xiangling_Liao Subscribers: rupprecht, seiyai,hiraditya Differential Revision: https://reviews.llvm.org/D70182
* [ARM,MVE] Add reversed isel patterns for MVE `vcmp qN,rN`Simon Tatham2019-11-151-13/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: As well as vector/vector compare instructions, MVE also has a family of comparisons taking a vector and a scalar, which compare every lane of the vector against the same value. We generate those at isel time using isel patterns that match `(ARMvcmp vector, (ARMvdup scalar))`. This commit adds corresponding patterns for the operand-reversed form `(ARMvcmp (ARMvdup scalar), vector)`, with condition codes swapped as necessary. That way, we can still generate the vector/scalar compare instruction if the IR happens to have been rearranged to put the operands the other way round, which can happen in some optimization phases. Previously, a vcmp the other way round was handled by emitting a `vdup` instruction to //explicitly// replicate the scalar input into a vector, and then doing a vector/vector comparison. I haven't added a new test, because it turned out that several existing tests were already exhibiting that failure mode. So just updating the expected output in the existing MVE codegen tests demonstrates what's been improved. Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70296
* [AMDGPU] Lower llvm.amdgcn.s.buffer.load.v3[i|f]32Piotr Sobczak2019-11-151-6/+24
| | | | | | | | | | Summary: Add lowering support for 32-bit vec3 variant of s.buffer.load intrinsic. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70118
* [ARM][MVE] tail-predicationSjoerd Meijer2019-11-151-0/+3
| | | | | | | This is a follow up of d90804d, to also flag fmcp instructions as instructions that we do not support in tail-predicated vector loops. Differential Revision: https://reviews.llvm.org/D70295
* [MIPS GlobalISel] Select andi, ori and xoriPetar Avramovic2019-11-151-3/+6
| | | | | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates. Change immZExt16 with imm32ZExt16 for andi, ori and xori. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi, respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero extending 16 low bits of imm is equal to imm. Large number of test changes comes from zero extending of small types which is transformed into 'and' with bitmask in legalizer. Differential Revision:https://reviews.llvm.org/D70185
* [MIPS GlobalISel] Select addiuPetar Avramovic2019-11-151-1/+2
| | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immSExt16 for 32-bit immediates. Change immSExt16 with imm32SExt16 for addiu. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_ADD into ADDIu when 32-bit imm satisfies imm32SExt16 predicate: sign extending 16 low bits of imm is equal to imm. Differential Revision: https://reviews.llvm.org/D70184
* AMDGPU: Change boolean content type to 0 or 1Matt Arsenault2019-11-154-8/+15
| | | | | | | | The usage of target boolean checks is overly inflexible, since sext and zext of a compare are equally cheap. The choice is arbitrary, but using 0/1 to some degree is the choice of lower resistance since that's what most targets use. This enables a few combines that don't bother to support ZeroOrNegativeOneBooleanContent.
* AMDGPU: Try to commute sub of boolean extMatt Arsenault2019-11-151-3/+26
| | | | Avoids another regression in a future patch.
* GlobalISel: Lower s1 source G_SITOFP/G_UITOFPMatt Arsenault2019-11-153-48/+2
|
* [WinEH] Fix the wrong alignment orientation during calculating EH frame.Wang, Pengfei2019-11-151-1/+1
| | | | | | | | | | | | Summary: This is a bug fix for further issues in PR43585. Reviewers: rnk, RKSimon, craig.topper, andrew.w.kaylor Subscribers: hiraditya, llvm-commits, annita.zhang Tags: #llvm Differential Revision: https://reviews.llvm.org/D70224
* Add missing includes needed to prune LLVMContext.h include, NFCReid Kleckner2019-11-143-0/+3
| | | | | These are a pre-requisite to removing #include "llvm/Support/Options.h" from LLVMContext.h: https://reviews.llvm.org/D70280
* [Hexagon] Validate the iterators before converting them to mux.Sumanth Gundapaneni2019-11-141-2/+8
| | | | | | The conditional instructions that are translated to mux instructions are deleted and the iterators to these deleted instructions are being used later. This patch fixed this issue.
* [RISCV] Use addi rather than add x0Sam Elliott2019-11-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The RISC-V backend used to generate `add <reg>, x0, <reg>` in a few instances. It seems most places no longer generate this sequence. This is semantically equivalent to `addi <reg>, <reg>, 0`, but the latter has the advantage of being noted to be the canonical instruction to be used for moves (which microarchitectures can and should recognise as such). The changed testcases use instruction aliases - `mv <reg>, <reg>` is an alias for `addi <reg>, <reg>, 0`. Reviewers: luismarques Reviewed By: luismarques Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70124
* [RISCV] Fix wrong CFI directivesLuís Marques2019-11-141-55/+0
| | | | | | | | | | | | | Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723
* ARM: allow rewriting frame indexes for all prefetch variants.Tim Northover2019-11-141-0/+14
| | | | | For some reason we could handle PLD but not PLDW or PLI, but all of them can potentially refer to the stack region (if weirdly for PLI).
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-141-1/+1
|
* Fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-142-6/+5
|
* Hexagon - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-144-6/+6
|
* MSP430 - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-143-21/+18
|
* [AArch64][SVE] Implement floating-point comparison & reduction intrinsicsKerry McLaughlin2019-11-142-16/+28
| | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - fadda & faddv - fminv, fmaxv, fminnmv & fmaxnmv - facge & facgt - fcmp[eq|ge|gt|ne|uo] Reviewers: sdesmalen, huntergr, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69858
* [mips][NFC] Remove old FIXME commentMiloš Stojanović2019-11-141-1/+0
| | | | | | This was fixed in rL229595 but this comment was missed. Differential Revision: https://reviews.llvm.org/D70231
* [AArch64][SVE] Implement remaining floating-point arithmetic intrinsicsKerry McLaughlin2019-11-142-19/+40
| | | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - fabs & fneg - fexpa - frint[a|i|m|n|p|x|z] - frecpe, frecps & frecpx - fsqrt, frsqrte & frsqrts Reviewers: huntergr, sdesmalen, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69800
* [AArch64][SVE] Implement additional floating-point arithmetic intrinsicsKerry McLaughlin2019-11-143-38/+104
| | | | | | | | | | | | | | | | | | | Summary: Adds intrinsics for the following: - ftssel - fcadd, fcmla - fmla, fmls, fnmla, fnmls - fmad, fmsb, fnmad, fnmsb Reviewers: sdesmalen, huntergr, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69707
* [AArch64][DebugInfo] Fix incorrect call site param value produced by MOVZXiDjordje Todorovic2019-11-141-1/+1
| | | | | | This resolves the problem with the truncation of the immediate operand. Differential Revision: https://reviews.llvm.org/D70168
* [NFC] Fix typo in ARMBaseRegisterInfoAnna Welker2019-11-141-1/+1
|
* [mips] Use local variable to escape repetitive calls of `getOpcode`. NFCSimon Atanasyan2019-11-141-13/+10
|
* [mips] Use isInt<> call instead of explicit range checking. NFCSimon Atanasyan2019-11-141-2/+1
|
* Move CodeGenFileType enum to Support/CodeGen.hReid Kleckner2019-11-131-3/+3
| | | | | | | Avoids the need to include TargetMachine.h from various places just for an enum. Various other enums live here, such as the optimization level, TLS model, etc. Data suggests that this change probably doesn't matter, but it seems nice to have anyway.
* Sink all InitializePasses.h includesReid Kleckner2019-11-1358-38/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file lists every pass in LLVM, and is included by Pass.h, which is very popular. Every time we add, remove, or rename a pass in LLVM, it caused lots of recompilation. I found this fact by looking at this table, which is sorted by the number of times a file was changed over the last 100,000 git commits multiplied by the number of object files that depend on it in the current checkout: recompiles touches affected_files header 342380 95 3604 llvm/include/llvm/ADT/STLExtras.h 314730 234 1345 llvm/include/llvm/InitializePasses.h 307036 118 2602 llvm/include/llvm/ADT/APInt.h 213049 59 3611 llvm/include/llvm/Support/MathExtras.h 170422 47 3626 llvm/include/llvm/Support/Compiler.h 162225 45 3605 llvm/include/llvm/ADT/Optional.h 158319 63 2513 llvm/include/llvm/ADT/Triple.h 140322 39 3598 llvm/include/llvm/ADT/StringRef.h 137647 59 2333 llvm/include/llvm/Support/Error.h 131619 73 1803 llvm/include/llvm/Support/FileSystem.h Before this change, touching InitializePasses.h would cause 1345 files to recompile. After this change, touching it only causes 550 compiles in an incremental rebuild. Reviewers: bkramer, asbirlea, bollu, jdoerfert Differential Revision: https://reviews.llvm.org/D70211
* [X86] Don't treat mxcsr as a register name when parsing MS inline assembly.Craig Topper2019-11-131-2/+3
| | | | | No instruction takes mxcsr as a an operand so we should always treat it as an identifier name.
* [X86] Don't set the operation action for i16 SINT_TO_FP to Promote just ↵Craig Topper2019-11-131-3/+9
| | | | | | | because SSE1 is enabled. Instead do custom promotion in the handler so that we can still allow i16 to be used with fp80. And f64 without sse2.
* [X86] Fix typo in comment. NFCCraig Topper2019-11-131-1/+1
|
* [X86] Move all the FP_TO_XINT/XINT_TO_FP setOperationActions into the same ↵Craig Topper2019-11-131-41/+28
| | | | | | | | | !useSoftFloat block. Qualify all of the Promote actions for these with !useSoftFloat too. NFCI The Promote action doesn't apply until LegalizeDAG. By the time we get there, we would have already softened all the FP operations if useSoftFloat was true. So there wouldn't be any operation left to Promote.
* [mips] Reduce number of nested `if` statements. NFCSimon Atanasyan2019-11-131-8/+5
|
* [mips] Add tests to check `jal sym+offset`. NFCSimon Atanasyan2019-11-131-2/+0
|
* [LiveInterval] Allow updating subranges with slightly out-dated IRQuentin Colombet2019-11-132-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During register coalescing, we update the live-intervals on-the-fly. To do that we are in this strange mode where the live-intervals can be slightly out-of-sync (more precisely they are forward looking) compared to what the IR actually represents. This happens because the register coalescer only updates the IR when it is done with updating the live-intervals and it has to do it this way because updating the IR on-the-fly would actually clobber some information on how the live-ranges that are being updated look like. This is problematic for updates that rely on the IR to accurately represents the state of the live-ranges. Right now, we have only one of those: stripValuesNotDefiningMask. To reconcile this need of out-of-sync IR, this patch introduces a new argument to LiveInterval::refineSubRanges that allows the code doing the live range updates to reason about how the code should look like after the coalescer will have rewritten the registers. Essentially this captures how a subregister index with be offseted to match its position in a new register class. E.g., let say we want to merge: V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32> We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32> overlap, i.e., by choosing a class where we can find "offset + 1 == 3". Put differently we align V2's sub3 with V1's sub1: V2: sub0 sub1 sub2 sub3 V1: <offset> sub0 sub1 This offset will look like a composed subregidx in the the class: V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> => V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> Now if we didn't rewrite the uses and def of V1, all the checks for V1 need to account for this offset to match what the live intervals intend to capture. Prior to this patch, we would fail to recognize the uses and def of V1 and would end up with machine verifier errors: No live segment at def. This could lead to miscompile as we would drop some live-ranges and thus, miss some interferences. For this problem to trigger, we need to reach stripValuesNotDefiningMask while having a mismatch between the IR and the live-ranges (i.e., we have to apply a subreg offset to the IR.) This requires the following three conditions: 1. An update of overlapping subreg lanes: e.g., dsub0 == <ssub0, ssub1> 2. An update with Tuple registers with a possibility to coalesce the subreg index: e.g., v1.dsub_1 == v2.dsub_3 3. Subreg liveness enabled. looking at the IR to decide what is alive and what is not, i.e., calling stripValuesNotDefiningMask. coalescer maintains for the live-ranges information. None of the targets that currently use subreg liveness (i.e., the targets that fulfill #3, Hexagon, AMDGPU, PowerPC, and SystemZ IIRC) expose #1 and and #2, so this patch also artificial enables subreg liveness for ARM, so that a nice test case can be attached.
* [AArch64][v8.3a] Add missing imp-defs on RETA*.Ahmed Bougacha2019-11-131-0/+1
| | | | | | | | | | | | | RETA always implicitly uses LR, unlike RET which merely has an alias that defaults it to LR. Additionally, RETA implicitly uses SP as well, which it uses as a discriminator to authenticate LR. This isn't usually noticeable, because RET_ReallyLR is used in most of the backend. However, the post-RA scheduler, if enabled, will cause miscompiles if the imp-uses are missing. While there, fix a typo in the lone affected testcase.
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-131-0/+3
| | | | | | The instruction definition has been retroactively expanded to allow for an alias for '[xN, 0]!' as '[xN]!'. That wouldn't make sense on LDR, but does for LDRA.
* Fix comment spelling {addresing -> addressing} (NFC)Matthew Malcomson2019-11-131-1/+1
|
* PowerPC - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-133-7/+7
|
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
|
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
|
* Fix uninitialized variable warning. NFCI.Simon Pilgrim2019-11-131-1/+1
|
* Sparc - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-11-133-3/+3
|
OpenPOWER on IntegriCloud