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* [SystemZ] Use SLLK, SRLK and SRAK for codegenRichard Sandiford2013-07-193-5/+73
| | | | | | This patch uses the instructions added in r186680 for codegen. llvm-svn: 186681
* [SystemZ] Start adding z196 and zEC12 supportRichard Sandiford2013-07-196-20/+58
| | | | | | | | | | | | This first step just adds definitions for SLLK, SRLK and SRAK. The next patch will actually make use of them during codegen. insn-bad.s tests that some form of error is reported when using these instructions on z10. More work is needed to get the "instruction requires: distinct-ops" that we'd ideally like, so I've stubbed that part out for now. I'll come back and make it mandatory once the necessary changes are in. llvm-svn: 186680
* [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.Akira Hatanaka2013-07-192-15/+2
| | | | | | No functionality change. llvm-svn: 186642
* ARM: Make sure the instruction alias for PLI uses the right subtarget features.Tilmann Scheller2013-07-181-1/+3
| | | | | | | | PLI requires both the Thumb2 and the ARMv7 feature. Related to <rdar://problem/14403733>. llvm-svn: 186620
* R600/SI: Fix crash with VSELECTTom Stellard2013-07-182-1/+13
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=66175 llvm-svn: 186616
* R600/SI: Add support for v2f32 loadsTom Stellard2013-07-183-1/+5
| | | | llvm-svn: 186615
* R600/SI: Add support for v2f32 storesTom Stellard2013-07-182-0/+6
| | | | llvm-svn: 186614
* R600: Expand VSELECT for all typesTom Stellard2013-07-182-3/+3
| | | | llvm-svn: 186613
* Change 'n' to 'N' to keep consistent with other instructions.Joey Gouly2013-07-181-4/+4
| | | | llvm-svn: 186576
* [ARMv8] Add NEON instructions VCVT{A, N, P, M}.Joey Gouly2013-07-182-0/+64
| | | | llvm-svn: 186574
* [SystemZ] Use RNSBGRichard Sandiford2013-07-182-21/+67
| | | | | | This should be the last of the R.SBG patches for now. llvm-svn: 186573
* Add Thumb tests for the ARMv8 FP instructions that I recently added.Joey Gouly2013-07-181-2/+2
| | | | | | Also, fix the namespace for two instructions that I missed previously. llvm-svn: 186572
* [SystemZ] Generalize RxSBG SRA caseRichard Sandiford2013-07-181-27/+36
| | | | | | | | | The original code only folded SRA into ROTATE ... SELECTED BITS if there was no outer shift. This patch splits out that check and generalises it slightly. The extra cases aren't really that interesting, but this is paving the way for RNSBG support. llvm-svn: 186571
* [SystemZ] Use RXSBGRichard Sandiford2013-07-181-11/+16
| | | | | | Extend the previous R.SBG patches to handle XORs. llvm-svn: 186570
* [SystemZ] Rename and formatting fixesRichard Sandiford2013-07-181-64/+61
| | | | | | | | | | | | In hindsight, using "RISBG" for something that can be any type of R.SBG instruction was a bit confusing, so this renames it to RxSBG. That might not be the best choice either, since there is an instruction called RXSBG, but hopefully the lower-case letter stands out enough. While there I fixed a couple of GNUisms that had crept in -- sorry about that! llvm-svn: 186569
* Remove the extra leading 0 from VMAXNMND.Joey Gouly2013-07-181-1/+1
| | | | | | | | The N3VDIntnp pattern takes bits<5> and I gave it 6 bits. Thanks to Jiangning Liu for spotting it! llvm-svn: 186568
* This patch extends mips register parsing methods to allow indexed register ↵Vladimir Medic2013-07-181-0/+12
| | | | | | parsing. The corresponding test cases are added to the patch. llvm-svn: 186567
* Fix copy and paste bug from r186491 to make v2f64 use MOVAPD/MOVUPD as it ↵Craig Topper2013-07-181-2/+2
| | | | | | should. llvm-svn: 186566
* PPC: Support dynamic allocas with large alignmentHal Finkel2013-07-182-27/+53
| | | | | | | | | | | | | | | Support for dynamic stack alignments in the PPC backend has been unfinished, in part because it depends on dynamic stack realignment (which I only just recently implemented fully). Now we can also support dynamic allocas with higher than the default target stack alignment (16 bytes). In order to round-up the requested size to the maximum requested alignment, we need an additional register to hold the rounded-up size. We're already using one scavenged register to hold the previous stack-pointer value (which needs to be stored with the signal-safe stdux update), and so when we have dynamic allocas and a large alignment, we allocate two emergency spill slots for the scavenger. llvm-svn: 186562
* PPC: Add base-pointer support to builtin setjmp/longjmpHal Finkel2013-07-175-41/+72
| | | | | | | | | | | | | | | | | | First, this changes the base-pointer implementation to remove an unnecessary complication (and one that is incompatible with how builtin SjLj is implemented): instead of using r31 as the base pointer when it is not needed as a frame pointer, now the base pointer will always be r30 when needed. Second, we introduce another pseudo register, BP, which is used just like the FP pseudo register to refer to the base register before we know for certain what register it will be. Third, we now save BP into the jmp_buf, and restore r30 from that slot in longjmp. If the function that called setjmp did not use a base pointer, then r30 will be overwritten by the setjmp-calling-function's restore code. FP restoration (which is restored into r31) works the same way. llvm-svn: 186545
* Silencing an MSVC warning about signed vs unsigned comparison mismatches.Aaron Ballman2013-07-171-1/+1
| | | | llvm-svn: 186529
* [mips] Use "foreach" loop to make register definitions more concise.Akira Hatanaka2013-07-171-80/+9
| | | | llvm-svn: 186528
* This patch checks for valid mnemonics at the beginning of parseInstruction ↵Vladimir Medic2013-07-171-0/+5
| | | | | | method, thus giving the user the right error message for non-existing instructions. llvm-svn: 186512
* Implement eret and deret(return from exception) instructions for Mips. Test ↵Vladimir Medic2013-07-172-0/+21
| | | | | | examples are given. llvm-svn: 186507
* [ARMv8] Add support for the NEON instructions vmaxnm/vminnm.Joey Gouly2013-07-175-0/+119
| | | | | | | This adds a new class for non-predicable NEON instructions and a new DecoderNamespace for v8 NEON instructions. llvm-svn: 186504
* [XCore] Ensure implicit operands aren't lost on the return instruction.Richard Osborne2013-07-171-1/+3
| | | | | | Patch by Robert Lytton. llvm-svn: 186500
* Teach x86 fast-isel to use AVX opcodes for vector stores when AVX is enabled.Craig Topper2013-07-171-6/+6
| | | | llvm-svn: 186496
* Make x86 fast-isel correctly choose between aligned and unaligned operations ↵Craig Topper2013-07-171-12/+28
| | | | | | for vector stores. Fixes PR16640. llvm-svn: 186491
* Fix ARMFastISel::ARMEmitIntExt shift emissionJF Bastien2013-07-171-30/+52
| | | | | | | | My patch 'r183551 - ARM FastISel integer sext/zext improvements' was incorrect when emitting ARM register-immediate ASR, LSL, LSR instructions: they are pseudo-instructions in ARMInstrInfo.td and I should have used MOVsi instead. This is not an issue when code is generated through a .s file, but is an issue when generated straight to a .o (-filetype=obj). llvm-svn: 186489
* PPC: Add CTR-register clobber to builtin setjmpHal Finkel2013-07-173-0/+9
| | | | | | | | | | | | | Because the builtin longjmp implementation uses a CTR-based indirect jump, when the control flow arrives at the builtin setjmp call, the CTR register has necessarily been clobbered. Correspondingly, this adds CTR to the list of implicit definitions of the builtin setjmp pseudo instruction. We don't need to add CTR to the implicit definitions of builtin longjmp because, even though it does clobber the CTR register, the control flow cannot return to inside the loop unless there is also a builtin setjmp call. llvm-svn: 186488
* PPC: Implement base pointer and stack realignmentHal Finkel2013-07-175-41/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This builds on some frame-lowering code that has existed since 2005 (r24224) but was disabled in 2008 (r48188) because it needed base pointer support to function correctly. This implementation follows the strategy suggested by Dale Johannesen in r48188 where the following comment was added: This does not currently work, because the delta between old and new stack pointers is added to offsets that reference incoming parameters after the prolog is generated, and the code that does that doesn't handle a variable delta. You don't want to do that anyway; a better approach is to reserve another register that retains to the incoming stack pointer, and reference parameters relative to that. And now we do exactly that. If we don't need a frame pointer, then we use r31 as a base pointer. If we do need a frame pointer, then we use r30 as a base pointer. The base pointer retains the value of the stack pointer before it was decremented in the prologue. We then use the base pointer to resolve all negative frame indicies. The basic scheme follows that for base pointers in the X86 backend. We use a base pointer when we need to dynamically realign the incoming stack pointer. This currently applies only to static objects (dynamic allocas with large alignments, and base-pointer support in SjLj lowering will come in future commits). llvm-svn: 186478
* Move string pointer from being a static class member to just a static global ↵Craig Topper2013-07-172-7/+2
| | | | | | in the one file its needed in. llvm-svn: 186476
* Related to r181161 - Indirect branches may not be the last branch in a basicLang Hames2013-07-161-0/+7
| | | | | | | | | | | | block. Blocks that have an indirect branch terminator, even if it's not the last terminator, should still be treated as unanalyzable. <rdar://problem/14437274> Reducing a useful regression test case is proving difficult - I hope to have one soon. llvm-svn: 186461
* ARM: Add support for the Thumb2 PLI alternate literal form.Tilmann Scheller2013-07-161-0/+3
| | | | | | | | | | This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>] See A8.8.129 in the ARM ARM (DDI 0406C.b). Fixes <rdar://problem/14403733>. llvm-svn: 186459
* Add a wrapper for open.Rafael Espindola2013-07-161-1/+1
| | | | | | | This centralizes the handling of O_BINARY and opens the way for hiding more differences (like how open behaves with directories). llvm-svn: 186447
* [X86] Use min/max to optimze unsigend vector comparison on X86Juergen Ributzka2013-07-161-2/+22
| | | | | | | | | | | | | Use PMIN/PMAX for UGE/ULE vector comparions to reduce the number of required instructions. This trick also works for UGT/ULT, but there is no advantage in doing so. It wouldn't reduce the number of instructions and it would actually reduce performance. Reviewer: Ben radar:5972691 llvm-svn: 186432
* Test commit to verify write access.Juergen Ributzka2013-07-161-0/+1
| | | | llvm-svn: 186429
* [XCore] Fix printing of inline asm operands.Richard Osborne2013-07-161-11/+7
| | | | | | | Previously an asm operand with no operand modifier would give the error "invalid operand in inline asm". llvm-svn: 186407
* ARM: allow printing of ARM atomic DAG nodes.Tim Northover2013-07-161-0/+13
| | | | | | | | We'd forgotten to provide string representations for the special ARMISD atomic nodes; this adds them in. No effect on CodeGen, just makes the output of "-view-whatever-dags" slightly more readable. llvm-svn: 186406
* [SystemZ] Use ROSBG and non-zero form of RISBG for OR nodesRichard Sandiford2013-07-161-1/+86
| | | | llvm-svn: 186405
* Fixing a buildbot failure:unused function.Vladimir Medic2013-07-161-14/+0
| | | | llvm-svn: 186403
* [SystemZ] Add MC support for R[NOX]SBGRichard Sandiford2013-07-161-0/+8
| | | | | | CodeGen support will come later. llvm-svn: 186401
* [SystemZ] Use RISBG for (shift (and ...))Richard Sandiford2013-07-161-97/+168
| | | | | | | Another patch in the series to make more use of R.SBG. This one extends r186072 and r186073 to handle cases where the AND is inside the shift. llvm-svn: 186399
* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-164-270/+242
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
* PPCJITInfo.cpp: Tweak r186252 with s/__ppc/__powerpc/ to work on ↵NAKAMURA Takumi2013-07-161-2/+2
| | | | | | | | powerpc-linux Fedora 12. g++ (GCC) 4.4.4 20100630 (Red Hat 4.4.4-10) llvm-svn: 186396
* ARM: implement ldrex, strex and clrex intrinsicsTim Northover2013-07-165-16/+131
| | | | | | | Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
* ARM EABI divmod supportRenato Golin2013-07-163-2/+87
| | | | | | | | | | | | This patch enables calls to __aeabi_idivmod when in EABI mode, by using the remainder value returned on registers (R1), enabled by the ARM triple "none-eabi". Note that Darwin and GNUEABI triples will continue lowering on GNU style, that is, using the stack for the remainder. Still need to add SREM/UREM support fix for 64-bit lowering. llvm-svn: 186390
* Add 'const' qualifiers to static const char* variables.Craig Topper2013-07-161-7/+7
| | | | llvm-svn: 186371
* PPC: Refactoring to support subtarget feature changingHal Finkel2013-07-152-37/+69
| | | | | | | | | This change mirrors the changes that were made to the X86 and ARM targets to support subtarget feature changing. As indicated in r182899, the mechanism is still undergoing revision, and so as with the X86 and ARM targets, there is no test case yet (there is no effective functionality change). llvm-svn: 186357
* Fix register subclass handling in PPCInstrInfo::insertSelectHal Finkel2013-07-151-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | PPCInstrInfo::insertSelect and PPCInstrInfo::canInsertSelect were computing the common subclass of the true and false inputs, and then selecting either the 32-bit or the 64-bit isel variant based on the result of calling PPC::GPRCRegClass.hasSubClassEq(RC) and PPC::G8RCRegClass.hasSubClassEq(RC) (where RC is the common subclass). Unfortunately, this is not quite right: if we have something like this: %vreg8<def> = SELECT_CC_I8 %vreg4<kill>, %vreg7<kill>, %vreg6<kill>, 76; G8RC_and_G8RC_NOX0:%vreg8 CRRC:%vreg4 G8RC_NOX0:%vreg7,%vreg6 then the common subclass of G8RC_and_G8RC_NOX0 and G8RC_NOX0 is G8RC_NOX0, and G8RC_NOX0 is not a subclass of G8RC (because it also contains the ZERO8 pseudo-register). As a result, we also need to check the common subclass against GPRC_NOR0 and G8RC_NOX0 explicitly. This had not been a problem for clients of insertSelect that called canInsertSelect first (because it had a compensating mistake), but insertSelect is also used by the PPC pseudo-instruction expander, and this error was causing a problem in that context. This problem was found by csmith. llvm-svn: 186343
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